From xen-devel-bounces@lists.xensource.com Fri Nov 11 08:14:00 2011 Return-path: Envelope-to: www-data@lists.xensource.com Delivery-date: Fri, 11 Nov 2011 08:14:00 -0800 Received: from localhost ([127.0.0.1] helo=lists.colo.xensource.com) by lists.xensource.com with esmtp (Exim 4.43) id 1ROtjs-0006DB-Fl; Fri, 11 Nov 2011 08:14:00 -0800 Received: from mail27.messagelabs.com ([193.109.254.147]) by lists.xensource.com with esmtp (Exim 4.43) id 1ROtfX-0005UV-Ao; Fri, 11 Nov 2011 08:09:32 -0800 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-3.tower-27.messagelabs.com!1321027733!45555116!1 X-Originating-IP: [130.57.49.28] X-StarScan-Version: 6.4.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26685 invoked from network); 11 Nov 2011 16:08:53 -0000 Received: from nat28.tlf.novell.com (HELO nat28.tlf.novell.com) (130.57.49.28) by server-3.tower-27.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 11 Nov 2011 16:08:53 -0000 Received: from EMEA1-MTA by nat28.tlf.novell.com with Novell_GroupWise; Fri, 11 Nov 2011 16:09:26 +0000 Message-Id: <4EBD56C50200007800060781@nat28.tlf.novell.com> X-Mailer: Novell GroupWise Internet Agent 8.0.1 Date: Fri, 11 Nov 2011 16:09:25 +0000 From: "Jan Beulich" To: "xen-devel@lists.xensource.com" Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part765988A5.0__=" Cc: xen-ia64-devel@lists.xensource.com Subject: [Xen-devel] [PATCH] ia64: introduce atomic_{read,write}NN() X-BeenThere: xen-devel@lists.xensource.com X-Mailman-Version: 2.1.5 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part765988A5.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline These are required to be able to build certain portions of common code. Signed-off-by: Jan Beulich --- a/xen/include/asm-ia64/linux-xen/asm/atomic.h +++ b/xen/include/asm-ia64/linux-xen/asm/atomic.h @@ -24,12 +24,9 @@ typedef struct { volatile __s32 counter; typedef struct { volatile __s64 counter; } atomic64_t; =20 #ifndef XEN + #define ATOMIC_INIT(i) ((atomic_t) { (i) }) #define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) -#else -#define ATOMIC_INIT(i) { (i) } -#define ATOMIC64_INIT(i) { (i) } -#endif =20 #define atomic_read(v) ((v)->counter) #define atomic64_read(v) ((v)->counter) @@ -37,6 +34,55 @@ typedef struct { volatile __s64 counter; #define atomic_set(v,i) (((v)->counter) =3D (i)) #define atomic64_set(v,i) (((v)->counter) =3D (i)) =20 +#else + +#define ATOMIC_INIT(i) { (i) } +#define ATOMIC64_INIT(i) { (i) } + +#define build_atomic_read(tag, type) \ +static inline type atomic_read##tag(const volatile type *addr) \ +{ \ + type ret; \ + asm volatile("ld%2.acq %0 =3D %1" \ + : "=3Dr" (ret) \ + : "m" (*addr), "i" (sizeof(type))); \ + return ret; \ +} + +#define build_atomic_write(tag, type) \ +static inline void atomic_write##tag(volatile type *addr, type val) \ +{ \ + asm volatile("st%2.rel %0 =3D %1" \ + : "=3Dm" (*addr) \ + : "r" (val), "i" (sizeof(type))); \ +} + +build_atomic_read(8, uint8_t) +build_atomic_read(16, uint16_t) +build_atomic_read(32, uint32_t) +build_atomic_read(64, uint64_t) +build_atomic_read(_int, int) +build_atomic_read(_long, long) + +build_atomic_write(8, uint8_t) +build_atomic_write(16, uint16_t) +build_atomic_write(32, uint32_t) +build_atomic_write(64, uint64_t) +build_atomic_write(_int, int) +build_atomic_write(_long, long) + +#define _atomic_read(v) ((v).counter) +#define _atomic64_read(v) ((v).counter) +#define atomic_read(v) atomic_read_int(&((v)->counter)) +#define atomic64_read(v) atomic_read_long(&((v)->counter)) + +#define _atomic_set(v,i) (((v).counter) =3D (i)) +#define _atomic64_set(v,i) (((v).counter) =3D (i)) +#define atomic_set(v,i) atomic_write_int(&((v)->counter), = i) +#define atomic64_set(v,l) atomic_write_long(&((v)->counter), l) + +#endif + static __inline__ int ia64_atomic_add (int i, atomic_t *v) { @@ -59,7 +105,7 @@ ia64_atomic64_add (__s64 i, atomic64_t * =20 do { CMPXCHG_BUGCHECK(v); - old =3D atomic_read(v); + old =3D atomic64_read(v); new =3D old + i; } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) !=3D = old); return new; @@ -87,7 +133,7 @@ ia64_atomic64_sub (__s64 i, atomic64_t * =20 do { CMPXCHG_BUGCHECK(v); - old =3D atomic_read(v); + old =3D atomic64_read(v); new =3D old - i; } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) !=3D = old); return new; --=__Part765988A5.0__= Content-Type: text/plain; name="ia64-atomic-rw.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="ia64-atomic-rw.patch" ia64: introduce atomic_{read,write}NN()=0A=0AThese are required to be able = to build certain portions of common code.=0A=0ASigned-off-by: Jan Beulich = =0A=0A--- a/xen/include/asm-ia64/linux-xen/asm/atomic.h= =0A+++ b/xen/include/asm-ia64/linux-xen/asm/atomic.h=0A@@ -24,12 +24,9 @@ = typedef struct { volatile __s32 counter;=0A typedef struct { volatile = __s64 counter; } atomic64_t;=0A =0A #ifndef XEN=0A+=0A #define ATOMIC_INIT(= i) ((atomic_t) { (i) })=0A #define ATOMIC64_INIT(i) = ((atomic64_t) { (i) })=0A-#else=0A-#define ATOMIC_INIT(i) { = (i) }=0A-#define ATOMIC64_INIT(i) { (i) }=0A-#endif=0A =0A #define = atomic_read(v) ((v)->counter)=0A #define atomic64_read(v) = ((v)->counter)=0A@@ -37,6 +34,55 @@ typedef struct { volatile __s64 = counter;=0A #define atomic_set(v,i) (((v)->counter) =3D = (i))=0A #define atomic64_set(v,i) (((v)->counter) =3D (i))=0A = =0A+#else=0A+=0A+#define ATOMIC_INIT(i) { (i) }=0A+#define = ATOMIC64_INIT(i) { (i) }=0A+=0A+#define build_atomic_read(tag, = type) \=0A+static inline type atomic_read##tag(const volatile type *addr) = \=0A+{ \=0A+ type ret; \=0A+ asm volatile("ld%2.acq %0 =3D %1" \=0A+ = : "=3Dr" (ret) \=0A+ : "m" (*addr), "i" (sizeof(typ= e))); \=0A+ return ret; \=0A+}=0A+=0A+#define build_atomic_write(tag, = type) \=0A+static inline void atomic_write##tag(volatile type *addr, type = val) \=0A+{ \=0A+ asm volatile("st%2.rel %0 =3D %1" \=0A+ = : "=3Dm" (*addr) \=0A+ : "r" (val), "i" (sizeof(type)= )); \=0A+}=0A+=0A+build_atomic_read(8, uint8_t)=0A+build_atomic_read(16, = uint16_t)=0A+build_atomic_read(32, uint32_t)=0A+build_atomic_read(64, = uint64_t)=0A+build_atomic_read(_int, int)=0A+build_atomic_read(_long, = long)=0A+=0A+build_atomic_write(8, uint8_t)=0A+build_atomic_write(16, = uint16_t)=0A+build_atomic_write(32, uint32_t)=0A+build_atomic_write(64, = uint64_t)=0A+build_atomic_write(_int, int)=0A+build_atomic_write(_long, = long)=0A+=0A+#define _atomic_read(v) ((v).counter)=0A+#define = _atomic64_read(v) ((v).counter)=0A+#define atomic_read(v) = atomic_read_int(&((v)->counter))=0A+#define atomic64_read(v) atomic_read= _long(&((v)->counter))=0A+=0A+#define _atomic_set(v,i) (((v).counter) =3D = (i))=0A+#define _atomic64_set(v,i) (((v).counter) =3D (i))=0A+#define = atomic_set(v,i) atomic_write_int(&((v)->counter), i)=0A+#define = atomic64_set(v,l) atomic_write_long(&((v)->counter), l)=0A+=0A+#endif= =0A+=0A static __inline__ int=0A ia64_atomic_add (int i, atomic_t *v)=0A = {=0A@@ -59,7 +105,7 @@ ia64_atomic64_add (__s64 i, atomic64_t *=0A =0A do = {=0A CMPXCHG_BUGCHECK(v);=0A- old =3D atomic_read= (v);=0A+ old =3D atomic64_read(v);=0A new =3D = old + i;=0A } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t))= !=3D old);=0A return new;=0A@@ -87,7 +133,7 @@ ia64_atomic64_sub (__s64 = i, atomic64_t *=0A =0A do {=0A CMPXCHG_BUGCHECK(v);=0A- = old =3D atomic_read(v);=0A+ old =3D atomic64_read(v);= =0A new =3D old - i;=0A } while (ia64_cmpxchg(acq, v, old, = new, sizeof(atomic64_t)) !=3D old);=0A return new;=0A --=__Part765988A5.0__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=__Part765988A5.0__=-- From xen-devel-bounces@lists.xensource.com Fri Nov 11 08:18:14 2011 Return-path: Envelope-to: www-data@lists.xensource.com Delivery-date: Fri, 11 Nov 2011 08:18:14 -0800 Received: from localhost ([127.0.0.1] helo=lists.colo.xensource.com) by lists.xensource.com with esmtp (Exim 4.43) id 1ROtnx-00070t-Nk; Fri, 11 Nov 2011 08:18:13 -0800 Received: from mail174.messagelabs.com ([85.158.138.51]) by lists.xensource.com with esmtp (Exim 4.43) id 1ROtld-0006Wu-PO; Fri, 11 Nov 2011 08:15:51 -0800 X-Env-Sender: JBeulich@suse.com X-Msg-Ref: server-5.tower-174.messagelabs.com!1321028145!1210994!1 X-Originating-IP: [130.57.49.28] X-StarScan-Version: 6.4.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 25386 invoked from network); 11 Nov 2011 16:15:46 -0000 Received: from nat28.tlf.novell.com (HELO nat28.tlf.novell.com) (130.57.49.28) by server-5.tower-174.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 11 Nov 2011 16:15:46 -0000 Received: from EMEA1-MTA by nat28.tlf.novell.com with Novell_GroupWise; Fri, 11 Nov 2011 16:15:45 +0000 Message-Id: <4EBD583E0200007800060794@nat28.tlf.novell.com> X-Mailer: Novell GroupWise Internet Agent 8.0.1 Date: Fri, 11 Nov 2011 16:15:42 +0000 From: "Jan Beulich" To: "xen-devel@lists.xensource.com" Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartEFC0113E.0__=" Cc: xen-ia64-devel@lists.xensource.com Subject: [Xen-devel] ia64: fix the build X-BeenThere: xen-devel@lists.xensource.com X-Mailman-Version: 2.1.5 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartEFC0113E.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline This addresses all remaining build problems introduced over the last several months. Signed-off-by: Jan Beulich --- a/xen/arch/ia64/linux-xen/iosapic.c +++ b/xen/arch/ia64/linux-xen/iosapic.c @@ -275,12 +275,6 @@ set_rte (unsigned int gsi, unsigned int=20 iosapic_intr_info[vector].dest =3D dest; } =20 -static void -nop (struct irq_desc *desc) -{ - /* do nothing... */ -} - void kexec_disable_iosapic(void) { @@ -428,7 +422,7 @@ iosapic_end_level_irq (struct irq_desc * #define iosapic_shutdown_level_irq mask_irq #define iosapic_enable_level_irq unmask_irq #define iosapic_disable_level_irq mask_irq -#define iosapic_ack_level_irq nop +#define iosapic_ack_level_irq irq_actor_none =20 static hw_irq_controller irq_type_iosapic_level =3D { .typename =3D "IO-SAPIC-level", @@ -446,9 +440,9 @@ static hw_irq_controller irq_type_iosapi */ =20 static unsigned int -iosapic_startup_edge_irq (unsigned int irq) +iosapic_startup_edge_irq (struct irq_desc *desc) { - unmask_irq(irq); + unmask_irq(desc); /* * IOSAPIC simply drops interrupts pended while the * corresponding pin was masked, so we can't know if an @@ -458,23 +452,21 @@ iosapic_startup_edge_irq (unsigned int i } =20 static void -iosapic_ack_edge_irq (unsigned int irq) +iosapic_ack_edge_irq (struct irq_desc *desc) { - irq_desc_t *idesc =3D irq_descp(irq); - - move_irq(irq); + move_irq(idesc->irq); /* * Once we have recorded IRQ_PENDING already, we can mask the * interrupt for real. This prevents IRQ storms from unhandled * devices. */ - if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) =3D=3D (IRQ_PENDIN= G|IRQ_DISABLED)) - mask_irq(irq); + if ((desc->status & (IRQ_PENDING|IRQ_DISABLED)) =3D=3D (IRQ_PENDING= |IRQ_DISABLED)) + mask_irq(desc); } =20 #define iosapic_enable_edge_irq unmask_irq -#define iosapic_disable_edge_irq nop -#define iosapic_end_edge_irq nop +#define iosapic_disable_edge_irq irq_disable_none +#define iosapic_end_edge_irq irq_actor_none =20 static hw_irq_controller irq_type_iosapic_edge =3D { .typename =3D "IO-SAPIC-edge", --- a/xen/arch/ia64/linux-xen/irq_ia64.c +++ b/xen/arch/ia64/linux-xen/irq_ia64.c @@ -242,6 +242,16 @@ static struct irqaction __read_mostly ip }; #endif =20 +static hw_irq_controller irq_type_ia64_lsapic =3D { + .typename =3D "LSAPIC", + .startup =3D irq_startup_none, + .shutdown =3D irq_shutdown_none, + .enable =3D irq_enable_none, + .disable =3D irq_disable_none, + .ack =3D irq_actor_none, + .end =3D irq_actor_none +}; + void register_percpu_irq (ia64_vector vec, struct irqaction *action) { --- a/xen/arch/ia64/linux-xen/mca.c +++ b/xen/arch/ia64/linux-xen/mca.c @@ -428,9 +428,9 @@ void disable_irq_nosync(unsigned int irq return; =20 spin_lock_irqsave(&desc->lock, flags); - if (!desc->depth++) { + if (!desc->arch.depth++) { desc->status |=3D IRQ_DISABLED; - desc->handler->disable(irq); + desc->handler->disable(desc); } spin_unlock_irqrestore(&desc->lock, flags); } @@ -456,7 +456,7 @@ void enable_irq(unsigned int irq) return; =20 spin_lock_irqsave(&desc->lock, flags); - switch (desc->depth) { + switch (desc->arch.depth) { case 0: WARN_ON(1); break; @@ -468,11 +468,11 @@ void enable_irq(unsigned int irq) desc->status =3D status | IRQ_REPLAY; hw_resend_irq(desc->handler,irq); } - desc->handler->enable(irq); + desc->handler->enable(desc); /* fall-through */ } default: - desc->depth--; + desc->arch.depth--; } spin_unlock_irqrestore(&desc->lock, flags); } --- a/xen/arch/ia64/linux-xen/sn/kernel/irq.c +++ b/xen/arch/ia64/linux-xen/sn/kernel/irq.c @@ -72,6 +72,7 @@ void sn_intr_free(nasid_t local_nasid, i (u64) sn_irq_info->irq_cookie, 0, 0); } =20 +#ifndef XEN static unsigned int sn_startup_irq(unsigned int irq) { return 0; @@ -88,9 +89,16 @@ static void sn_disable_irq(unsigned int=20 static void sn_enable_irq(unsigned int irq) { } +#endif =20 +#ifdef XEN +static void sn_ack_irq(struct irq_desc *desc) +{ + unsigned int irq =3D desc->irq; +#else static void sn_ack_irq(unsigned int irq) { +#endif u64 event_occurred, mask; =20 irq =3D irq & 0xff; @@ -102,8 +110,14 @@ static void sn_ack_irq(unsigned int irq) move_native_irq(irq); } =20 +#ifdef XEN +static void sn_end_irq(struct irq_desc *desc) +{ + unsigned int irq =3D desc->irq; +#else static void sn_end_irq(unsigned int irq) { +#endif int ivec; u64 event_occurred; =20 @@ -224,13 +238,17 @@ static void sn_set_affinity_irq(unsigned static hw_irq_controller irq_type_sn =3D { #ifndef XEN .name =3D "SN hub", -#else - .typename =3D "SN hub", -#endif .startup =3D sn_startup_irq, .shutdown =3D sn_shutdown_irq, .enable =3D sn_enable_irq, .disable =3D sn_disable_irq, +#else + .typename =3D "SN hub", + .startup =3D irq_startup_none, + .shutdown =3D irq_shutdown_none, + .enable =3D irq_enable_none, + .disable =3D irq_disable_none, +#endif .ack =3D sn_ack_irq, .end =3D sn_end_irq, #ifndef XEN --- a/xen/arch/ia64/linux/Makefile +++ b/xen/arch/ia64/linux/Makefile @@ -9,7 +9,6 @@ obj-y +=3D efi_stub.o obj-y +=3D extable.o obj-y +=3D flush.o obj-y +=3D hpsim.o -obj-y +=3D irq_lsapic.o obj-y +=3D linuxextable.o obj-y +=3D machvec.o obj-y +=3D memcpy_mck.o --- a/xen/arch/ia64/linux/README.origin +++ b/xen/arch/ia64/linux/README.origin @@ -7,7 +7,6 @@ the instructions in the README there. efi_stub.S -> linux/arch/ia64/kernel/efi_stub.S extable.c -> linux/arch/ia64/mm/extable.c hpsim.S -> linux/arch/ia64/hp/sim/hpsim.S -irq_lsapic.c -> linux/arch/ia64/kernel/irq_lsapic.c linuxextable.c -> linux/kernel/extable.c machvec.c -> linux/arch/ia64/kernel/machvec.c numa.c -> linux/arch/ia64/mm/numa.c --- a/xen/arch/ia64/linux/irq_lsapic.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * LSAPIC Interrupt Controller - * - * This takes care of interrupts that are generated by the CPU's - * internal Streamlined Advanced Programmable Interrupt Controller - * (LSAPIC), such as the ITC and IPI interrupts. - * - * Copyright (C) 1999 VA Linux Systems - * Copyright (C) 1999 Walt Drummond - * Copyright (C) 2000 Hewlett-Packard Co - * Copyright (C) 2000 David Mosberger-Tang - */ - -#include -#include - -static unsigned int -lsapic_noop_startup (unsigned int irq) -{ - return 0; -} - -static void -lsapic_noop (unsigned int irq) -{ - /* nuthing to do... */ -} - -hw_irq_controller irq_type_ia64_lsapic =3D { - .typename =3D "LSAPIC", - .startup =3D lsapic_noop_startup, - .shutdown =3D lsapic_noop, - .enable =3D lsapic_noop, - .disable =3D lsapic_noop, - .ack =3D lsapic_noop, - .end =3D lsapic_noop -}; --- a/xen/arch/ia64/xen/dom0_ops.c +++ b/xen/arch/ia64/xen/dom0_ops.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include --- a/xen/arch/ia64/xen/domain.c +++ b/xen/arch/ia64/xen/domain.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include --- a/xen/arch/ia64/xen/fw_emul.c +++ b/xen/arch/ia64/xen/fw_emul.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include #include --- a/xen/arch/ia64/xen/hypercall.c +++ b/xen/arch/ia64/xen/hypercall.c @@ -70,7 +70,8 @@ static long __do_pirq_guest_eoi(struct d evtchn_unmask(pirq_to_evtchn(d, pirq)); spin_unlock(&d->event_lock); } - return pirq_guest_eoi(pirq); + pirq_guest_eoi(pirq_info(d, pirq)); + return 0; } =20 long do_pirq_guest_eoi(int pirq) --- a/xen/arch/ia64/xen/irq.c +++ b/xen/arch/ia64/xen/irq.c @@ -95,8 +95,11 @@ int __init init_irq_data(void) struct irq_desc *desc =3D irq_to_desc(irq); =20 desc->irq =3D irq; - init_one_irq_desc(desc); + if (init_one_irq_desc(desc)) + BUG(); } + + return 0; } =20 void __do_IRQ_guest(int irq); @@ -105,14 +108,14 @@ void __do_IRQ_guest(int irq); * Special irq handlers. */ =20 -static void ack_none(unsigned int irq) +static void ack_none(struct irq_desc *desc) { /* * 'what should we do if we get a hw irq event on an illegal vector'. * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ - printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, = smp_processor_id()); + printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", = desc->irq, smp_processor_id()); } =20 hw_irq_controller no_irq_type =3D { @@ -147,11 +150,11 @@ fastcall unsigned int __do_IRQ(unsigned=20 /* * No locking required for CPU-local interrupts: */ - desc->handler->ack(irq); + desc->handler->ack(desc); local_irq_enable(); desc->action->handler(irq, desc->action->dev_id, regs); local_irq_disable(); - desc->handler->end(irq); + desc->handler->end(desc); return 1; } =20 @@ -163,7 +166,7 @@ fastcall unsigned int __do_IRQ(unsigned=20 return 1; } =20 - desc->handler->ack(irq); + desc->handler->ack(desc); status =3D desc->status & ~IRQ_REPLAY; status |=3D IRQ_PENDING; /* we _want_ to handle it */ =20 @@ -215,7 +218,7 @@ out: * The ->end() handler has to deal with interrupts which got * disabled while the handler was running. */ - desc->handler->end(irq); + desc->handler->end(desc); spin_unlock(&desc->lock); =20 return 1; @@ -248,10 +251,10 @@ int setup_vector(unsigned int vector, st =20 *p =3D new; =20 - desc->depth =3D 0; + desc->arch.depth =3D 0; desc->status &=3D ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_GUEST); - desc->handler->startup(vector); - desc->handler->enable(vector); + desc->handler->startup(desc); + desc->handler->enable(desc); desc->arch.vector =3D vector; spin_unlock_irqrestore(&desc->lock,flags); =20 @@ -287,9 +290,9 @@ void __init release_irq_vector(unsigned=20 spin_lock_irqsave(&desc->lock, flags); clear_bit(vec, ia64_xen_vector); desc->action =3D NULL; - desc->depth =3D 1; + desc->arch.depth =3D 1; desc->status |=3D IRQ_DISABLED; - desc->handler->shutdown(vec); + desc->handler->shutdown(desc); desc->arch.vector =3D -1; spin_unlock_irqrestore(&desc->lock, flags); =20 @@ -336,7 +339,7 @@ static void _irq_guest_eoi(irq_desc_t *d clear_pirq_eoi(action->guest[i], vector); =20 desc->status &=3D ~(IRQ_INPROGRESS|IRQ_GUEST_EOI_PENDING); - desc->handler->enable(vector); + desc->handler->enable(desc); } =20 static struct timer irq_guest_eoi_timer[NR_IRQS]; @@ -383,7 +386,7 @@ void __do_IRQ_guest(int irq) if ( already_pending =3D=3D action->nr_guests ) { stop_timer(&irq_guest_eoi_timer[irq]); - desc->handler->disable(irq); + desc->handler->disable(desc); desc->status |=3D IRQ_GUEST_EOI_PENDING; for ( i =3D 0; i < already_pending; ++i ) { @@ -417,31 +420,28 @@ static int pirq_acktype(int irq) return ACKTYPE_NONE; } =20 -int pirq_guest_eoi(struct pirq *pirq) +void pirq_guest_eoi(struct pirq *pirq) { irq_desc_t *desc; irq_guest_action_t *action; =20 - desc =3D &irq_desc[irq]; + desc =3D &irq_desc[pirq->pirq]; spin_lock_irq(&desc->lock); action =3D (irq_guest_action_t *)desc->action; =20 if ( action->ack_type =3D=3D ACKTYPE_NONE ) { ASSERT(!pirq->masked); - stop_timer(&irq_guest_eoi_timer[irq]); + stop_timer(&irq_guest_eoi_timer[pirq->pirq]); _irq_guest_eoi(desc); } =20 if ( test_and_clear_bool(pirq->masked) && (--action->in_flight =3D=3D = 0) ) { ASSERT(action->ack_type =3D=3D ACKTYPE_UNMASK); - desc->handler->end(irq); + desc->handler->end(desc); } spin_unlock_irq(&desc->lock); - - return 0; - } =20 int pirq_guest_unmask(struct domain *d) @@ -505,12 +505,12 @@ int pirq_guest_bind(struct vcpu *v, stru action->nr_guests =3D 0; action->in_flight =3D 0; action->shareable =3D will_share; - action->ack_type =3D pirq_acktype(irq); + action->ack_type =3D pirq_acktype(pirq->pirq); =20 - desc->depth =3D 0; + desc->arch.depth =3D 0; desc->status |=3D IRQ_GUEST; desc->status &=3D ~IRQ_DISABLED; - desc->handler->startup(pirq->pirq); + desc->handler->startup(desc); =20 /* Attempt to bind the interrupt target to the correct CPU. */ #if 0 /* FIXME CONFIG_SMP ??? */ @@ -549,9 +549,9 @@ int pirq_guest_bind(struct vcpu *v, stru return rc; } =20 -void pirq_guest_unbind(struct domain *d, int irq, struct pirq *pirq) +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) { - irq_desc_t *desc =3D &irq_desc[irq]; + irq_desc_t *desc =3D &irq_desc[pirq->pirq]; irq_guest_action_t *action; unsigned long flags; int i; @@ -569,17 +569,17 @@ void pirq_guest_unbind(struct domain *d, if ( action->ack_type =3D=3D ACKTYPE_UNMASK ) if ( test_and_clear_bool(pirq->masked) && (--action->in_flight =3D=3D 0) ) - desc->handler->end(irq); + desc->handler->end(desc); =20 if ( !action->nr_guests ) { BUG_ON(action->in_flight !=3D 0); desc->action =3D NULL; xfree(action); - desc->depth =3D 1; + desc->arch.depth =3D 1; desc->status |=3D IRQ_DISABLED; desc->status &=3D ~IRQ_GUEST; - desc->handler->shutdown(irq); + desc->handler->shutdown(desc); } =20 spin_unlock_irqrestore(&desc->lock, flags); =20 @@ -610,10 +610,24 @@ void pirq_set_affinity(struct domain *d, /* FIXME */ } =20 +void (pirq_cleanup_check)(struct pirq *pirq, struct domain *d) +{ + /* + * Check whether all fields have their default values, and delete + * the entry from the tree if so. + * + * NB: Common parts were already checked. + */ + if ( !pt_pirq_cleanup_check(&pirq->arch.dpci) ) + return; + + if ( radix_tree_delete(&d->pirq_tree, pirq->pirq) !=3D pirq ) + BUG(); +} /* * Exit an interrupt context. Process softirqs if needed and possible: */ void irq_exit(void) { - sub_preempt_count(IRQ_EXIT_OFFSET); + preempt_count() -=3D IRQ_EXIT_OFFSET;/* sub_preempt_count(IRQ_EXIT_= OFFSET); */ } --- a/xen/arch/ia64/xen/mm.c +++ b/xen/arch/ia64/xen/mm.c @@ -176,6 +176,7 @@ #include #include #include +#include #include #include #include --- a/xen/arch/ia64/xen/pci.c +++ b/xen/arch/ia64/xen/pci.c @@ -83,54 +83,57 @@ pci_sal_write (unsigned int seg, unsigne =20 =20 uint8_t pci_conf_read8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg) { uint32_t value; - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_read(0, bus, (dev<<3)|func, reg, 1, &value); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_read(seg, bus, (dev<<3)|func, reg, 1, &value); return (uint8_t)value; } =20 uint16_t pci_conf_read16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg) { uint32_t value; - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_read(0, bus, (dev<<3)|func, reg, 2, &value); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_read(seg, bus, (dev<<3)|func, reg, 2, &value); return (uint16_t)value; } =20 uint32_t pci_conf_read32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg) { uint32_t value; - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_read(0, bus, (dev<<3)|func, reg, 4, &value); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_read(seg, bus, (dev<<3)|func, reg, 4, &value); return (uint32_t)value; } =20 void pci_conf_write8( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg, - uint8_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg, uint8_t data) { - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_write(0, bus, (dev<<3)|func, reg, 1, data); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_write(seg, bus, (dev<<3)|func, reg, 1, data); } =20 void pci_conf_write16( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg, - uint16_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg, uint16_t data) { - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_write(0, bus, (dev<<3)|func, reg, 2, data); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_write(seg, bus, (dev<<3)|func, reg, 2, data); } =20 void pci_conf_write32( - unsigned int bus, unsigned int dev, unsigned int func, unsigned int = reg, - uint32_t data) + unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func, + unsigned int reg, uint32_t data) { - BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255)); - pci_sal_write(0, bus, (dev<<3)|func, reg, 4, data); + BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > 7) || = (reg > 255)); + pci_sal_write(seg, bus, (dev<<3)|func, reg, 4, data); } =20 int pci_find_ext_capability(int seg, int bus, int devfn, int cap) --- a/xen/arch/ia64/xen/tlb_track.c +++ b/xen/arch/ia64/xen/tlb_track.c @@ -22,6 +22,7 @@ =20 #include #include +#include #include /* for IA64_RR_SHIFT */ #include /* for VRN7 */ #include /* for PSCB() */ --- a/xen/arch/ia64/xen/vhpt.c +++ b/xen/arch/ia64/xen/vhpt.c @@ -516,7 +516,7 @@ void domain_flush_tlb_vhpt(struct domain on_each_cpu((void (*)(void *))local_flush_tlb_all, NULL, = 1); else on_each_cpu((void (*)(void *))flush_tlb_vhpt_all, d, 1); - cpumask_clear_cpu(d->domain_dirty_cpumask); + cpumask_clear(d->domain_dirty_cpumask); } =20 void flush_tlb_for_log_dirty(struct domain *d) @@ -545,7 +545,7 @@ void flush_tlb_for_log_dirty(struct doma } else { on_each_cpu((void (*)(void *))flush_tlb_vhpt_all, d, 1); } - cpumask_clear_cpu(d->domain_dirty_cpumask); + cpumask_clear(d->domain_dirty_cpumask); } =20 void flush_tlb_mask(const cpumask_t *mask) --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -27,7 +27,7 @@ #include #include #include /* for hvm_acpi_power_button */ -#include /* for arch_do_domctl */ +#include /* for arch_do_domctl */ #include #include #include --- a/xen/common/event_channel.c +++ b/xen/common/event_channel.c @@ -365,8 +365,10 @@ static long evtchn_bind_pirq(evtchn_bind =20 bind->port =3D port; =20 +#ifdef CONFIG_X86 if ( is_hvm_domain(d) && domain_pirq_to_irq(d, pirq) > 0 ) map_domain_emuirq_pirq(d, pirq, IRQ_PT); +#endif =20 out: spin_unlock(&d->event_lock); @@ -421,8 +423,10 @@ static long __evtchn_close(struct domain pirq->evtchn =3D 0; pirq_cleanup_check(pirq, d1); unlink_pirq_port(chn1, d1->vcpu[chn1->notify_vcpu_id]); +#ifdef CONFIG_X86 if ( is_hvm_domain(d1) && domain_pirq_to_irq(d1, pirq->pirq) > 0 = ) unmap_domain_pirq_emuirq(d1, pirq->pirq); +#endif break; } =20 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -42,7 +42,12 @@ #include #include #include +#ifdef CONFIG_X86 #include +#else +#define p2m_pod_offline_or_broken_hit(pg) 0 +#define p2m_pod_offline_or_broken_replace(pg) BUG_ON(pg !=3D NULL) +#endif =20 /* * Comma-separated list of hexadecimal page numbers containing bad bytes. --- a/xen/drivers/passthrough/vtd/dmar.c +++ b/xen/drivers/passthrough/vtd/dmar.c @@ -809,6 +809,7 @@ int platform_supports_intremap(void) return ((dmar_flags & flags) =3D=3D DMAR_INTR_REMAP); } =20 +#ifdef CONFIG_X86 int platform_supports_x2apic(void) { unsigned int flags =3D 0; @@ -819,3 +820,4 @@ int platform_supports_x2apic(void) flags =3D DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT; return ((dmar_flags & flags) =3D=3D DMAR_INTR_REMAP); } +#endif --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -47,8 +47,8 @@ }) #define __ioapic_write_entry(apic, pin, raw, ent) ({ \ ASSERT(raw); \ - __io_apic_write(apic, 0x10 + 2 * (pin), ((u32 *)&_e_)[0]); \ - __io_apic_write(apic, 0x11 + 2 * (pin), ((u32 *)&_e_)[1]); \ + __io_apic_write(apic, 0x10 + 2 * (pin), ((u32 *)&(ent))[0]); \ + __io_apic_write(apic, 0x11 + 2 * (pin), ((u32 *)&(ent))[1]); \ }) #else #include @@ -392,7 +392,7 @@ unsigned int io_apic_read_remap_rte( ( (index =3D apic_pin_2_ir_idx[apic][ioapic_pin]) < 0 ) ) return __io_apic_read(apic, reg); =20 - old_rte =3D __ioapic_read_entry(apic, ioapic_pin, TRUE); + old_rte =3D __ioapic_read_entry(apic, ioapic_pin, 1); =20 if ( remap_entry_to_ioapic_rte(iommu, index, &old_rte) ) return __io_apic_read(apic, reg); @@ -420,7 +420,7 @@ void io_apic_write_remap_rte( return; } =20 - old_rte =3D __ioapic_read_entry(apic, ioapic_pin, TRUE); + old_rte =3D __ioapic_read_entry(apic, ioapic_pin, 1); =20 remap_rte =3D (struct IO_APIC_route_remap_entry *) &old_rte; =20 @@ -440,7 +440,7 @@ void io_apic_write_remap_rte( __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte); } else - __ioapic_write_entry(apic, ioapic_pin, TRUE, old_rte); + __ioapic_write_entry(apic, ioapic_pin, 1, old_rte); } =20 #if defined(__i386__) || defined(__x86_64__) @@ -838,6 +838,8 @@ out: spin_unlock_irqrestore(&iommu->register_lock, flags); } =20 +#ifndef __ia64__ + /* * This function is used to enable Interrupt remapping when * enable x2apic @@ -912,3 +914,5 @@ void iommu_disable_x2apic_IR(void) for_each_drhd_unit ( drhd ) disable_qinval(drhd->iommu); } + +#endif /* !__ia64__ */ --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -33,9 +33,11 @@ #include #include #include +#ifndef __ia64__ #include #include #include +#endif #include "iommu.h" #include "dmar.h" #include "extern.h" @@ -990,7 +992,11 @@ static unsigned int dma_msi_startup(stru return 0; } =20 +#ifndef __ia64__ static void dma_msi_end(struct irq_desc *desc, u8 vector) +#else +static void dma_msi_end(struct irq_desc *desc) +#endif { dma_msi_unmask(desc); ack_APIC_irq(); @@ -1790,6 +1796,7 @@ void iommu_pte_flush(struct domain *d, u =20 static int vtd_ept_page_compatible(struct iommu *iommu) { +#ifndef __ia64__ u64 ept_cap, vtd_cap =3D iommu->cap; =20 /* EPT is not initialised yet, so we must check the capability in @@ -1799,6 +1806,9 @@ static int vtd_ept_page_compatible(struc =20 return ( ept_has_2mb(ept_cap) =3D=3D cap_sps_2mb(vtd_cap)=20 && ept_has_1gb(ept_cap) =3D=3D cap_sps_1gb(vtd_cap) ); +#else + return 0; +#endif } =20 /* @@ -1806,6 +1816,7 @@ static int vtd_ept_page_compatible(struc */ void iommu_set_pgd(struct domain *d) { +#ifndef __ia64__ struct hvm_iommu *hd =3D domain_hvm_iommu(d); mfn_t pgd_mfn; =20 @@ -1816,6 +1827,7 @@ void iommu_set_pgd(struct domain *d) =20 pgd_mfn =3D pagetable_get_mfn(p2m_get_pagetable(p2m_get_hostp2m(d))); hd->pgd_maddr =3D pagetable_get_paddr(pagetable_from_mfn(pgd_mfn)); +#endif } =20 static int rmrr_identity_mapping(struct domain *d, @@ -2107,7 +2119,7 @@ int __init intel_vtd_setup(void) iommu_intremap =3D 0; =20 if ( !vtd_ept_page_compatible(iommu) ) - iommu_hap_pt_share =3D FALSE; + iommu_hap_pt_share =3D 0; =20 ret =3D iommu_set_interrupt(iommu); if ( ret < 0 ) --- a/xen/include/asm-ia64/config.h +++ b/xen/include/asm-ia64/config.h @@ -211,10 +211,6 @@ void sort_main_extable(void); // see common/keyhandler.c #define nop() asm volatile ("nop 0") =20 -// from include/linux/preempt.h (needs including from interrupt.h or = smp.h) -#define preempt_enable() do { } while (0) -#define preempt_disable() do { } while (0) - // needed for include/xen/linuxtime.h typedef s64 time_t; typedef s64 suseconds_t; --- a/xen/include/asm-ia64/domain.h +++ b/xen/include/asm-ia64/domain.h @@ -317,12 +317,8 @@ struct arch_vcpu { cpumask_t cache_coherent_map; }; =20 -struct arch_pirq { - struct hvm_pirq_dpci dpci; -}; - #define pirq_dpci(pirq) ((pirq) ? &(pirq)->arch.dpci : NULL) -#define dpci_pirq(dpci) container_of(dpci, struct pirq, arch.dpci) +#define dpci_pirq(dp) container_of(dp, struct pirq, arch.dpci) =20 #define alloc_pirq_struct(d) ({ \ struct pirq *pirq =3D xmalloc(struct pirq); \ --- a/xen/include/asm-ia64/hvm/irq.h +++ b/xen/include/asm-ia64/hvm/irq.h @@ -22,7 +22,7 @@ #ifndef __ASM_IA64_HVM_IRQ_H__ #define __ASM_IA64_HVM_IRQ_H__ =20 -#include +#include =20 #define VIOAPIC_NUM_PINS 48 =20 --- a/xen/include/asm-ia64/linux-xen/asm/hw_irq.h +++ b/xen/include/asm-ia64/linux-xen/asm/hw_irq.h @@ -79,8 +79,6 @@ enum { extern __u8 isa_irq_to_vector_map[16]; #define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] =20 -extern hw_irq_controller irq_type_ia64_lsapic; /* CPU-internal interrupt = controller */ - extern int assign_irq_vector (int irq); /* allocate a free vector = */ extern void free_irq_vector (int vector); extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int = redirect); --- a/xen/include/asm-ia64/linux-xen/asm/irq.h +++ b/xen/include/asm-ia64/linux-xen/asm/irq.h @@ -15,11 +15,18 @@ #define NR_IRQS 256 =20 #ifdef XEN +#include + struct arch_irq_desc { int vector; + unsigned int depth; cpumask_var_t cpu_mask; }; =20 +struct arch_pirq { + struct hvm_pirq_dpci dpci; +}; + int init_irq_data(void); #endif =20 @@ -66,6 +73,8 @@ extern int request_irq_vector(unsigned i while(!x) =20 #define domain_pirq_to_irq(d, irq) domain_irq_to_vector(d, irq) + +#define hvm_domain_use_pirq(d, info) 0 #endif =20 #endif /* _ASM_IA64_IRQ_H */ --- a/xen/include/asm-ia64/linux-xen/asm/spinlock.h +++ b/xen/include/asm-ia64/linux-xen/asm/spinlock.h @@ -35,6 +35,17 @@ typedef struct { } raw_rwlock_t; #define _RAW_RW_LOCK_UNLOCKED /*(raw_rwlock_t)*/ { 0, 0 } =20 +#define _raw_read_lock(rw) = \ +do { = \ + raw_rwlock_t *__read_lock_ptr =3D (rw); = \ + = \ + while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < = 0)) { \ + ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); = \ + while (*(volatile int *)__read_lock_ptr < 0) = \ + cpu_relax(); = \ + } = \ +} while (0) + #define _raw_read_unlock(rw) \ do { \ raw_rwlock_t *__read_lock_ptr =3D (rw); \ @@ -68,7 +79,14 @@ do { = \ =20 #endif /* !ASM_SUPPORTED */ =20 -#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) +#define _raw_read_trylock(rw) ({ \ + raw_rwlock_t *__read_lock_ptr =3D (rw); \ + int orig =3D ia64_fetchadd(1, (int *) __read_lock_ptr, acq); \ + \ + if (unlikely(orig < 0)) \ + ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \ + (orig >=3D 0); \ +}) =20 #define _raw_write_unlock(x) = \ ({ = \ --- a/xen/include/asm-ia64/linux-xen/linux/hardirq.h +++ b/xen/include/asm-ia64/linux-xen/linux/hardirq.h @@ -107,7 +107,8 @@ static inline void account_system_vtime( #define irq_enter() \ do { \ account_system_vtime(current); \ - add_preempt_count(HARDIRQ_OFFSET); \ + /*add_preempt_count(HARDIRQ_OFFSET);*/ \ + preempt_count() +=3D HARDIRQ_OFFSET; \ } while (0) =20 extern void irq_exit(void); --- a/xen/include/asm-ia64/xenoprof.h +++ b/xen/include/asm-ia64/xenoprof.h @@ -24,6 +24,8 @@ #ifndef __ASM_XENOPROF_H__ #define __ASM_XENOPROF_H__ =20 +#include + int xenoprof_arch_init(int *num_events, char *cpu_type); int xenoprof_arch_reserve_counters(void); int xenoprof_arch_counter(XEN_GUEST_HANDLE(void) arg); --- a/xen/include/asm-x86/hypercall.h +++ b/xen/include/asm-x86/hypercall.h @@ -7,7 +7,6 @@ =20 #include #include /* for do_mca */ -#include /* for arch_do_domctl */ #include =20 /* @@ -97,11 +96,6 @@ arch_do_vcpu_op( int cmd, struct vcpu *v, XEN_GUEST_HANDLE(void) arg); =20 extern long -arch_do_domctl( - struct xen_domctl *domctl, - XEN_GUEST_HANDLE(xen_domctl_t) u_domctl); - -extern long arch_do_sysctl( struct xen_sysctl *op,=20 XEN_GUEST_HANDLE(xen_sysctl_t) u_sysctl); --- a/xen/include/xen/acpi.h +++ b/xen/include/xen/acpi.h @@ -360,7 +360,9 @@ static inline unsigned int acpi_get_csta static inline void acpi_set_cstate_limit(unsigned int new_limit) { = return; } #endif =20 +#ifdef XEN_GUEST_HANDLE int acpi_set_pdc_bits(u32 acpi_id, XEN_GUEST_HANDLE(uint32)); +#endif int arch_acpi_set_pdc_bits(u32 acpi_id, u32 *, u32 mask); =20 #ifdef CONFIG_ACPI_NUMA --- a/xen/include/xen/efi.h +++ b/xen/include/xen/efi.h @@ -1,10 +1,12 @@ #ifndef __XEN_EFI_H__ #define __XEN_EFI_H__ =20 +#ifndef __ASSEMBLY__ #include +#endif =20 #if defined(__ia64__) -# #include +# include_next #else =20 # if defined(__i386__) @@ -27,6 +29,8 @@ extern struct efi efi; =20 #endif =20 +#ifndef __ASSEMBLY__ + union xenpf_efi_info; union compat_pf_efi_info; =20 @@ -44,4 +48,6 @@ int efi_runtime_call(struct xenpf_efi_ru int efi_compat_get_info(uint32_t idx, union compat_pf_efi_info *); int efi_compat_runtime_call(struct compat_pf_efi_runtime_call *); =20 +#endif /* !__ASSEMBLY__ */ + #endif /* __XEN_EFI_H__ */ --- a/xen/include/xen/hypercall.h +++ b/xen/include/xen/hypercall.h @@ -36,6 +36,11 @@ do_domctl( XEN_GUEST_HANDLE(xen_domctl_t) u_domctl); =20 extern long +arch_do_domctl( + struct xen_domctl *domctl, + XEN_GUEST_HANDLE(xen_domctl_t) u_domctl); + +extern long do_sysctl( XEN_GUEST_HANDLE(xen_sysctl_t) u_sysctl); =20 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -35,7 +35,11 @@ extern bool_t iommu_debug; extern bool_t amd_iommu_perdev_intremap; =20 /* Does this domain have a P2M table we can use as its IOMMU pagetable? = */ +#ifndef __ia64__ #define iommu_use_hap_pt(d) (hap_enabled(d) && iommu_hap_pt_share) +#else +#define iommu_use_hap_pt(d) 0 +#endif =20 extern struct rangeset *mmio_ro_ranges; =20 --- a/xen/include/xen/irq.h +++ b/xen/include/xen/irq.h @@ -27,6 +27,7 @@ struct irqaction { #define IRQ_GUEST (1u<<4) /* IRQ is handled by guest OS(es) */ #define IRQ_MOVE_PENDING (1u<<5) /* IRQ is migrating to another CPUs */ #define IRQ_PER_CPU (1u<<6) /* IRQ is per CPU */ +#define IRQ_GUEST_EOI_PENDING (1u<<7) /* IRQ was disabled, pending a = guest EOI */ =20 /* Special IRQ numbers. */ #define AUTO_ASSIGN_IRQ (-1) @@ -46,7 +47,11 @@ struct hw_interrupt_type { void (*enable)(struct irq_desc *); void (*disable)(struct irq_desc *); void (*ack)(struct irq_desc *); +#ifdef CONFIG_X86 void (*end)(struct irq_desc *, u8 vector); +#else + void (*end)(struct irq_desc *); +#endif void (*set_affinity)(struct irq_desc *, const cpumask_t *); }; =20 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -39,7 +39,9 @@ struct pci_dev_info { u8 bus; u8 devfn; } physfn; - vmask_t used_vectors;=20 +#ifdef CONFIG_X86 + vmask_t used_vectors; +#endif }; =20 struct pci_dev { --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -109,6 +109,10 @@ struct xsm_operations { int (*add_range) (struct domain *d, char *name, unsigned long s, = unsigned long e); int (*remove_range) (struct domain *d, char *name, unsigned long s, = unsigned long e); =20 + int (*test_assign_device) (uint32_t machine_bdf); + int (*assign_device) (struct domain *d, uint32_t machine_bdf); + int (*deassign_device) (struct domain *d, uint32_t machine_bdf); + long (*__do_xsm_op) (XEN_GUEST_HANDLE(xsm_op_t) op); =20 #ifdef CONFIG_X86 @@ -146,9 +150,6 @@ struct xsm_operations { struct page_info *page); int (*add_to_physmap) (struct domain *d1, struct domain *d2); int (*sendtrigger) (struct domain *d); - int (*test_assign_device) (uint32_t machine_bdf); - int (*assign_device) (struct domain *d, uint32_t machine_bdf); - int (*deassign_device) (struct domain *d, uint32_t machine_bdf); int (*bind_pt_irq) (struct domain *d, struct xen_domctl_bind_pt_irq = *bind); int (*pin_mem_cacheattr) (struct domain *d); int (*ext_vcpucontext) (struct domain *d, uint32_t cmd); @@ -428,6 +429,21 @@ static inline int xsm_remove_range (stru return xsm_call(remove_range(d, name, s, e)); } =20 +static inline int xsm_test_assign_device(uint32_t machine_bdf) +{ + return xsm_call(test_assign_device(machine_bdf)); +} + +static inline int xsm_assign_device(struct domain *d, uint32_t machine_bdf= ) +{ + return xsm_call(assign_device(d, machine_bdf)); +} + +static inline int xsm_deassign_device(struct domain *d, uint32_t = machine_bdf) +{ + return xsm_call(deassign_device(d, machine_bdf)); +} + static inline long __do_xsm_op (XEN_GUEST_HANDLE(xsm_op_t) op) { #ifdef XSM_ENABLE @@ -612,21 +628,6 @@ static inline int xsm_sendtrigger(struct return xsm_call(sendtrigger(d)); } =20 -static inline int xsm_test_assign_device(uint32_t machine_bdf) -{ - return xsm_call(test_assign_device(machine_bdf)); -} - -static inline int xsm_assign_device(struct domain *d, uint32_t machine_bdf= ) -{ - return xsm_call(assign_device(d, machine_bdf)); -} - -static inline int xsm_deassign_device(struct domain *d, uint32_t = machine_bdf) -{ - return xsm_call(deassign_device(d, machine_bdf)); -} - static inline int xsm_bind_pt_irq(struct domain *d,=20 struct xen_domctl_bind_pt_= irq *bind) { --=__PartEFC0113E.0__= Content-Type: text/plain; name="ia64-build.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="ia64-build.patch" ia64: fix the build=0A=0AThis addresses all remaining build problems = introduced over the last=0Aseveral months.=0A=0ASigned-off-by: Jan Beulich = =0A=0A--- a/xen/arch/ia64/linux-xen/iosapic.c=0A+++ = b/xen/arch/ia64/linux-xen/iosapic.c=0A@@ -275,12 +275,6 @@ set_rte = (unsigned int gsi, unsigned int =0A iosapic_intr_info[vector].dest =3D = dest;=0A }=0A =0A-static void=0A-nop (struct irq_desc *desc)=0A-{=0A- /* = do nothing... */=0A-}=0A-=0A void=0A kexec_disable_iosapic(void)=0A {=0A@@ = -428,7 +422,7 @@ iosapic_end_level_irq (struct irq_desc *=0A #define = iosapic_shutdown_level_irq mask_irq=0A #define iosapic_enable_level_ir= q unmask_irq=0A #define iosapic_disable_level_irq mask_irq=0A-#define= iosapic_ack_level_irq nop=0A+#define iosapic_ack_level_irq = irq_actor_none=0A =0A static hw_irq_controller irq_type_iosapic_level =3D = {=0A .typename =3D "IO-SAPIC-level",=0A@@ -446,9 +440,9 @@ static = hw_irq_controller irq_type_iosapi=0A */=0A =0A static unsigned int=0A-iosa= pic_startup_edge_irq (unsigned int irq)=0A+iosapic_startup_edge_irq = (struct irq_desc *desc)=0A {=0A- unmask_irq(irq);=0A+ unmask_irq(= desc);=0A /*=0A * IOSAPIC simply drops interrupts pended while = the=0A * corresponding pin was masked, so we can't know if an=0A@@ = -458,23 +452,21 @@ iosapic_startup_edge_irq (unsigned int i=0A }=0A =0A = static void=0A-iosapic_ack_edge_irq (unsigned int irq)=0A+iosapic_ack_edge_= irq (struct irq_desc *desc)=0A {=0A- irq_desc_t *idesc =3D irq_descp(irq= );=0A-=0A- move_irq(irq);=0A+ move_irq(idesc->irq);=0A = /*=0A * Once we have recorded IRQ_PENDING already, we can mask the=0A = * interrupt for real. This prevents IRQ storms from unhandled=0A * = devices.=0A */=0A- if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) = =3D=3D (IRQ_PENDING|IRQ_DISABLED))=0A- mask_irq(irq);=0A+ if = ((desc->status & (IRQ_PENDING|IRQ_DISABLED)) =3D=3D (IRQ_PENDING|IRQ_DISABL= ED))=0A+ mask_irq(desc);=0A }=0A =0A #define iosapic_enable_= edge_irq unmask_irq=0A-#define iosapic_disable_edge_irq = nop=0A-#define iosapic_end_edge_irq nop=0A+#define iosapic_disa= ble_edge_irq irq_disable_none=0A+#define iosapic_end_edge_irq = irq_actor_none=0A =0A static hw_irq_controller irq_type_iosapic_edge =3D = {=0A .typename =3D "IO-SAPIC-edge",=0A--- a/xen/arch/ia64/linux-xen/ir= q_ia64.c=0A+++ b/xen/arch/ia64/linux-xen/irq_ia64.c=0A@@ -242,6 +242,16 @@ = static struct irqaction __read_mostly ip=0A };=0A #endif=0A =0A+static = hw_irq_controller irq_type_ia64_lsapic =3D {=0A+ .typename =3D = "LSAPIC",=0A+ .startup =3D irq_startup_none,=0A+ .shutdown =3D = irq_shutdown_none,=0A+ .enable =3D irq_enable_none,=0A+ .disable = =3D irq_disable_none,=0A+ .ack =3D irq_actor_none,=0A+= .end =3D irq_actor_none=0A+};=0A+=0A void=0A = register_percpu_irq (ia64_vector vec, struct irqaction *action)=0A {=0A--- = a/xen/arch/ia64/linux-xen/mca.c=0A+++ b/xen/arch/ia64/linux-xen/mca.c=0A@@ = -428,9 +428,9 @@ void disable_irq_nosync(unsigned int irq=0A = return;=0A =0A spin_lock_irqsave(&desc->lock, flags);=0A- if = (!desc->depth++) {=0A+ if (!desc->arch.depth++) {=0A desc->statu= s |=3D IRQ_DISABLED;=0A- desc->handler->disable(irq);=0A+ = desc->handler->disable(desc);=0A }=0A spin_unlock_irqrest= ore(&desc->lock, flags);=0A }=0A@@ -456,7 +456,7 @@ void enable_irq(unsigne= d int irq)=0A return;=0A =0A spin_lock_irqsave(&desc->lock, = flags);=0A- switch (desc->depth) {=0A+ switch (desc->arch.depth) = {=0A case 0:=0A WARN_ON(1);=0A break;=0A@@ = -468,11 +468,11 @@ void enable_irq(unsigned int irq)=0A = desc->status =3D status | IRQ_REPLAY;=0A hw_resend_i= rq(desc->handler,irq);=0A }=0A- desc->handler->enab= le(irq);=0A+ desc->handler->enable(desc);=0A /* = fall-through */=0A }=0A default:=0A- desc->depth--;=0A+ = desc->arch.depth--;=0A }=0A spin_unlock_irqrestore(&desc->lock,= flags);=0A }=0A--- a/xen/arch/ia64/linux-xen/sn/kernel/irq.c=0A+++ = b/xen/arch/ia64/linux-xen/sn/kernel/irq.c=0A@@ -72,6 +72,7 @@ void = sn_intr_free(nasid_t local_nasid, i=0A (u64) sn_irq_info->= irq_cookie, 0, 0);=0A }=0A =0A+#ifndef XEN=0A static unsigned int = sn_startup_irq(unsigned int irq)=0A {=0A return 0;=0A@@ -88,9 = +89,16 @@ static void sn_disable_irq(unsigned int =0A static void = sn_enable_irq(unsigned int irq)=0A {=0A }=0A+#endif=0A =0A+#ifdef = XEN=0A+static void sn_ack_irq(struct irq_desc *desc)=0A+{=0A+ unsigned = int irq =3D desc->irq;=0A+#else=0A static void sn_ack_irq(unsigned int = irq)=0A {=0A+#endif=0A u64 event_occurred, mask;=0A =0A irq =3D = irq & 0xff;=0A@@ -102,8 +110,14 @@ static void sn_ack_irq(unsigned int = irq)=0A move_native_irq(irq);=0A }=0A =0A+#ifdef XEN=0A+static = void sn_end_irq(struct irq_desc *desc)=0A+{=0A+ unsigned int irq =3D = desc->irq;=0A+#else=0A static void sn_end_irq(unsigned int irq)=0A = {=0A+#endif=0A int ivec;=0A u64 event_occurred;=0A =0A@@ -224,13 = +238,17 @@ static void sn_set_affinity_irq(unsigned=0A static hw_irq_contro= ller irq_type_sn =3D {=0A #ifndef XEN=0A .name =3D "SN = hub",=0A-#else=0A- .typename =3D "SN hub",=0A-#endif=0A = .startup =3D sn_startup_irq,=0A .shutdown =3D sn_shutdown_irq= ,=0A .enable =3D sn_enable_irq,=0A .disable =3D = sn_disable_irq,=0A+#else=0A+ .typename =3D "SN hub",=0A+ = .startup =3D irq_startup_none,=0A+ .shutdown =3D = irq_shutdown_none,=0A+ .enable =3D irq_enable_none,=0A+ = .disable =3D irq_disable_none,=0A+#endif=0A .ack = =3D sn_ack_irq,=0A .end =3D sn_end_irq,=0A #ifndef = XEN=0A--- a/xen/arch/ia64/linux/Makefile=0A+++ b/xen/arch/ia64/linux/Makefi= le=0A@@ -9,7 +9,6 @@ obj-y +=3D efi_stub.o=0A obj-y +=3D extable.o=0A = obj-y +=3D flush.o=0A obj-y +=3D hpsim.o=0A-obj-y +=3D irq_lsapic.o=0A = obj-y +=3D linuxextable.o=0A obj-y +=3D machvec.o=0A obj-y +=3D memcpy_mck.= o=0A--- a/xen/arch/ia64/linux/README.origin=0A+++ b/xen/arch/ia64/linux/REA= DME.origin=0A@@ -7,7 +7,6 @@ the instructions in the README there.=0A = efi_stub.S -> linux/arch/ia64/kernel/efi_stub.S=0A extable.c = -> linux/arch/ia64/mm/extable.c=0A hpsim.S -> = linux/arch/ia64/hp/sim/hpsim.S=0A-irq_lsapic.c -> linux/arch/ia64/= kernel/irq_lsapic.c=0A linuxextable.c -> linux/kernel/extable.c= =0A machvec.c -> linux/arch/ia64/kernel/machvec.c=0A numa.c = -> linux/arch/ia64/mm/numa.c=0A--- a/xen/arch/ia64/linux/irq_lsapic= .c=0A+++ /dev/null=0A@@ -1,37 +0,0 @@=0A-/*=0A- * LSAPIC Interrupt = Controller=0A- *=0A- * This takes care of interrupts that are generated by = the CPU's=0A- * internal Streamlined Advanced Programmable Interrupt = Controller=0A- * (LSAPIC), such as the ITC and IPI interrupts.=0A- = *=0A- * Copyright (C) 1999 VA Linux Systems=0A- * Copyright (C) 1999 Walt = Drummond =0A- * Copyright (C) 2000 Hewlett-Packard = Co=0A- * Copyright (C) 2000 David Mosberger-Tang =0A- = */=0A-=0A-#include =0A-#include =0A-=0A-static = unsigned int=0A-lsapic_noop_startup (unsigned int irq)=0A-{=0A- return = 0;=0A-}=0A-=0A-static void=0A-lsapic_noop (unsigned int irq)=0A-{=0A- /* = nuthing to do... */=0A-}=0A-=0A-hw_irq_controller irq_type_ia64_lsapic =3D = {=0A- .typename =3D "LSAPIC",=0A- .startup =3D lsapic_noop_startup= ,=0A- .shutdown =3D lsapic_noop,=0A- .enable =3D lsapic_noop= ,=0A- .disable =3D lsapic_noop,=0A- .ack =3D = lsapic_noop,=0A- .end =3D lsapic_noop=0A-};=0A--- = a/xen/arch/ia64/xen/dom0_ops.c=0A+++ b/xen/arch/ia64/xen/dom0_ops.c=0A@@ = -17,6 +17,7 @@=0A #include =0A #include =0A = #include =0A+#include =0A #include = =0A #include =0A #include =0A--- = a/xen/arch/ia64/xen/domain.c=0A+++ b/xen/arch/ia64/xen/domain.c=0A@@ -23,6 = +23,7 @@=0A #include =0A #include =0A #include = =0A+#include =0A #include =0A = #include =0A #include =0A--- = a/xen/arch/ia64/xen/fw_emul.c=0A+++ b/xen/arch/ia64/xen/fw_emul.c=0A@@ = -31,7 +31,7 @@=0A #include =0A #include =0A = #include =0A-#include =0A+#include =0A #include =0A #include =0A = #include =0A--- a/xen/arch/ia64/xen/hypercall.c=0A+++ = b/xen/arch/ia64/xen/hypercall.c=0A@@ -70,7 +70,8 @@ static long __do_pirq_g= uest_eoi(struct d=0A evtchn_unmask(pirq_to_evtchn(d, pirq));=0A = spin_unlock(&d->event_lock);=0A }=0A- return = pirq_guest_eoi(pirq);=0A+ pirq_guest_eoi(pirq_info(d, pirq));=0A+ = return 0;=0A }=0A =0A long do_pirq_guest_eoi(int pirq)=0A--- a/xen/arch/ia6= 4/xen/irq.c=0A+++ b/xen/arch/ia64/xen/irq.c=0A@@ -95,8 +95,11 @@ int = __init init_irq_data(void)=0A struct irq_desc *desc =3D = irq_to_desc(irq);=0A =0A desc->irq =3D irq;=0A- = init_one_irq_desc(desc);=0A+ if (init_one_irq_desc(desc))=0A+ = BUG();=0A }=0A+=0A+ return 0;=0A }=0A =0A void = __do_IRQ_guest(int irq);=0A@@ -105,14 +108,14 @@ void __do_IRQ_guest(int = irq);=0A * Special irq handlers.=0A */=0A =0A-static void ack_none(unsign= ed int irq)=0A+static void ack_none(struct irq_desc *desc)=0A {=0A /*=0A = * 'what should we do if we get a hw irq event on an illegal vector'.=0A * = each architecture has to answer this themselves, it doesn't deserve=0A * = a generic callback i think.=0A */=0A- printk(KERN_ERR "Unexpected irq = vector 0x%x on CPU %u!\n", irq, smp_processor_id());=0A+ printk(KERN= _ERR "Unexpected irq vector 0x%x on CPU %u!\n", desc->irq, smp_processor_id= ());=0A }=0A =0A hw_irq_controller no_irq_type =3D {=0A@@ -147,11 +150,11 = @@ fastcall unsigned int __do_IRQ(unsigned =0A /*=0A * = No locking required for CPU-local interrupts:=0A */=0A- = desc->handler->ack(irq);=0A+ desc->handler->ack(desc);=0A = local_irq_enable();=0A desc->action->handler(irq, desc->action->de= v_id, regs);=0A local_irq_disable();=0A- = desc->handler->end(irq);=0A+ desc->handler->end(desc);=0A = return 1;=0A }=0A =0A@@ -163,7 +166,7 @@ fastcall unsigned int = __do_IRQ(unsigned =0A return 1;=0A }=0A =0A- desc->handl= er->ack(irq);=0A+ desc->handler->ack(desc);=0A status =3D = desc->status & ~IRQ_REPLAY;=0A status |=3D IRQ_PENDING; /* we _want_ to = handle it */=0A =0A@@ -215,7 +218,7 @@ out:=0A * The ->end() handler has = to deal with interrupts which got=0A * disabled while the handler was = running.=0A */=0A- desc->handler->end(irq);=0A+ desc->handler->end(= desc);=0A spin_unlock(&desc->lock);=0A =0A return 1;=0A@@ = -248,10 +251,10 @@ int setup_vector(unsigned int vector, st=0A =0A *p = =3D new;=0A =0A- desc->depth =3D 0;=0A+ desc->arch.depth =3D 0;=0A = desc->status &=3D ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_GUEST);=0A-= desc->handler->startup(vector);=0A- desc->handler->enable(vecto= r);=0A+ desc->handler->startup(desc);=0A+ desc->handler->enable(desc)= ;=0A desc->arch.vector =3D vector;=0A spin_unlock_irqrestore(&des= c->lock,flags);=0A =0A@@ -287,9 +290,9 @@ void __init release_irq_vector(un= signed =0A spin_lock_irqsave(&desc->lock, flags);=0A clear_bit(v= ec, ia64_xen_vector);=0A desc->action =3D NULL;=0A- desc->depth= =3D 1;=0A+ desc->arch.depth =3D 1;=0A desc->status |=3D = IRQ_DISABLED;=0A- desc->handler->shutdown(vec);=0A+ desc->handl= er->shutdown(desc);=0A desc->arch.vector =3D -1;=0A spin_unlock_irqrest= ore(&desc->lock, flags);=0A =0A@@ -336,7 +339,7 @@ static void _irq_guest_e= oi(irq_desc_t *d=0A clear_pirq_eoi(action->guest[i], vector);=0A = =0A desc->status &=3D ~(IRQ_INPROGRESS|IRQ_GUEST_EOI_PENDING);=0A- = desc->handler->enable(vector);=0A+ desc->handler->enable(desc);=0A }=0A = =0A static struct timer irq_guest_eoi_timer[NR_IRQS];=0A@@ -383,7 +386,7 = @@ void __do_IRQ_guest(int irq)=0A if ( already_pending =3D=3D = action->nr_guests )=0A {=0A stop_timer(&irq_guest_eoi_timer[irq= ]);=0A- desc->handler->disable(irq);=0A+ desc->handl= er->disable(desc);=0A desc->status |=3D IRQ_GUEST_EOI_PENDING;=0A = for ( i =3D 0; i < already_pending; ++i )=0A {=0A@@ -417,31 = +420,28 @@ static int pirq_acktype(int irq)=0A return ACKTYPE_NONE;=0A = }=0A =0A-int pirq_guest_eoi(struct pirq *pirq)=0A+void pirq_guest_eoi(struc= t pirq *pirq)=0A {=0A irq_desc_t *desc;=0A irq_guest_action_t = *action;=0A =0A- desc =3D &irq_desc[irq];=0A+ desc =3D &irq_desc[pirq= ->pirq];=0A spin_lock_irq(&desc->lock);=0A action =3D (irq_guest_ac= tion_t *)desc->action;=0A =0A if ( action->ack_type =3D=3D ACKTYPE_NONE= )=0A {=0A ASSERT(!pirq->masked);=0A- stop_timer(&irq_gu= est_eoi_timer[irq]);=0A+ stop_timer(&irq_guest_eoi_timer[pirq->pirq]= );=0A _irq_guest_eoi(desc);=0A }=0A =0A if ( test_and_clear= _bool(pirq->masked) && (--action->in_flight =3D=3D 0) )=0A {=0A = ASSERT(action->ack_type =3D=3D ACKTYPE_UNMASK);=0A- desc->handler->= end(irq);=0A+ desc->handler->end(desc);=0A }=0A spin_unlock_= irq(&desc->lock);=0A-=0A- return 0;=0A-=0A }=0A =0A int pirq_guest_unmas= k(struct domain *d)=0A@@ -505,12 +505,12 @@ int pirq_guest_bind(struct = vcpu *v, stru=0A action->nr_guests =3D 0;=0A action->in_fli= ght =3D 0;=0A action->shareable =3D will_share;=0A- = action->ack_type =3D pirq_acktype(irq);=0A+ action->ack_type =3D = pirq_acktype(pirq->pirq);=0A =0A- desc->depth =3D 0;=0A+ = desc->arch.depth =3D 0;=0A desc->status |=3D IRQ_GUEST;=0A = desc->status &=3D ~IRQ_DISABLED;=0A- desc->handler->startup(pirq= ->pirq);=0A+ desc->handler->startup(desc);=0A =0A /* = Attempt to bind the interrupt target to the correct CPU. */=0A #if 0 /* = FIXME CONFIG_SMP ??? */=0A@@ -549,9 +549,9 @@ int pirq_guest_bind(struct = vcpu *v, stru=0A return rc;=0A }=0A =0A-void pirq_guest_unbind(struct = domain *d, int irq, struct pirq *pirq)=0A+void pirq_guest_unbind(struct = domain *d, struct pirq *pirq)=0A {=0A- irq_desc_t *desc =3D = &irq_desc[irq];=0A+ irq_desc_t *desc =3D &irq_desc[pirq->pirq];= =0A irq_guest_action_t *action;=0A unsigned long flags;=0A = int i;=0A@@ -569,17 +569,17 @@ void pirq_guest_unbind(str= uct domain *d,=0A if ( action->ack_type =3D=3D ACKTYPE_UNMASK )=0A = if ( test_and_clear_bool(pirq->masked) &&=0A (--action->in= _flight =3D=3D 0) )=0A- desc->handler->end(irq);=0A+ = desc->handler->end(desc);=0A =0A if ( !action->nr_guests )=0A {=0A = BUG_ON(action->in_flight !=3D 0);=0A desc->action =3D = NULL;=0A xfree(action);=0A- desc->depth =3D 1;=0A+ = desc->arch.depth =3D 1;=0A desc->status |=3D IRQ_DISABLED;=0A = desc->status &=3D ~IRQ_GUEST;=0A- desc->handler->shutdown(irq);= =0A+ desc->handler->shutdown(desc);=0A }=0A =0A spin_unlock_= irqrestore(&desc->lock, flags); =0A@@ -610,10 +610,24 @@ void pirq_set_a= ffinity(struct domain *d,=0A /* FIXME */=0A }=0A =0A+void (pirq_cleanup_= check)(struct pirq *pirq, struct domain *d)=0A+{=0A+ /*=0A+ * Check = whether all fields have their default values, and delete=0A+ * the = entry from the tree if so.=0A+ *=0A+ * NB: Common parts were = already checked.=0A+ */=0A+ if ( !pt_pirq_cleanup_check(&pirq->arch.= dpci) )=0A+ return;=0A+=0A+ if ( radix_tree_delete(&d->pirq_tree,= pirq->pirq) !=3D pirq )=0A+ BUG();=0A+}=0A /*=0A * Exit an = interrupt context. Process softirqs if needed and possible:=0A */=0A void = irq_exit(void)=0A {=0A- sub_preempt_count(IRQ_EXIT_OFFSET);=0A+ preempt_cou= nt() -=3D IRQ_EXIT_OFFSET;/* sub_preempt_count(IRQ_EXIT_OFFSET); */=0A = }=0A--- a/xen/arch/ia64/xen/mm.c=0A+++ b/xen/arch/ia64/xen/mm.c=0A@@ = -176,6 +176,7 @@=0A #include =0A #include =0A= #include =0A+#include =0A #include = =0A #include =0A #include =0A--- a/xen/arch/ia64/xen/pci.c=0A+++ b/xen/arch/ia64/xen/pci.c=0A@@ = -83,54 +83,57 @@ pci_sal_write (unsigned int seg, unsigne=0A =0A =0A = uint8_t pci_conf_read8(=0A- unsigned int bus, unsigned int dev, = unsigned int func, unsigned int reg)=0A+ unsigned int seg, unsigned int = bus, unsigned int dev, unsigned int func,=0A+ unsigned int reg)=0A {=0A = uint32_t value;=0A- BUG_ON((bus > 255) || (dev > 31) || (func > 7) = || (reg > 255));=0A- pci_sal_read(0, bus, (dev<<3)|func, reg, 1, = &value);=0A+ BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func = > 7) || (reg > 255));=0A+ pci_sal_read(seg, bus, (dev<<3)|func, reg, 1, = &value);=0A return (uint8_t)value;=0A }=0A =0A uint16_t pci_conf_read16= (=0A- unsigned int bus, unsigned int dev, unsigned int func, unsigned = int reg)=0A+ unsigned int seg, unsigned int bus, unsigned int dev, = unsigned int func,=0A+ unsigned int reg)=0A {=0A uint32_t value;=0A-= BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A- = pci_sal_read(0, bus, (dev<<3)|func, reg, 2, &value);=0A+ BUG_ON((seg > = 65535) || (bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A+ = pci_sal_read(seg, bus, (dev<<3)|func, reg, 2, &value);=0A return = (uint16_t)value;=0A }=0A =0A uint32_t pci_conf_read32(=0A- unsigned int = bus, unsigned int dev, unsigned int func, unsigned int reg)=0A+ = unsigned int seg, unsigned int bus, unsigned int dev, unsigned int = func,=0A+ unsigned int reg)=0A {=0A uint32_t value;=0A- = BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A- = pci_sal_read(0, bus, (dev<<3)|func, reg, 4, &value);=0A+ BUG_ON((seg > = 65535) || (bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A+ = pci_sal_read(seg, bus, (dev<<3)|func, reg, 4, &value);=0A return = (uint32_t)value;=0A }=0A =0A void pci_conf_write8(=0A- unsigned int = bus, unsigned int dev, unsigned int func, unsigned int reg,=0A- uint8_t = data)=0A+ unsigned int seg, unsigned int bus, unsigned int dev, = unsigned int func,=0A+ unsigned int reg, uint8_t data)=0A {=0A- = BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A- = pci_sal_write(0, bus, (dev<<3)|func, reg, 1, data);=0A+ BUG_ON((seg > = 65535) || (bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A+ = pci_sal_write(seg, bus, (dev<<3)|func, reg, 1, data);=0A }=0A =0A void = pci_conf_write16(=0A- unsigned int bus, unsigned int dev, unsigned int = func, unsigned int reg,=0A- uint16_t data)=0A+ unsigned int seg, = unsigned int bus, unsigned int dev, unsigned int func,=0A+ unsigned int = reg, uint16_t data)=0A {=0A- BUG_ON((bus > 255) || (dev > 31) || (func = > 7) || (reg > 255));=0A- pci_sal_write(0, bus, (dev<<3)|func, reg, 2, = data);=0A+ BUG_ON((seg > 65535) || (bus > 255) || (dev > 31) || (func > = 7) || (reg > 255));=0A+ pci_sal_write(seg, bus, (dev<<3)|func, reg, 2, = data);=0A }=0A =0A void pci_conf_write32(=0A- unsigned int bus, = unsigned int dev, unsigned int func, unsigned int reg,=0A- uint32_t = data)=0A+ unsigned int seg, unsigned int bus, unsigned int dev, = unsigned int func,=0A+ unsigned int reg, uint32_t data)=0A {=0A- = BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A- = pci_sal_write(0, bus, (dev<<3)|func, reg, 4, data);=0A+ BUG_ON((seg > = 65535) || (bus > 255) || (dev > 31) || (func > 7) || (reg > 255));=0A+ = pci_sal_write(seg, bus, (dev<<3)|func, reg, 4, data);=0A }=0A =0A int = pci_find_ext_capability(int seg, int bus, int devfn, int cap)=0A--- = a/xen/arch/ia64/xen/tlb_track.c=0A+++ b/xen/arch/ia64/xen/tlb_track.c=0A@@ = -22,6 +22,7 @@=0A =0A #include =0A #include =0A+#include =0A #include /* for = IA64_RR_SHIFT */=0A #include /* for VRN7 */=0A = #include /* for PSCB() */=0A--- a/xen/arch/ia64/xen/vhp= t.c=0A+++ b/xen/arch/ia64/xen/vhpt.c=0A@@ -516,7 +516,7 @@ void domain_flus= h_tlb_vhpt(struct domain=0A on_each_cpu((void (*)(void = *))local_flush_tlb_all, NULL, 1);=0A else=0A on_each_cpu= ((void (*)(void *))flush_tlb_vhpt_all, d, 1);=0A- cpumask_clear_cpu(d= ->domain_dirty_cpumask);=0A+ cpumask_clear(d->domain_dirty_cpumask);=0A = }=0A =0A void flush_tlb_for_log_dirty(struct domain *d)=0A@@ -545,7 +545,7 = @@ void flush_tlb_for_log_dirty(struct doma=0A } else {=0A = on_each_cpu((void (*)(void *))flush_tlb_vhpt_all, d, 1);=0A }=0A- = cpumask_clear_cpu(d->domain_dirty_cpumask);=0A+ cpumask_clear(d->domain_dir= ty_cpumask);=0A }=0A =0A void flush_tlb_mask(const cpumask_t *mask)=0A--- = a/xen/arch/x86/domctl.c=0A+++ b/xen/arch/x86/domctl.c=0A@@ -27,7 +27,7 = @@=0A #include =0A #include =0A = #include /* for hvm_acpi_power_button */=0A-#include = /* for arch_do_domctl */=0A+#include = /* for arch_do_domctl */=0A #include =0A #include = =0A #include =0A--- a/xen/common/event_channel.c=0A+++ = b/xen/common/event_channel.c=0A@@ -365,8 +365,10 @@ static long evtchn_bind= _pirq(evtchn_bind=0A =0A bind->port =3D port;=0A =0A+#ifdef CONFIG_X86= =0A if ( is_hvm_domain(d) && domain_pirq_to_irq(d, pirq) > 0 )=0A = map_domain_emuirq_pirq(d, pirq, IRQ_PT);=0A+#endif=0A =0A out:=0A = spin_unlock(&d->event_lock);=0A@@ -421,8 +423,10 @@ static long __evtchn_cl= ose(struct domain=0A pirq->evtchn =3D 0;=0A pirq_cleanup_ch= eck(pirq, d1);=0A unlink_pirq_port(chn1, d1->vcpu[chn1->notify_vcpu= _id]);=0A+#ifdef CONFIG_X86=0A if ( is_hvm_domain(d1) && domain_pir= q_to_irq(d1, pirq->pirq) > 0 )=0A unmap_domain_pirq_emuirq(d1, = pirq->pirq);=0A+#endif=0A break;=0A }=0A =0A--- a/xen/common/pa= ge_alloc.c=0A+++ b/xen/common/page_alloc.c=0A@@ -42,7 +42,12 @@=0A = #include =0A #include =0A #include = =0A+#ifdef CONFIG_X86=0A #include =0A+#else=0A+#define = p2m_pod_offline_or_broken_hit(pg) 0=0A+#define p2m_pod_offline_or_broken_re= place(pg) BUG_ON(pg !=3D NULL)=0A+#endif=0A =0A /*=0A * Comma-separated = list of hexadecimal page numbers containing bad bytes.=0A--- a/xen/drivers/= passthrough/vtd/dmar.c=0A+++ b/xen/drivers/passthrough/vtd/dmar.c=0A@@ = -809,6 +809,7 @@ int platform_supports_intremap(void)=0A return = ((dmar_flags & flags) =3D=3D DMAR_INTR_REMAP);=0A }=0A =0A+#ifdef = CONFIG_X86=0A int platform_supports_x2apic(void)=0A {=0A unsigned int = flags =3D 0;=0A@@ -819,3 +820,4 @@ int platform_supports_x2apic(void)=0A = flags =3D DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT;=0A return ((dmar_fla= gs & flags) =3D=3D DMAR_INTR_REMAP);=0A }=0A+#endif=0A--- a/xen/drivers/pas= sthrough/vtd/intremap.c=0A+++ b/xen/drivers/passthrough/vtd/intremap.c=0A@@= -47,8 +47,8 @@=0A })=0A #define __ioapic_write_entry(apic, pin, raw, ent) = ({ \=0A ASSERT(raw); \=0A- __io_apic_write(apic, 0x10 + 2 * (pin), = ((u32 *)&_e_)[0]); \=0A- __io_apic_write(apic, 0x11 + 2 * (pin), ((u32 = *)&_e_)[1]); \=0A+ __io_apic_write(apic, 0x10 + 2 * (pin), ((u32 = *)&(ent))[0]); \=0A+ __io_apic_write(apic, 0x11 + 2 * (pin), ((u32 = *)&(ent))[1]); \=0A })=0A #else=0A #include =0A@@ -392,7 = +392,7 @@ unsigned int io_apic_read_remap_rte(=0A ( (index =3D = apic_pin_2_ir_idx[apic][ioapic_pin]) < 0 ) )=0A return __io_apic_re= ad(apic, reg);=0A =0A- old_rte =3D __ioapic_read_entry(apic, ioapic_pin,= TRUE);=0A+ old_rte =3D __ioapic_read_entry(apic, ioapic_pin, 1);=0A = =0A if ( remap_entry_to_ioapic_rte(iommu, index, &old_rte) )=0A = return __io_apic_read(apic, reg);=0A@@ -420,7 +420,7 @@ void io_apic_write= _remap_rte(=0A return;=0A }=0A =0A- old_rte =3D __ioapic_rea= d_entry(apic, ioapic_pin, TRUE);=0A+ old_rte =3D __ioapic_read_entry(api= c, ioapic_pin, 1);=0A =0A remap_rte =3D (struct IO_APIC_route_remap_ent= ry *) &old_rte;=0A =0A@@ -440,7 +440,7 @@ void io_apic_write_remap_rte(=0A = __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte);=0A }=0A = else=0A- __ioapic_write_entry(apic, ioapic_pin, TRUE, = old_rte);=0A+ __ioapic_write_entry(apic, ioapic_pin, 1, old_rte);=0A= }=0A =0A #if defined(__i386__) || defined(__x86_64__)=0A@@ -838,6 +838,8 = @@ out:=0A spin_unlock_irqrestore(&iommu->register_lock, flags);=0A = }=0A =0A+#ifndef __ia64__=0A+=0A /*=0A * This function is used to enable = Interrupt remapping when=0A * enable x2apic=0A@@ -912,3 +914,5 @@ void = iommu_disable_x2apic_IR(void)=0A for_each_drhd_unit ( drhd )=0A = disable_qinval(drhd->iommu);=0A }=0A+=0A+#endif /* !__ia64__ */=0A--- = a/xen/drivers/passthrough/vtd/iommu.c=0A+++ b/xen/drivers/passthrough/vtd/i= ommu.c=0A@@ -33,9 +33,11 @@=0A #include =0A #include = =0A #include =0A+#ifndef __ia64__=0A #include = =0A #include =0A #include =0A+#e= ndif=0A #include "iommu.h"=0A #include "dmar.h"=0A #include "extern.h"=0A@@= -990,7 +992,11 @@ static unsigned int dma_msi_startup(stru=0A return = 0;=0A }=0A =0A+#ifndef __ia64__=0A static void dma_msi_end(struct irq_desc = *desc, u8 vector)=0A+#else=0A+static void dma_msi_end(struct irq_desc = *desc)=0A+#endif=0A {=0A dma_msi_unmask(desc);=0A ack_APIC_irq();= =0A@@ -1790,6 +1796,7 @@ void iommu_pte_flush(struct domain *d, u=0A =0A = static int vtd_ept_page_compatible(struct iommu *iommu)=0A {=0A+#ifndef = __ia64__=0A u64 ept_cap, vtd_cap =3D iommu->cap;=0A =0A /* EPT is = not initialised yet, so we must check the capability in=0A@@ -1799,6 = +1806,9 @@ static int vtd_ept_page_compatible(struc=0A =0A return ( = ept_has_2mb(ept_cap) =3D=3D cap_sps_2mb(vtd_cap) =0A && = ept_has_1gb(ept_cap) =3D=3D cap_sps_1gb(vtd_cap) );=0A+#else=0A+ return = 0;=0A+#endif=0A }=0A =0A /*=0A@@ -1806,6 +1816,7 @@ static int vtd_ept_page= _compatible(struc=0A */=0A void iommu_set_pgd(struct domain *d)=0A = {=0A+#ifndef __ia64__=0A struct hvm_iommu *hd =3D domain_hvm_iommu(d);= =0A mfn_t pgd_mfn;=0A =0A@@ -1816,6 +1827,7 @@ void iommu_set_pgd(struc= t domain *d)=0A =0A pgd_mfn =3D pagetable_get_mfn(p2m_get_pagetable(p2m= _get_hostp2m(d)));=0A hd->pgd_maddr =3D pagetable_get_paddr(pagetable_f= rom_mfn(pgd_mfn));=0A+#endif=0A }=0A =0A static int rmrr_identity_mapping(s= truct domain *d,=0A@@ -2107,7 +2119,7 @@ int __init intel_vtd_setup(void)= =0A iommu_intremap =3D 0;=0A =0A if ( !vtd_ept_page_com= patible(iommu) )=0A- iommu_hap_pt_share =3D FALSE;=0A+ = iommu_hap_pt_share =3D 0;=0A =0A ret =3D iommu_set_interrupt(iomm= u);=0A if ( ret < 0 )=0A--- a/xen/include/asm-ia64/config.h=0A+++ = b/xen/include/asm-ia64/config.h=0A@@ -211,10 +211,6 @@ void sort_main_extab= le(void);=0A // see common/keyhandler.c=0A #define nop() asm = volatile ("nop 0")=0A =0A-// from include/linux/preempt.h (needs including = from interrupt.h or smp.h)=0A-#define preempt_enable() do { } while = (0)=0A-#define preempt_disable() do { } while (0)=0A-=0A // needed = for include/xen/linuxtime.h=0A typedef s64 time_t;=0A typedef s64 = suseconds_t;=0A--- a/xen/include/asm-ia64/domain.h=0A+++ b/xen/include/asm-= ia64/domain.h=0A@@ -317,12 +317,8 @@ struct arch_vcpu {=0A cpumask_t = cache_coherent_map;=0A };=0A =0A-struct arch_pirq {=0A- struct = hvm_pirq_dpci dpci;=0A-};=0A-=0A #define pirq_dpci(pirq) ((pirq) ? = &(pirq)->arch.dpci : NULL)=0A-#define dpci_pirq(dpci) container_of(dpci, = struct pirq, arch.dpci)=0A+#define dpci_pirq(dp) container_of(dp, struct = pirq, arch.dpci)=0A =0A #define alloc_pirq_struct(d) ({ \=0A struct = pirq *pirq =3D xmalloc(struct pirq); \=0A--- a/xen/include/asm-ia64/hvm/irq= .h=0A+++ b/xen/include/asm-ia64/hvm/irq.h=0A@@ -22,7 +22,7 @@=0A #ifndef = __ASM_IA64_HVM_IRQ_H__=0A #define __ASM_IA64_HVM_IRQ_H__=0A =0A-#include = =0A+#include =0A =0A #define VIOAPIC_NUM_PINS 48=0A = =0A--- a/xen/include/asm-ia64/linux-xen/asm/hw_irq.h=0A+++ b/xen/include/as= m-ia64/linux-xen/asm/hw_irq.h=0A@@ -79,8 +79,6 @@ enum {=0A extern __u8 = isa_irq_to_vector_map[16];=0A #define isa_irq_to_vector(x) isa_irq_to_= vector_map[(x)]=0A =0A-extern hw_irq_controller irq_type_ia64_lsapic; /* = CPU-internal interrupt controller */=0A-=0A extern int assign_irq_vector = (int irq); /* allocate a free vector */=0A extern void free_irq_vector= (int vector);=0A extern void ia64_send_ipi (int cpu, int vector, int = delivery_mode, int redirect);=0A--- a/xen/include/asm-ia64/linux-xen/asm/ir= q.h=0A+++ b/xen/include/asm-ia64/linux-xen/asm/irq.h=0A@@ -15,11 +15,18 = @@=0A #define NR_IRQS 256=0A =0A #ifdef XEN=0A+#include = =0A+=0A struct arch_irq_desc {=0A int vector;=0A+ = unsigned int depth;=0A cpumask_var_t cpu_mask;=0A };=0A =0A+struct = arch_pirq {=0A+ struct hvm_pirq_dpci dpci;=0A+};=0A+=0A int init_irq_data(v= oid);=0A #endif=0A =0A@@ -66,6 +73,8 @@ extern int request_irq_vector(unsig= ned i=0A while(!x)=0A =0A #define domain_pirq_to_irq(d, irq) domain_irq= _to_vector(d, irq)=0A+=0A+#define hvm_domain_use_pirq(d, info) 0=0A = #endif=0A =0A #endif /* _ASM_IA64_IRQ_H */=0A--- a/xen/include/asm-ia64/lin= ux-xen/asm/spinlock.h=0A+++ b/xen/include/asm-ia64/linux-xen/asm/spinlock.h= =0A@@ -35,6 +35,17 @@ typedef struct {=0A } raw_rwlock_t;=0A #define = _RAW_RW_LOCK_UNLOCKED /*(raw_rwlock_t)*/ { 0, 0 }=0A =0A+#define _raw_read_= lock(rw) = \=0A+do { = \=0A+ raw_rwlock_t *__read_lock_ptr =3D (rw); = \=0A+ = \=0A+ while (unlikely(ia64_fetchadd(1, = (int *) __read_lock_ptr, acq) < 0)) { \=0A+ ia64_fetcha= dd(-1, (int *) __read_lock_ptr, rel); \=0A+ = while (*(volatile int *)__read_lock_ptr < 0) = \=0A+ cpu_relax(); = \=0A+ } = \=0A+} while (0)=0A+=0A #define _raw_read_unlock(rw) = \=0A do { = \=0A raw_rwlock_t *__read_lock_ptr =3D (rw); = \=0A@@ -68,7 +79,14 @@ do { = \=0A =0A #endif /* !ASM_SUPPORTED */=0A =0A-#define _raw_read_trylo= ck(lock) generic_raw_read_trylock(lock)=0A+#define _raw_read_trylock(rw) = ({ \=0A+ raw_rwlock_t *__read_lock_p= tr =3D (rw); \=0A+ int orig =3D ia64_fetchadd(= 1, (int *) __read_lock_ptr, acq); \=0A+ = \=0A+ if (unlikely(orig < 0)) = \=0A+ ia64_fetchadd(-1, (int *) = __read_lock_ptr, rel); \=0A+ (orig >=3D 0); = \=0A+})=0A =0A #define _raw_write_unlock(x) = \=0A ({ = \=0A--- a/xen/include/asm-i= a64/linux-xen/linux/hardirq.h=0A+++ b/xen/include/asm-ia64/linux-xen/linux/= hardirq.h=0A@@ -107,7 +107,8 @@ static inline void account_system_vtime(=0A= #define irq_enter() \=0A do { = \=0A account_system_vtime(curren= t); \=0A- add_preempt_count(HARDIRQ_OFFSET); = \=0A+ /*add_preempt_count(HARDIRQ_OFFSET);*/ \=0A+ = preempt_count() +=3D HARDIRQ_OFFSET; \=0A } while (0)=0A =0A extern = void irq_exit(void);=0A--- a/xen/include/asm-ia64/xenoprof.h=0A+++ = b/xen/include/asm-ia64/xenoprof.h=0A@@ -24,6 +24,8 @@=0A #ifndef __ASM_XENO= PROF_H__=0A #define __ASM_XENOPROF_H__=0A =0A+#include = =0A+=0A int xenoprof_arch_init(int *num_events, char *cpu_type);=0A int = xenoprof_arch_reserve_counters(void);=0A int xenoprof_arch_counter(XEN_GUES= T_HANDLE(void) arg);=0A--- a/xen/include/asm-x86/hypercall.h=0A+++ = b/xen/include/asm-x86/hypercall.h=0A@@ -7,7 +7,6 @@=0A =0A #include = =0A #include /* for do_mca = */=0A-#include /* for arch_do_domctl */=0A #include = =0A =0A /*=0A@@ -97,11 +96,6 @@ arch_do_vcpu_op(=0A int = cmd, struct vcpu *v, XEN_GUEST_HANDLE(void) arg);=0A =0A extern long=0A-arc= h_do_domctl(=0A- struct xen_domctl *domctl,=0A- XEN_GUEST_HANDLE(xen_= domctl_t) u_domctl);=0A-=0A-extern long=0A arch_do_sysctl(=0A struct = xen_sysctl *op, =0A XEN_GUEST_HANDLE(xen_sysctl_t) u_sysctl);=0A--- = a/xen/include/xen/acpi.h=0A+++ b/xen/include/xen/acpi.h=0A@@ -360,7 +360,9 = @@ static inline unsigned int acpi_get_csta=0A static inline void = acpi_set_cstate_limit(unsigned int new_limit) { return; }=0A #endif=0A = =0A+#ifdef XEN_GUEST_HANDLE=0A int acpi_set_pdc_bits(u32 acpi_id, = XEN_GUEST_HANDLE(uint32));=0A+#endif=0A int arch_acpi_set_pdc_bits(u32 = acpi_id, u32 *, u32 mask);=0A =0A #ifdef CONFIG_ACPI_NUMA=0A--- a/xen/inclu= de/xen/efi.h=0A+++ b/xen/include/xen/efi.h=0A@@ -1,10 +1,12 @@=0A #ifndef = __XEN_EFI_H__=0A #define __XEN_EFI_H__=0A =0A+#ifndef __ASSEMBLY__=0A = #include =0A+#endif=0A =0A #if defined(__ia64__)=0A-# = #include =0A+# include_next =0A #else=0A =0A # = if defined(__i386__)=0A@@ -27,6 +29,8 @@ extern struct efi efi;=0A =0A = #endif=0A =0A+#ifndef __ASSEMBLY__=0A+=0A union xenpf_efi_info;=0A union = compat_pf_efi_info;=0A =0A@@ -44,4 +48,6 @@ int efi_runtime_call(struct = xenpf_efi_ru=0A int efi_compat_get_info(uint32_t idx, union compat_pf_efi_i= nfo *);=0A int efi_compat_runtime_call(struct compat_pf_efi_runtime_call = *);=0A =0A+#endif /* !__ASSEMBLY__ */=0A+=0A #endif /* __XEN_EFI_H__ = */=0A--- a/xen/include/xen/hypercall.h=0A+++ b/xen/include/xen/hypercall.h= =0A@@ -36,6 +36,11 @@ do_domctl(=0A XEN_GUEST_HANDLE(xen_domctl_t) = u_domctl);=0A =0A extern long=0A+arch_do_domctl(=0A+ struct xen_domctl = *domctl,=0A+ XEN_GUEST_HANDLE(xen_domctl_t) u_domctl);=0A+=0A+extern = long=0A do_sysctl(=0A XEN_GUEST_HANDLE(xen_sysctl_t) u_sysctl);=0A = =0A--- a/xen/include/xen/iommu.h=0A+++ b/xen/include/xen/iommu.h=0A@@ = -35,7 +35,11 @@ extern bool_t iommu_debug;=0A extern bool_t amd_iommu_perde= v_intremap;=0A =0A /* Does this domain have a P2M table we can use as its = IOMMU pagetable? */=0A+#ifndef __ia64__=0A #define iommu_use_hap_pt(d) = (hap_enabled(d) && iommu_hap_pt_share)=0A+#else=0A+#define iommu_use_hap_pt= (d) 0=0A+#endif=0A =0A extern struct rangeset *mmio_ro_ranges;=0A =0A--- = a/xen/include/xen/irq.h=0A+++ b/xen/include/xen/irq.h=0A@@ -27,6 +27,7 @@ = struct irqaction {=0A #define IRQ_GUEST (1u<<4) /* IRQ is handled = by guest OS(es) */=0A #define IRQ_MOVE_PENDING (1u<<5) /* IRQ is = migrating to another CPUs */=0A #define IRQ_PER_CPU (1u<<6) /* IRQ = is per CPU */=0A+#define IRQ_GUEST_EOI_PENDING (1u<<7) /* IRQ was = disabled, pending a guest EOI */=0A =0A /* Special IRQ numbers. */=0A = #define AUTO_ASSIGN_IRQ (-1)=0A@@ -46,7 +47,11 @@ struct hw_interru= pt_type {=0A void (*enable)(struct irq_desc *);=0A void (*disable)(= struct irq_desc *);=0A void (*ack)(struct irq_desc *);=0A+#ifdef = CONFIG_X86=0A void (*end)(struct irq_desc *, u8 vector);=0A+#else=0A+ = void (*end)(struct irq_desc *);=0A+#endif=0A void (*set_affinity)(str= uct irq_desc *, const cpumask_t *);=0A };=0A =0A--- a/xen/include/xen/pci.h= =0A+++ b/xen/include/xen/pci.h=0A@@ -39,7 +39,9 @@ struct pci_dev_info = {=0A u8 bus;=0A u8 devfn;=0A } physfn;=0A- vmask_t = used_vectors; =0A+#ifdef CONFIG_X86=0A+ vmask_t used_vectors;=0A+#endif= =0A };=0A =0A struct pci_dev {=0A--- a/xen/include/xsm/xsm.h=0A+++ = b/xen/include/xsm/xsm.h=0A@@ -109,6 +109,10 @@ struct xsm_operations {=0A = int (*add_range) (struct domain *d, char *name, unsigned long s, = unsigned long e);=0A int (*remove_range) (struct domain *d, char = *name, unsigned long s, unsigned long e);=0A =0A+ int (*test_assign_devi= ce) (uint32_t machine_bdf);=0A+ int (*assign_device) (struct domain *d, = uint32_t machine_bdf);=0A+ int (*deassign_device) (struct domain *d, = uint32_t machine_bdf);=0A+=0A long (*__do_xsm_op) (XEN_GUEST_HANDLE(xsm= _op_t) op);=0A =0A #ifdef CONFIG_X86=0A@@ -146,9 +150,6 @@ struct = xsm_operations {=0A struct page_info *page);=0A = int (*add_to_physmap) (struct domain *d1, struct domain *d2);=0A = int (*sendtrigger) (struct domain *d);=0A- int (*test_assign_device) = (uint32_t machine_bdf);=0A- int (*assign_device) (struct domain *d, = uint32_t machine_bdf);=0A- int (*deassign_device) (struct domain *d, = uint32_t machine_bdf);=0A int (*bind_pt_irq) (struct domain *d, struct = xen_domctl_bind_pt_irq *bind);=0A int (*pin_mem_cacheattr) (struct = domain *d);=0A int (*ext_vcpucontext) (struct domain *d, uint32_t = cmd);=0A@@ -428,6 +429,21 @@ static inline int xsm_remove_range (stru=0A = return xsm_call(remove_range(d, name, s, e));=0A }=0A =0A+static inline = int xsm_test_assign_device(uint32_t machine_bdf)=0A+{=0A+ return = xsm_call(test_assign_device(machine_bdf));=0A+}=0A+=0A+static inline int = xsm_assign_device(struct domain *d, uint32_t machine_bdf)=0A+{=0A+ = return xsm_call(assign_device(d, machine_bdf));=0A+}=0A+=0A+static inline = int xsm_deassign_device(struct domain *d, uint32_t machine_bdf)=0A+{=0A+ = return xsm_call(deassign_device(d, machine_bdf));=0A+}=0A+=0A static = inline long __do_xsm_op (XEN_GUEST_HANDLE(xsm_op_t) op)=0A {=0A #ifdef = XSM_ENABLE=0A@@ -612,21 +628,6 @@ static inline int xsm_sendtrigger(struct= =0A return xsm_call(sendtrigger(d));=0A }=0A =0A-static inline int = xsm_test_assign_device(uint32_t machine_bdf)=0A-{=0A- return xsm_call(te= st_assign_device(machine_bdf));=0A-}=0A-=0A-static inline int xsm_assign_de= vice(struct domain *d, uint32_t machine_bdf)=0A-{=0A- return xsm_call(as= sign_device(d, machine_bdf));=0A-}=0A-=0A-static inline int xsm_deassign_de= vice(struct domain *d, uint32_t machine_bdf)=0A-{=0A- return xsm_call(de= assign_device(d, machine_bdf));=0A-}=0A-=0A static inline int xsm_bind_pt_i= rq(struct domain *d, =0A = struct xen_domctl_bind_pt_irq *bind)=0A {=0A --=__PartEFC0113E.0__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 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[86.129.245.239]) by mx.google.com with ESMTPS id x8sm7228238wix.17.2011.11.11.08.40.03 (version=SSLv3 cipher=OTHER); Fri, 11 Nov 2011 08:40:03 -0800 (PST) User-Agent: Microsoft-Entourage/12.31.0.110725 Date: Fri, 11 Nov 2011 16:40:00 +0000 Subject: Re: [Xen-devel] [PATCH] ia64: introduce atomic_{read,write}NN() From: Keir Fraser To: Jan Beulich , "xen-devel@lists.xensource.com" Message-ID: Thread-Topic: [Xen-devel] [PATCH] ia64: introduce atomic_{read,write}NN() Thread-Index: AcygkI2zldpmezpHLE6ZR2Nl2Kpzyw== In-Reply-To: <4EBD56C50200007800060781@nat28.tlf.novell.com> Mime-version: 1.0 Content-type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Cc: xen-ia64-devel@lists.xensource.com X-BeenThere: xen-devel@lists.xensource.com X-Mailman-Version: 2.1.5 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com On 11/11/2011 16:09, "Jan Beulich" wrote: > These are required to be able to build certain portions of common code. > > Signed-off-by: Jan Beulich Acked-by: Keir Fraser > --- a/xen/include/asm-ia64/linux-xen/asm/atomic.h > +++ b/xen/include/asm-ia64/linux-xen/asm/atomic.h > @@ -24,12 +24,9 @@ typedef struct { volatile __s32 counter; > typedef struct { volatile __s64 counter; } atomic64_t; > > #ifndef XEN > + > #define ATOMIC_INIT(i) ((atomic_t) { (i) }) > #define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) > -#else > -#define ATOMIC_INIT(i) { (i) } > -#define ATOMIC64_INIT(i) { (i) } > -#endif > > #define atomic_read(v) ((v)->counter) > #define atomic64_read(v) ((v)->counter) > @@ -37,6 +34,55 @@ typedef struct { volatile __s64 counter; > #define atomic_set(v,i) (((v)->counter) = (i)) > #define atomic64_set(v,i) (((v)->counter) = (i)) > > +#else > + > +#define ATOMIC_INIT(i) { (i) } > +#define ATOMIC64_INIT(i) { (i) } > + > +#define build_atomic_read(tag, type) \ > +static inline type atomic_read##tag(const volatile type *addr) \ > +{ \ > + type ret; \ > + asm volatile("ld%2.acq %0 = %1" \ > + : "=r" (ret) \ > + : "m" (*addr), "i" (sizeof(type))); \ > + return ret; \ > +} > + > +#define build_atomic_write(tag, type) \ > +static inline void atomic_write##tag(volatile type *addr, type val) \ > +{ \ > + asm volatile("st%2.rel %0 = %1" \ > + : "=m" (*addr) \ > + : "r" (val), "i" (sizeof(type))); \ > +} > + > +build_atomic_read(8, uint8_t) > +build_atomic_read(16, uint16_t) > +build_atomic_read(32, uint32_t) > +build_atomic_read(64, uint64_t) > +build_atomic_read(_int, int) > +build_atomic_read(_long, long) > + > +build_atomic_write(8, uint8_t) > +build_atomic_write(16, uint16_t) > +build_atomic_write(32, uint32_t) > +build_atomic_write(64, uint64_t) > +build_atomic_write(_int, int) > +build_atomic_write(_long, long) > + > +#define _atomic_read(v) ((v).counter) > +#define _atomic64_read(v) ((v).counter) > +#define atomic_read(v) atomic_read_int(&((v)->counter)) > +#define atomic64_read(v) atomic_read_long(&((v)->counter)) > + > +#define _atomic_set(v,i) (((v).counter) = (i)) > +#define _atomic64_set(v,i) (((v).counter) = (i)) > +#define atomic_set(v,i) atomic_write_int(&((v)->counter), i) > +#define atomic64_set(v,l) atomic_write_long(&((v)->counter), l) > + > +#endif > + > static __inline__ int > ia64_atomic_add (int i, atomic_t *v) > { > @@ -59,7 +105,7 @@ ia64_atomic64_add (__s64 i, atomic64_t * > > do { > CMPXCHG_BUGCHECK(v); > - old = atomic_read(v); > + old = atomic64_read(v); > new = old + i; > } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); > return new; > @@ -87,7 +133,7 @@ ia64_atomic64_sub (__s64 i, atomic64_t * > > do { > CMPXCHG_BUGCHECK(v); > - old = atomic_read(v); > + old = atomic64_read(v); > new = old - i; > } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); > return new; > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel