From xen-announce-bounces@lists.xenproject.org Tue Jun 09 17:01:37 2020 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 09 Jun 2020 17:01:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jihcE-0005Ed-Ev; Tue, 09 Jun 2020 17:00:46 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jihcD-0005Dl-Rg for xen-announce@lists.xen.org; Tue, 09 Jun 2020 17:00:45 +0000 X-Inumbo-ID: bb47a184-aa72-11ea-b343-12813bfff9fa Received: from mail.xenproject.org (unknown [104.130.215.37]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id bb47a184-aa72-11ea-b343-12813bfff9fa; Tue, 09 Jun 2020 17:00:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=ibrw2dMw1jlbrjnlYVNU0hHtjOZsr2v2S82Tbvvu8G0=; b=V+zw+wubzFhbqVzyZJ2jWp1Li/ ZrQwbJkmu+d1jHIKFtoYLHVi70YprffYUzZtZN91jf+34IBKELLxVsg91DY0kE8t1v46XyFg039IX ooaAICh83D2LsQ5q55X5GvIQxPmlJeNzsN82slx2RSJLOpSgOitP7PgVP8q1WTg4GZQw=; Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jihbt-0004Bc-3n; Tue, 09 Jun 2020 17:00:25 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1jihbt-0000Ja-1n; Tue, 09 Jun 2020 17:00:25 +0000 Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team Subject: Xen Security Advisory 320 v1 (CVE-2020-0543) - Special Register Buffer speculative side channel Message-Id: Date: Tue, 09 Jun 2020 17:00:25 +0000 X-BeenThere: xen-announce@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Xen announcements \(low volume\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: "Xen.org security team" Errors-To: xen-announce-bounces@lists.xenproject.org Sender: "Xen-announce" --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2020-0543 / XSA-320 Special Register Buffer speculative side channel ISSUE DESCRIPTION ================= This issue is related to the MDS and TAA vulnerabilities. Please see https://xenbits.xen.org/xsa/advisory-297.html (MDS) and https://xenbits.xen.org/xsa/advisory-305.html (TAA) for details. Certain processor operations microarchitecturally need to read data from outside the physical core (e.g. to communicate with the random number generator). In some implementations, this operation is called a Special Register Read. In some implementations, data are staged in a single shared buffer, and a full cache line at a time is returned to the core which made the Special Register Read. On parts vulnerable to MFBDS or TAA, an attacker may be able to access stale data requested by other cores in the system. For more details, see: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html IMPACT ====== An attacker, which could include a malicious untrusted user process on a trusted guest, or an untrusted guest, can sample the contents of certain off-core accesses by other cores in the system. This can include data whose use may depend on the secrecy of the value, such as data from the Random Number Generator (e.g. RDRAND/RDSEED instructions). VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Only x86 processors are vulnerable. ARM processors are not believed to be vulnerable. Only Intel based processors are affected. Processors from other manufacturers (e.g. AMD) are not believed to be vulnerable. Please consult the Intel Security Advisory for details on the affected processors. MITIGATION ========== There is no mitigation available. RESOLUTION ========== New microcode is being released on affected parts to work around the vulnerability. It may be available via a firmware update (consult your hardware vendor), or available for OS loading (consult your dom0 OS vendor). On Xen 4.13 and later, OS microcode can be loaded at runtime. See https://xenbits.xen.org/docs/latest/admin-guide/microcode-loading.html#runtime-microcode-loading for details on the xen-ucode utility. Loading the microcode, either at boot or at runtime, suffices to mitigate the issue, as protections are active by default. The mitigations do have an impact on latency of individual RDRAND/RDSEED instructions. The patches below are for Xen, and offer boot time information, defaults selection, and opt-out controls. They are recommended to take, but not absolutely necessary for protection. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa320/xsa320-?.patch xen-unstable xsa320/xsa320-4.13-?.patch Xen 4.13.x xsa320/xsa320-4.12-?.patch Xen 4.12.x xsa320/xsa320-4.11-?.patch Xen 4.11.x xsa320/xsa320-4.10-?.patch Xen 4.10.x xsa320/xsa320-4.9-?.patch Xen 4.9.x $ sha256sum xsa320*/* 84e4f66492042b08e69b0894ea7feb20c17c89a696cf95f05a8826fba4f26355 xsa320/xsa320-1.patch 5a3a06c72d0281fa1191ba18e39b836d2748400d9bf6a59dd45447850530c88b xsa320/xsa320-2.patch 759259ef88c980363d44e11d9c272f6a4a15918e5e6bcdfe971b1ce7ea160cd9 xsa320/xsa320-4.9-1.patch ebac2c011841c55c3c1e99d9e8afc53e56e54268d379ec8b904f6bfe6a1a5045 xsa320/xsa320-4.9-2.patch 5c622c74358ab21cbd27484c649f26df0f08e89ec333c346415bc51e35ba26c1 xsa320/xsa320-4.10-1.patch f112e34a6a4564a043926fc255a15c7e319001bd023a97ae2947228024e1c306 xsa320/xsa320-4.10-2.patch f24b51292be0cb5de80c6eff0b26983629dd48cc39ae5a331e2e38e15a6cf712 xsa320/xsa320-4.11-1.patch 03579810eaf2e9eeb1a82de4b50ff5c4b01e60b30ccf7609c9e3378ef576d81e xsa320/xsa320-4.11-2.patch 282537ffe2fd4332c0e061ddc537bea3e135a7bbd9253ec298becb49047323cf xsa320/xsa320-4.12-1.patch e4417429297354c233e8f5c261aff4888aae602f8c68897c09b16ea1aa44b1ca xsa320/xsa320-4.12-2.patch 611f2ab1a1c67e04767188d9803b6afd7d304e81a5b4f1eb1744d3e8a68ced66 xsa320/xsa320-4.13-1.patch cd1bc0071e72e2342ff4508ea3d937988694f4c03506b3afb3184f7d81aa1c86 xsa320/xsa320-4.13-2.patch $ NOTE REGARDING LACK OF EMBARGO ============================== Despite an attempt to organise predisclosure, the discoverers ultimately did not authorise a predisclosure. -----BEGIN PGP SIGNATURE----- iQFABAEBCAAqFiEEI+MiLBRfRHX6gGCng/4UyVfoK9kFAl7fufEMHHBncEB4ZW4u b3JnAAoJEIP+FMlX6CvZCNgIALz6dLCvvznL7n3HFzYgKcelmOySjoZ52hJhg6ki N4C1AaPQmo1QPprycmuJ4uQIcLUP55Nh+h19V5PnRqSX1+7Qa8TXnv2TTpVK58fC JBfWBZ3xiXYdmaQOWYlJtD1Nq3vywA0LII9TZ7JdCUxjmPxn2y5ZOv6lRG6P9CVJ U+w3py0Zt32ZwYvVCbBPP49SdQmArH2BItEbGSQR5xeKnD/8Bx2/9odN0Mrnq5RQ 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MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team Subject: Xen Security Advisory 320 v2 (CVE-2020-0543) - Special Register Buffer speculative side channel Message-Id: Date: Thu, 11 Jun 2020 13:10:11 +0000 X-BeenThere: xen-announce@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Xen announcements \(low volume\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: "Xen.org security team" Errors-To: xen-announce-bounces@lists.xenproject.org Sender: "Xen-announce" --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2020-0543 / XSA-320 version 2 Special Register Buffer speculative side channel UPDATES IN VERSION 2 ==================== Add a link to Intel's cross reference of affected hardware. Provide a suggested workaround for Ivy Bridge hardware, which is not receiving a microcode update. This includes a 3rd patch for each release. ISSUE DESCRIPTION ================= This issue is related to the MDS and TAA vulnerabilities. Please see https://xenbits.xen.org/xsa/advisory-297.html (MDS) and https://xenbits.xen.org/xsa/advisory-305.html (TAA) for details. Certain processor operations microarchitecturally need to read data from outside the physical core (e.g. to communicate with the random number generator). In some implementations, this operation is called a Special Register Read. In some implementations, data are staged in a single shared buffer, and a full cache line at a time is returned to the core which made the Special Register Read. On parts vulnerable to MFBDS or TAA, an attacker may be able to access stale data requested by other cores in the system. For more details, see: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html https://software.intel.com/security-software-guidance/processors-affected-transient-execution-attack-mitigation-product-cpu-model IMPACT ====== An attacker, which could include a malicious untrusted user process on a trusted guest, or an untrusted guest, can sample the contents of certain off-core accesses by other cores in the system. This can include data whose use may depend on the secrecy of the value, such as data from the Random Number Generator (e.g. RDRAND/RDSEED instructions). VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Only x86 processors are vulnerable. ARM processors are not believed to be vulnerable. Only Intel based processors are affected. Processors from other manufacturers (e.g. AMD) are not believed to be vulnerable. Please consult the Intel Security Advisory for details on the affected processors. MITIGATION ========== Disabling RDRAND (and, where applicable, RDSEED) will avoid the vulnerability. It may have other adverse consequences, such as guests generating keys with weak random numbers, or guests hanging during boot waiting for entropy. A domain (guest, dom0, or service domain) which is runs with RDRAND disabled in CPUID, and whose software conforms to normal feature detection as specified in the Intel/AMD manuals, will not be vulnerable to snooping by other domains. But such a domain *can* still potentially snoop on any domains which are still using RDRAND. This mitigation is recommended to be applied globally, due to the practical complexity of auditing all software in a VM to confirm that there are no vulnerable uses of the RDRAND/RDSEED instructions. RDRAND and RDSEED can be disabled at the host level by booting Xen with `cpuid=no-rdrand,no-rdseed`, which will hide the feature from all domains including guests and dom0. Xen 4.12 and earlier require the appropriate patch 3 below for this mechanism to work. RDRAND and RDSEED can be disabled for guests with the following setting in the VM configuration file (xl.cfg): cpuid=["host:rdrand=0,rdseed=0]" (NB it would have to be merged into any existing cpuid= setting). Xen 4.9 and earlier require the appropriate patch 3 below for this mechanism to work. RESOLUTION ========== New microcode is being released on some affected parts to work around the vulnerability. It may be available via a firmware update (consult your hardware vendor), or available for OS loading (consult your dom0 OS vendor). For Ivy Bridge hardware, which is not receiving a microcode update, see MITIGATION, above. On Xen 4.13 and later, OS microcode can be loaded at runtime. See https://xenbits.xen.org/docs/latest/admin-guide/microcode-loading.html#runtime-microcode-loading for details on the xen-ucode utility. Loading the microcode, either at boot or at runtime, suffices to mitigate the issue, as protections are active by default. The mitigations do have an impact on latency of individual RDRAND/RDSEED instructions. The patches below are for Xen, and offer boot time information, defaults selection, opt-out controls, and uniform controls for hiding the RDRAND/RDSEED instructions. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa320/xsa320-?.patch xen-unstable xsa320/xsa320-4.13-?.patch Xen 4.13.x xsa320/xsa320-4.12-?.patch Xen 4.12.x xsa320/xsa320-4.11-?.patch Xen 4.11.x xsa320/xsa320-4.10-?.patch Xen 4.10.x xsa320/xsa320-4.9-?.patch Xen 4.9.x $ sha256sum xsa320*/* 84e4f66492042b08e69b0894ea7feb20c17c89a696cf95f05a8826fba4f26355 xsa320/xsa320-1.patch 5a3a06c72d0281fa1191ba18e39b836d2748400d9bf6a59dd45447850530c88b xsa320/xsa320-2.patch fd15c8a5098ce70af85c6cf1f69f1e6b51eabfda0a0bb780b27f47a8ae44e3a2 xsa320/xsa320-3.patch 759259ef88c980363d44e11d9c272f6a4a15918e5e6bcdfe971b1ce7ea160cd9 xsa320/xsa320-4.9-1.patch ebac2c011841c55c3c1e99d9e8afc53e56e54268d379ec8b904f6bfe6a1a5045 xsa320/xsa320-4.9-2.patch 3aeade2c9bb1fe77f6c076d531378d3971aa44cdb87996bda27565fa6e707bd2 xsa320/xsa320-4.9-3.patch 5c622c74358ab21cbd27484c649f26df0f08e89ec333c346415bc51e35ba26c1 xsa320/xsa320-4.10-1.patch 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