From xen-arm-bounces@lists.xen.org Fri Apr 04 08:23:39 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Apr 2014 08:23:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzPS-0002ak-8N; Fri, 04 Apr 2014 08:23:34 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzPQ-0002ac-CX; Fri, 04 Apr 2014 08:23:32 +0000 Received: from [85.158.139.211:25306] by server-11.bemta-5.messagelabs.com id FE/09-30804-30C6E335; Fri, 04 Apr 2014 08:23:31 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-4.tower-206.messagelabs.com!1396599810!5409705!1 X-Originating-IP: [195.245.231.148] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTk1LjI0NS4yMzEuMTQ4ID0+IDU5MTI=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10034 invoked from network); 4 Apr 2014 08:23:30 -0000 Received: from mail1.bemta5.messagelabs.com (HELO mail1.bemta5.messagelabs.com) (195.245.231.148) by server-4.tower-206.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 4 Apr 2014 08:23:30 -0000 Received: from [85.158.139.51:2200] by server-12.bemta-5.messagelabs.com id 35/50-03824-20C6E335; Fri, 04 Apr 2014 08:23:30 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-5.tower-180.messagelabs.com!1396599809!28516556!1 X-Originating-IP: [194.121.90.173] X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22525 invoked from network); 4 Apr 2014 08:23:30 -0000 Received: from unassigned (HELO HIKAWSEX02.ad.harman.com) (194.121.90.173) by server-5.tower-180.messagelabs.com with AES128-SHA encrypted SMTP; 4 Apr 2014 08:23:30 -0000 Received: from HIKAWSEX01.ad.harman.com ([fe80::f023:31d4:f809:b22e]) by HIKAWSEX02.ad.harman.com ([172.16.1.216]) with mapi; Fri, 4 Apr 2014 10:22:31 +0200 From: "Khandelwal, Shubham" To: xen-devel , "'xen-arm@lists.xen.org'" , 'Stefano Stabellini' Date: Fri, 4 Apr 2014 10:22:30 +0200 Thread-Topic: Understanding XEN on ARM Thread-Index: Ac9P3wOHOQnAbMaRQqmi8t0jbxjIkw== Message-ID: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Cc: "Datta, Souvik" Subject: [XenARM] Understanding XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8425987623100157359==" Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org --===============8425987623100157359== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_" --_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, I am trying to understand the source code of XEN on ARM to get a deeper und= erstanding of how XEN works and I am facing some difficulties in understand= ing a section of the assembly code present in xen/arch/arm/arm32/head.S. The snippet of the code is: /* Rebuild the boot pagetable's first-level entries. The structure * is described in mm.c. * * After the CPU enables paging it will add the fixmap mapping * to these page tables, however this may clash with the 1:1 * mapping. So each CPU must rebuild the page tables here with * the 1:1 in place. */ /* Write Xen's PT's paddr into the HTTBR */ ldr r4, =3Dboot_pgtable add r4, r4, r10 /* r4 :=3D paddr (boot_pagetable) */ mov r5, #0 /* r4:r5 is paddr (boot_pagetable) */ mcrr CP64(r4, r5, HTTBR) /* Setup boot_pgtable: */ ldr r1, =3Dboot_second add r1, r1, r10 /* r1 :=3D paddr (boot_second) */ mov r3, #0x0 /* ... map boot_second in boot_pgtable[0] */ orr r2, r1, #PT_UPPER(PT) /* r2:r3 :=3D table map of boot_second= */ orr r2, r2, #PT_LOWER(PT) /* (+ rights for linear PT) */ strd r2, r3, [r4, #0] /* Map it in slot 0 */ /* ... map of paddr(start) in boot_pgtable */ lsrs r1, r9, #30 /* Offset of base paddr in boot_pgtabl= e */ beq 1f /* If it is in slot 0 then map in boot= _second * later on */ lsl r2, r1, #30 /* Base address for 1GB mapping */ orr r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */ orr r2, r2, #PT_LOWER(MEM) lsl r1, r1, #3 /* r1 :=3D Slot offset */ strd r2, r3, [r4, r1] /* Mapping of paddr(start) */ 1: /* Setup boot_second: */ ldr r4, =3Dboot_second add r4, r4, r10 /* r1 :=3D paddr (boot_second) */ lsr r2, r9, #20 /* Base address for 2MB mapping */ lsl r2, r2, #20 orr r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */ orr r2, r2, #PT_LOWER(MEM) /* ... map of vaddr(start) in boot_second */ ldr r1, =3Dstart lsr r1, #18 /* Slot for vaddr(start) */ strd r2, r3, [r4, r1] /* Map vaddr(start) */ /* ... map of paddr(start) in boot_second */ lsrs r1, r9, #30 /* Base paddr */ bne 1f /* If paddr(start) is not in slot 0 * then the mapping was done in * boot_pgtable above */ mov r1, r9, lsr #18 /* Slot for paddr(start) */ strd r2, r3, [r4, r1] /* Map Xen there */ 1: /* Defer fixmap and dtb mapping until after paging enabled, to * avoid them clashing with the 1:1 mapping. */ /* boot pagetable setup complete */ PRINT("- Turning on paging -\r\n") ldr r1, =3Dpaging /* Explicit vaddr, not RIP-relative = */ mrc CP32(r0, HSCTLR) orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */ dsb /* Flush PTE writes and finish reads *= / mcr CP32(r0, HSCTLR) /* now paging is enabled */ isb /* Now, flush the icache */ mov pc, r1 /* Get a proper vaddr into PC */ paging: /* Now we can install the fixmap and dtb mappings, since we * don't need the 1:1 map any more */ dsb #if defined(EARLY_PRINTK) /* Fixmap is only used by early printk */ /* Non-boot CPUs don't need to rebuild the fixmap itself, just * the mapping from boot_second to xen_fixmap */ teq r12, #0 bne 1f /* Add UART to the fixmap table */ ldr r1, =3Dxen_fixmap /* r1 :=3D vaddr (xen_fixmap) */ mov r3, #0 lsr r2, r11, #12 lsl r2, r2, #12 /* 4K aligned paddr of UART */ orr r2, r2, #PT_UPPER(DEV_L3) orr r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 :=3D 4K dev map including = UART */ strd r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixm= ap's slot */ 1: /* Map fixmap into boot_second */ ldr r1, =3Dboot_second /* r1 :=3D vaddr (xen_fixmap) */ ldr r2, =3Dxen_fixmap add r2, r2, r10 /* r2 :=3D paddr (xen_fixmap) */ orr r2, r2, #PT_UPPER(PT) orr r2, r2, #PT_LOWER(PT) /* r2:r3 :=3D table map of xen_fixmap = */ ldr r4, =3DFIXMAP_ADDR(0) mov r4, r4, lsr #18 /* r4 :=3D Slot for FIXMAP(0) */ strd r2, r3, [r1, r4] /* Map it in the fixmap's slot */ /* Use a virtual address to access the UART. */ ldr r11, =3DEARLY_UART_VIRTUAL_ADDRESS #endif /* Map the DTB in the boot misc slot */ teq r12, #0 /* Only on boot CPU */ bne 1f ldr r1, =3Dboot_second mov r3, #0x0 lsr r2, r8, #21 lsl r2, r2, #21 /* r2: 2MB-aligned paddr of DTB */ orr r2, r2, #PT_UPPER(MEM) orr r2, r2, #PT_LOWER(MEM) /* r2:r3 :=3D 2MB RAM incl. DTB */ ldr r4, =3DBOOT_FDT_VIRT_START mov r4, r4, lsr #18 /* Slot for BOOT_FDT_VIRT_START */ strd r2, r3, [r1, r4] /* Map it in the early fdt slot */ dsb 1: It will be great help if anyone can throw some light on the function of the= above piece of code. Thanks & Regards Shubham Khandelwal --_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

 

I am trying to understand the source code of XEN on AR= M to get a deeper understanding of how XEN works and I am facing some difficulti= es in understanding a section of the assembly code present in xen/arch/arm/arm= 32/head.S.

 

The snippet of the code is:

 

 

        /* Rebuild the boot pagetable's first-level entries. The structure

         * is described in mm.c.

         *

         * After the CPU enables paging it will add the fixmap mapping

         * to these page tables, however this may clash with the 1:1

         * mapping. So each CPU must rebuild the page tables here with

         * the 1:1 in place. */

 

        /* Write Xen's PT's paddr into the HTTBR */

        ldr   r4, =3Dboot_pgtable

        add   r4, r4, r10            /* r4= :=3D paddr (boot_pagetable) */

        mov   r5, #0            &= nbsp;    /* r4:r5 is paddr (boot_pagetable) */

        mcrr  CP64(r4, r5, HTTBR)

 

        /* Setup boot_pgtable: */

        ldr   r1, =3Dboot_second

        add   r1, r1, r10            /* r1= :=3D paddr (boot_second) */

        mov   r3, #0x0

 

        /* ... map boot_second in boot_pgtable[0] */

        orr   r2, r1, #PT_UPPER(PT)  /* r2:r3 :=3D table map of boot_second */

        orr   r2, r2, #PT_LOWER(PT)  /* (+ rights for linear PT) */<= o:p>

        strd  r2, r3, [r4, #0]       /* Map it i= n slot 0 */

 

        /* ... map of paddr(start) in boot_pgtable */

        lsrs  r1, r9, #30            /* Of= fset of base paddr in boot_pgtable */

        beq   1f            &= nbsp;        /* If it is in slot 0 then map in boot_second

         &= nbsp;           &nbs= p;            &= nbsp;   * later on */

        lsl   r2, r1, #30            /* Ba= se address for 1GB mapping */

        orr   r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */

        orr   r2, r2, #PT_LOWER(MEM)

        lsl   r1, r1, #3             = /* r1 :=3D Slot offset */

        strd  r2, r3, [r4, r1]       /* Mapping = of paddr(start) */

 

1:      /* Setup boot_second: */

        ldr   r4, =3Dboot_second

        add   r4, r4, r10            /* r1= :=3D paddr (boot_second) */

 

        lsr   r2, r9, #20            /* Ba= se address for 2MB mapping */

        lsl   r2, r2, #20

        orr   r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */

        orr   r2, r2, #PT_LOWER(MEM)

 

        /* ... map of vaddr(start) in boot_second */

        ldr   r1, =3Dstart

        lsr   r1, #18            =     /* Slot for vaddr(start) */

        strd  r2, r3, [r4, r1]       /* Map vaddr(start) */

 

        /* ... map of paddr(start) in boot_second */

        lsrs  r1, r9, #30            /* Ba= se paddr */

        bne   1f            &= nbsp;        /* If paddr(start) is not in slot 0

         &= nbsp;           &nbs= p;            &= nbsp;   * then the mapping was done in

         &= nbsp;           &nbs= p;            &= nbsp;   * boot_pgtable above */

 

        mov   r1, r9, lsr #18        /= * Slot for paddr(start) */

        strd  r2, r3, [r4, r1]       /* Map Xen there */

1:

 

        /* Defer fixmap and dtb mapping until after paging enabled, to

         * avoid them clashing with the 1:1 mapping. */

 

        /* boot pagetable setup complete */

 

        PRINT("- Turning on paging -\r\n")

 

        ldr   r1, =3Dpaging           = /* Explicit vaddr, not RIP-relative */

        mrc   CP32(r0, HSCTLR)

        orr   r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */

        dsb            =             &nb= sp; /* Flush PTE writes and finish reads */

        mcr   CP32(r0, HSCTLR)       /* now paging is enabled */

        isb            =             &nb= sp; /* Now, flush the icache */

        mov   pc, r1            &= nbsp;    /* Get a proper vaddr into PC */

paging:

 

        /* Now we can install the fixmap and dtb mappings, since we

         * don't need the 1:1 map any more */

        dsb

#if defined(EARLY_PRINTK) /* Fixmap is only used by early printk */<= /span>

        /* Non-boot CPUs don't need to rebuild the fixmap itself, just

         &= nbsp;   * the mapping from boot_second to xen_fixmap */

        teq   r12, #0

        bne   1f

 

        /* Add UART to the fixmap table */

        ldr   r1, =3Dxen_fixmap       = /* r1 :=3D vaddr (xen_fixmap) */

        mov   r3, #0

        lsr   r2, r11, #12

        lsl   r2, r2, #12            /* 4K aligned paddr of UART */

        orr   r2, r2, #PT_UPPER(DEV_L3)

        orr   r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 :=3D 4K dev map includin= g UART */

        strd  r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixmap'= s slot */

1:

 

        /* Map fixmap into boot_second */

        ldr   r1, =3Dboot_second       /* r= 1 :=3D vaddr (xen_fixmap) */

        ldr   r2, =3Dxen_fixmap

        add   r2, r2, r10            /* r2= :=3D paddr (xen_fixmap) */

        orr   r2, r2, #PT_UPPER(PT)

        orr   r2, r2, #PT_LOWER(PT)  /* r2:r3 :=3D table map of xen_= fixmap */

        ldr   r4, =3DFIXMAP_ADDR(0)

        mov   r4, r4, lsr #18        /= * r4 :=3D Slot for FIXMAP(0) */

        strd  r2, r3, [r1, r4]       /* Map it i= n the fixmap's slot */

 

        /* Use a virtual address to access the UART. */

        ldr   r11, =3DEARLY_UART_VIRTUAL_ADDRESS

#endif

        /* Map the DTB in the boot misc slot */

        teq   r12, #0            &= nbsp;   /* Only on boot CPU */

        bne   1f

 

        ldr   r1, =3Dboot_second

        mov   r3, #0x0

        lsr   r2, r8, #21

        lsl   r2, r2, #21            /* r2= : 2MB-aligned paddr of DTB */

        orr   r2, r2, #PT_UPPER(MEM)

        orr   r2, r2, #PT_LOWER(MEM) /* r2:r3 :=3D 2MB RAM incl. DTB */

        ldr   r4, =3DBOOT_FDT_VIRT_START

        mov   r4, r4, lsr #18        /= * Slot for BOOT_FDT_VIRT_START */

        strd  r2, r3, [r1, r4]       /* Map it i= n the early fdt slot */

        dsb

1:

 

 

It will be great help if anyone can throw some light o= n the function of the above piece of code.

 

Thanks & Regards

 

Shubham Khandelwal

 

--_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_-- --===============8425987623100157359== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm --===============8425987623100157359==-- From xen-arm-bounces@lists.xen.org Fri Apr 04 08:23:39 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Apr 2014 08:23:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzPS-0002ak-8N; Fri, 04 Apr 2014 08:23:34 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzPQ-0002ac-CX; Fri, 04 Apr 2014 08:23:32 +0000 Received: from [85.158.139.211:25306] by server-11.bemta-5.messagelabs.com id FE/09-30804-30C6E335; Fri, 04 Apr 2014 08:23:31 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-4.tower-206.messagelabs.com!1396599810!5409705!1 X-Originating-IP: [195.245.231.148] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTk1LjI0NS4yMzEuMTQ4ID0+IDU5MTI=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10034 invoked from network); 4 Apr 2014 08:23:30 -0000 Received: from mail1.bemta5.messagelabs.com (HELO mail1.bemta5.messagelabs.com) (195.245.231.148) by server-4.tower-206.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 4 Apr 2014 08:23:30 -0000 Received: from [85.158.139.51:2200] by server-12.bemta-5.messagelabs.com id 35/50-03824-20C6E335; Fri, 04 Apr 2014 08:23:30 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-5.tower-180.messagelabs.com!1396599809!28516556!1 X-Originating-IP: [194.121.90.173] X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22525 invoked from network); 4 Apr 2014 08:23:30 -0000 Received: from unassigned (HELO HIKAWSEX02.ad.harman.com) (194.121.90.173) by server-5.tower-180.messagelabs.com with AES128-SHA encrypted SMTP; 4 Apr 2014 08:23:30 -0000 Received: from HIKAWSEX01.ad.harman.com ([fe80::f023:31d4:f809:b22e]) by HIKAWSEX02.ad.harman.com ([172.16.1.216]) with mapi; Fri, 4 Apr 2014 10:22:31 +0200 From: "Khandelwal, Shubham" To: xen-devel , "'xen-arm@lists.xen.org'" , 'Stefano Stabellini' Date: Fri, 4 Apr 2014 10:22:30 +0200 Thread-Topic: Understanding XEN on ARM Thread-Index: Ac9P3wOHOQnAbMaRQqmi8t0jbxjIkw== Message-ID: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Cc: "Datta, Souvik" Subject: [XenARM] Understanding XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8425987623100157359==" Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org --===============8425987623100157359== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_" --_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, I am trying to understand the source code of XEN on ARM to get a deeper und= erstanding of how XEN works and I am facing some difficulties in understand= ing a section of the assembly code present in xen/arch/arm/arm32/head.S. The snippet of the code is: /* Rebuild the boot pagetable's first-level entries. The structure * is described in mm.c. * * After the CPU enables paging it will add the fixmap mapping * to these page tables, however this may clash with the 1:1 * mapping. So each CPU must rebuild the page tables here with * the 1:1 in place. */ /* Write Xen's PT's paddr into the HTTBR */ ldr r4, =3Dboot_pgtable add r4, r4, r10 /* r4 :=3D paddr (boot_pagetable) */ mov r5, #0 /* r4:r5 is paddr (boot_pagetable) */ mcrr CP64(r4, r5, HTTBR) /* Setup boot_pgtable: */ ldr r1, =3Dboot_second add r1, r1, r10 /* r1 :=3D paddr (boot_second) */ mov r3, #0x0 /* ... map boot_second in boot_pgtable[0] */ orr r2, r1, #PT_UPPER(PT) /* r2:r3 :=3D table map of boot_second= */ orr r2, r2, #PT_LOWER(PT) /* (+ rights for linear PT) */ strd r2, r3, [r4, #0] /* Map it in slot 0 */ /* ... map of paddr(start) in boot_pgtable */ lsrs r1, r9, #30 /* Offset of base paddr in boot_pgtabl= e */ beq 1f /* If it is in slot 0 then map in boot= _second * later on */ lsl r2, r1, #30 /* Base address for 1GB mapping */ orr r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */ orr r2, r2, #PT_LOWER(MEM) lsl r1, r1, #3 /* r1 :=3D Slot offset */ strd r2, r3, [r4, r1] /* Mapping of paddr(start) */ 1: /* Setup boot_second: */ ldr r4, =3Dboot_second add r4, r4, r10 /* r1 :=3D paddr (boot_second) */ lsr r2, r9, #20 /* Base address for 2MB mapping */ lsl r2, r2, #20 orr r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */ orr r2, r2, #PT_LOWER(MEM) /* ... map of vaddr(start) in boot_second */ ldr r1, =3Dstart lsr r1, #18 /* Slot for vaddr(start) */ strd r2, r3, [r4, r1] /* Map vaddr(start) */ /* ... map of paddr(start) in boot_second */ lsrs r1, r9, #30 /* Base paddr */ bne 1f /* If paddr(start) is not in slot 0 * then the mapping was done in * boot_pgtable above */ mov r1, r9, lsr #18 /* Slot for paddr(start) */ strd r2, r3, [r4, r1] /* Map Xen there */ 1: /* Defer fixmap and dtb mapping until after paging enabled, to * avoid them clashing with the 1:1 mapping. */ /* boot pagetable setup complete */ PRINT("- Turning on paging -\r\n") ldr r1, =3Dpaging /* Explicit vaddr, not RIP-relative = */ mrc CP32(r0, HSCTLR) orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */ dsb /* Flush PTE writes and finish reads *= / mcr CP32(r0, HSCTLR) /* now paging is enabled */ isb /* Now, flush the icache */ mov pc, r1 /* Get a proper vaddr into PC */ paging: /* Now we can install the fixmap and dtb mappings, since we * don't need the 1:1 map any more */ dsb #if defined(EARLY_PRINTK) /* Fixmap is only used by early printk */ /* Non-boot CPUs don't need to rebuild the fixmap itself, just * the mapping from boot_second to xen_fixmap */ teq r12, #0 bne 1f /* Add UART to the fixmap table */ ldr r1, =3Dxen_fixmap /* r1 :=3D vaddr (xen_fixmap) */ mov r3, #0 lsr r2, r11, #12 lsl r2, r2, #12 /* 4K aligned paddr of UART */ orr r2, r2, #PT_UPPER(DEV_L3) orr r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 :=3D 4K dev map including = UART */ strd r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixm= ap's slot */ 1: /* Map fixmap into boot_second */ ldr r1, =3Dboot_second /* r1 :=3D vaddr (xen_fixmap) */ ldr r2, =3Dxen_fixmap add r2, r2, r10 /* r2 :=3D paddr (xen_fixmap) */ orr r2, r2, #PT_UPPER(PT) orr r2, r2, #PT_LOWER(PT) /* r2:r3 :=3D table map of xen_fixmap = */ ldr r4, =3DFIXMAP_ADDR(0) mov r4, r4, lsr #18 /* r4 :=3D Slot for FIXMAP(0) */ strd r2, r3, [r1, r4] /* Map it in the fixmap's slot */ /* Use a virtual address to access the UART. */ ldr r11, =3DEARLY_UART_VIRTUAL_ADDRESS #endif /* Map the DTB in the boot misc slot */ teq r12, #0 /* Only on boot CPU */ bne 1f ldr r1, =3Dboot_second mov r3, #0x0 lsr r2, r8, #21 lsl r2, r2, #21 /* r2: 2MB-aligned paddr of DTB */ orr r2, r2, #PT_UPPER(MEM) orr r2, r2, #PT_LOWER(MEM) /* r2:r3 :=3D 2MB RAM incl. DTB */ ldr r4, =3DBOOT_FDT_VIRT_START mov r4, r4, lsr #18 /* Slot for BOOT_FDT_VIRT_START */ strd r2, r3, [r1, r4] /* Map it in the early fdt slot */ dsb 1: It will be great help if anyone can throw some light on the function of the= above piece of code. Thanks & Regards Shubham Khandelwal --_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

 

I am trying to understand the source code of XEN on AR= M to get a deeper understanding of how XEN works and I am facing some difficulti= es in understanding a section of the assembly code present in xen/arch/arm/arm= 32/head.S.

 

The snippet of the code is:

 

 

        /* Rebuild the boot pagetable's first-level entries. The structure

         * is described in mm.c.

         *

         * After the CPU enables paging it will add the fixmap mapping

         * to these page tables, however this may clash with the 1:1

         * mapping. So each CPU must rebuild the page tables here with

         * the 1:1 in place. */

 

        /* Write Xen's PT's paddr into the HTTBR */

        ldr   r4, =3Dboot_pgtable

        add   r4, r4, r10            /* r4= :=3D paddr (boot_pagetable) */

        mov   r5, #0            &= nbsp;    /* r4:r5 is paddr (boot_pagetable) */

        mcrr  CP64(r4, r5, HTTBR)

 

        /* Setup boot_pgtable: */

        ldr   r1, =3Dboot_second

        add   r1, r1, r10            /* r1= :=3D paddr (boot_second) */

        mov   r3, #0x0

 

        /* ... map boot_second in boot_pgtable[0] */

        orr   r2, r1, #PT_UPPER(PT)  /* r2:r3 :=3D table map of boot_second */

        orr   r2, r2, #PT_LOWER(PT)  /* (+ rights for linear PT) */<= o:p>

        strd  r2, r3, [r4, #0]       /* Map it i= n slot 0 */

 

        /* ... map of paddr(start) in boot_pgtable */

        lsrs  r1, r9, #30            /* Of= fset of base paddr in boot_pgtable */

        beq   1f            &= nbsp;        /* If it is in slot 0 then map in boot_second

         &= nbsp;           &nbs= p;            &= nbsp;   * later on */

        lsl   r2, r1, #30            /* Ba= se address for 1GB mapping */

        orr   r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */

        orr   r2, r2, #PT_LOWER(MEM)

        lsl   r1, r1, #3             = /* r1 :=3D Slot offset */

        strd  r2, r3, [r4, r1]       /* Mapping = of paddr(start) */

 

1:      /* Setup boot_second: */

        ldr   r4, =3Dboot_second

        add   r4, r4, r10            /* r1= :=3D paddr (boot_second) */

 

        lsr   r2, r9, #20            /* Ba= se address for 2MB mapping */

        lsl   r2, r2, #20

        orr   r2, r2, #PT_UPPER(MEM) /* r2:r3 :=3D section map */

        orr   r2, r2, #PT_LOWER(MEM)

 

        /* ... map of vaddr(start) in boot_second */

        ldr   r1, =3Dstart

        lsr   r1, #18            =     /* Slot for vaddr(start) */

        strd  r2, r3, [r4, r1]       /* Map vaddr(start) */

 

        /* ... map of paddr(start) in boot_second */

        lsrs  r1, r9, #30            /* Ba= se paddr */

        bne   1f            &= nbsp;        /* If paddr(start) is not in slot 0

         &= nbsp;           &nbs= p;            &= nbsp;   * then the mapping was done in

         &= nbsp;           &nbs= p;            &= nbsp;   * boot_pgtable above */

 

        mov   r1, r9, lsr #18        /= * Slot for paddr(start) */

        strd  r2, r3, [r4, r1]       /* Map Xen there */

1:

 

        /* Defer fixmap and dtb mapping until after paging enabled, to

         * avoid them clashing with the 1:1 mapping. */

 

        /* boot pagetable setup complete */

 

        PRINT("- Turning on paging -\r\n")

 

        ldr   r1, =3Dpaging           = /* Explicit vaddr, not RIP-relative */

        mrc   CP32(r0, HSCTLR)

        orr   r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */

        dsb            =             &nb= sp; /* Flush PTE writes and finish reads */

        mcr   CP32(r0, HSCTLR)       /* now paging is enabled */

        isb            =             &nb= sp; /* Now, flush the icache */

        mov   pc, r1            &= nbsp;    /* Get a proper vaddr into PC */

paging:

 

        /* Now we can install the fixmap and dtb mappings, since we

         * don't need the 1:1 map any more */

        dsb

#if defined(EARLY_PRINTK) /* Fixmap is only used by early printk */<= /span>

        /* Non-boot CPUs don't need to rebuild the fixmap itself, just

         &= nbsp;   * the mapping from boot_second to xen_fixmap */

        teq   r12, #0

        bne   1f

 

        /* Add UART to the fixmap table */

        ldr   r1, =3Dxen_fixmap       = /* r1 :=3D vaddr (xen_fixmap) */

        mov   r3, #0

        lsr   r2, r11, #12

        lsl   r2, r2, #12            /* 4K aligned paddr of UART */

        orr   r2, r2, #PT_UPPER(DEV_L3)

        orr   r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 :=3D 4K dev map includin= g UART */

        strd  r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixmap'= s slot */

1:

 

        /* Map fixmap into boot_second */

        ldr   r1, =3Dboot_second       /* r= 1 :=3D vaddr (xen_fixmap) */

        ldr   r2, =3Dxen_fixmap

        add   r2, r2, r10            /* r2= :=3D paddr (xen_fixmap) */

        orr   r2, r2, #PT_UPPER(PT)

        orr   r2, r2, #PT_LOWER(PT)  /* r2:r3 :=3D table map of xen_= fixmap */

        ldr   r4, =3DFIXMAP_ADDR(0)

        mov   r4, r4, lsr #18        /= * r4 :=3D Slot for FIXMAP(0) */

        strd  r2, r3, [r1, r4]       /* Map it i= n the fixmap's slot */

 

        /* Use a virtual address to access the UART. */

        ldr   r11, =3DEARLY_UART_VIRTUAL_ADDRESS

#endif

        /* Map the DTB in the boot misc slot */

        teq   r12, #0            &= nbsp;   /* Only on boot CPU */

        bne   1f

 

        ldr   r1, =3Dboot_second

        mov   r3, #0x0

        lsr   r2, r8, #21

        lsl   r2, r2, #21            /* r2= : 2MB-aligned paddr of DTB */

        orr   r2, r2, #PT_UPPER(MEM)

        orr   r2, r2, #PT_LOWER(MEM) /* r2:r3 :=3D 2MB RAM incl. DTB */

        ldr   r4, =3DBOOT_FDT_VIRT_START

        mov   r4, r4, lsr #18        /= * Slot for BOOT_FDT_VIRT_START */

        strd  r2, r3, [r1, r4]       /* Map it i= n the early fdt slot */

        dsb

1:

 

 

It will be great help if anyone can throw some light o= n the function of the above piece of code.

 

Thanks & Regards

 

Shubham Khandelwal

 

--_000_3A6586556649FF42BA3240F179473FD11454A64254HIKAWSEX01adh_-- --===============8425987623100157359== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm --===============8425987623100157359==-- From xen-arm-bounces@lists.xen.org Fri Apr 04 08:50:16 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Apr 2014 08:50:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzpF-00052X-VA; Fri, 04 Apr 2014 08:50:13 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzpE-00052O-1P; Fri, 04 Apr 2014 08:50:12 +0000 Received: from [193.109.254.147:49210] by server-10.bemta-14.messagelabs.com id 0F/2A-04546-3427E335; Fri, 04 Apr 2014 08:50:11 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1396601408!6267183!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23890 invoked from network); 4 Apr 2014 08:50:10 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-4.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 4 Apr 2014 08:50:10 -0000 X-IronPort-AV: E=Sophos;i="4.97,793,1389744000"; d="scan'208";a="117940882" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 04 Apr 2014 08:50:08 +0000 Received: from [10.80.2.80] (10.80.2.80) by FTLPEX01CL02.citrite.net (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Fri, 4 Apr 2014 04:50:07 -0400 Message-ID: <1396601406.4211.161.camel@kazak.uk.xensource.com> From: Ian Campbell To: "Khandelwal, Shubham" Date: Fri, 4 Apr 2014 09:50:06 +0100 In-Reply-To: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> References: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> Organization: Citrix Systems, Inc. X-Mailer: Evolution 3.8.5-2+b3 MIME-Version: 1.0 X-Originating-IP: [10.80.2.80] X-DLP: MIA2 Cc: "Datta, Souvik" , "'xen-arm@lists.xen.org'" , xen-devel Subject: Re: [XenARM] Understanding XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org On Fri, 2014-04-04 at 10:22 +0200, Khandelwal, Shubham wrote: > It will be great help if anyone can throw some light on the function > of the above piece of code. This code is constructing an initial set of page tables for us to use when we enable paging, the structure of those PTs is, as the comment says, described in mm.c. Ian. _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm From xen-arm-bounces@lists.xen.org Fri Apr 04 08:50:16 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Apr 2014 08:50:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzpF-00052X-VA; Fri, 04 Apr 2014 08:50:13 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVzpE-00052O-1P; Fri, 04 Apr 2014 08:50:12 +0000 Received: from [193.109.254.147:49210] by server-10.bemta-14.messagelabs.com id 0F/2A-04546-3427E335; Fri, 04 Apr 2014 08:50:11 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1396601408!6267183!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23890 invoked from network); 4 Apr 2014 08:50:10 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-4.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 4 Apr 2014 08:50:10 -0000 X-IronPort-AV: E=Sophos;i="4.97,793,1389744000"; d="scan'208";a="117940882" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 04 Apr 2014 08:50:08 +0000 Received: from [10.80.2.80] (10.80.2.80) by FTLPEX01CL02.citrite.net (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Fri, 4 Apr 2014 04:50:07 -0400 Message-ID: <1396601406.4211.161.camel@kazak.uk.xensource.com> From: Ian Campbell To: "Khandelwal, Shubham" Date: Fri, 4 Apr 2014 09:50:06 +0100 In-Reply-To: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> References: <3A6586556649FF42BA3240F179473FD11454A64254@HIKAWSEX01.ad.harman.com> Organization: Citrix Systems, Inc. X-Mailer: Evolution 3.8.5-2+b3 MIME-Version: 1.0 X-Originating-IP: [10.80.2.80] X-DLP: MIA2 Cc: "Datta, Souvik" , "'xen-arm@lists.xen.org'" , xen-devel Subject: Re: [XenARM] Understanding XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org On Fri, 2014-04-04 at 10:22 +0200, Khandelwal, Shubham wrote: > It will be great help if anyone can throw some light on the function > of the above piece of code. This code is constructing an initial set of page tables for us to use when we enable paging, the structure of those PTs is, as the comment says, described in mm.c. Ian. _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm From xen-arm-bounces@lists.xen.org Tue Apr 29 11:35:29 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 29 Apr 2014 11:35:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wf6Jn-0004Uw-Be; Tue, 29 Apr 2014 11:35:23 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wf6Jm-0004Uj-Gb; Tue, 29 Apr 2014 11:35:22 +0000 Received: from [85.158.137.68:37399] by server-13.bemta-3.messagelabs.com id E2/5D-18692-97E8F535; Tue, 29 Apr 2014 11:35:21 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1398771320!770303!1 X-Originating-IP: [195.245.231.151] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTk1LjI0NS4yMzEuMTUxID0+IDU3NzI=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24039 invoked from network); 29 Apr 2014 11:35:20 -0000 Received: from mail1.bemta5.messagelabs.com (HELO mail1.bemta5.messagelabs.com) (195.245.231.151) by server-3.tower-31.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 29 Apr 2014 11:35:20 -0000 Received: from [85.158.139.19:56071] by server-15.bemta-5.messagelabs.com id CC/E0-11079-87E8F535; Tue, 29 Apr 2014 11:35:20 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-16.tower-178.messagelabs.com!1398771319!21683892!2 X-Originating-IP: [194.121.90.173] X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8414 invoked from network); 29 Apr 2014 11:35:19 -0000 Received: from unassigned (HELO HIKAWSEX03.ad.harman.com) (194.121.90.173) by server-16.tower-178.messagelabs.com with AES128-SHA encrypted SMTP; 29 Apr 2014 11:35:19 -0000 Received: from HIKAWSEX01.ad.harman.com ([fe80::f023:31d4:f809:b22e]) by HIKAWSEX03.ad.harman.com ([172.16.1.217]) with mapi; Tue, 29 Apr 2014 13:35:00 +0200 From: "Khandelwal, Shubham" To: "'xen-arm@lists.xen.org'" , xen-devel , "xen-devel@lists.xensource.com" Date: Tue, 29 Apr 2014 13:35:00 +0200 Thread-Topic: Device pass through on XEN on ARM Thread-Index: Ac9jmCdfJo4F86aBQhuvI309+xxWGw== Message-ID: <3A6586556649FF42BA3240F179473FD11454A64270@HIKAWSEX01.ad.harman.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Subject: [XenARM] Device pass through on XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5869781872578339416==" Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org --===============5869781872578339416== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_" --_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, I would like to understand how is pass through achieved on XEN on ARM for d= evices which do not have a PCI bus controller, like for example embedded de= vices. Any pointers in this direction will be appreciated. Thanks & Regards Shubham Khandelwal --_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

 

I would like to understand how is pass through achieve= d on XEN on ARM for devices which do not have a PCI bus controller, like for exa= mple embedded devices. Any pointers in this direction will be appreciated.<= /o:p>

 

Thanks & Regards

 

Shubham Khandelwal

 

--_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_-- --===============5869781872578339416== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm --===============5869781872578339416==-- From xen-arm-bounces@lists.xen.org Tue Apr 29 11:35:29 2014 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 29 Apr 2014 11:35:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wf6Jn-0004Uw-Be; Tue, 29 Apr 2014 11:35:23 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wf6Jm-0004Uj-Gb; Tue, 29 Apr 2014 11:35:22 +0000 Received: from [85.158.137.68:37399] by server-13.bemta-3.messagelabs.com id E2/5D-18692-97E8F535; Tue, 29 Apr 2014 11:35:21 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1398771320!770303!1 X-Originating-IP: [195.245.231.151] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTk1LjI0NS4yMzEuMTUxID0+IDU3NzI=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24039 invoked from network); 29 Apr 2014 11:35:20 -0000 Received: from mail1.bemta5.messagelabs.com (HELO mail1.bemta5.messagelabs.com) (195.245.231.151) by server-3.tower-31.messagelabs.com with DHE-RSA-AES256-SHA encrypted SMTP; 29 Apr 2014 11:35:20 -0000 Received: from [85.158.139.19:56071] by server-15.bemta-5.messagelabs.com id CC/E0-11079-87E8F535; Tue, 29 Apr 2014 11:35:20 +0000 X-Env-Sender: Shubham.Khandelwal@harman.com X-Msg-Ref: server-16.tower-178.messagelabs.com!1398771319!21683892!2 X-Originating-IP: [194.121.90.173] X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8414 invoked from network); 29 Apr 2014 11:35:19 -0000 Received: from unassigned (HELO HIKAWSEX03.ad.harman.com) (194.121.90.173) by server-16.tower-178.messagelabs.com with AES128-SHA encrypted SMTP; 29 Apr 2014 11:35:19 -0000 Received: from HIKAWSEX01.ad.harman.com ([fe80::f023:31d4:f809:b22e]) by HIKAWSEX03.ad.harman.com ([172.16.1.217]) with mapi; Tue, 29 Apr 2014 13:35:00 +0200 From: "Khandelwal, Shubham" To: "'xen-arm@lists.xen.org'" , xen-devel , "xen-devel@lists.xensource.com" Date: Tue, 29 Apr 2014 13:35:00 +0200 Thread-Topic: Device pass through on XEN on ARM Thread-Index: Ac9jmCdfJo4F86aBQhuvI309+xxWGw== Message-ID: <3A6586556649FF42BA3240F179473FD11454A64270@HIKAWSEX01.ad.harman.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Subject: [XenARM] Device pass through on XEN on ARM X-BeenThere: xen-arm@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "List for Xen ARM PV developers and users \(planned to be archived\)" List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5869781872578339416==" Sender: xen-arm-bounces@lists.xen.org Errors-To: xen-arm-bounces@lists.xen.org --===============5869781872578339416== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_" --_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, I would like to understand how is pass through achieved on XEN on ARM for d= evices which do not have a PCI bus controller, like for example embedded de= vices. Any pointers in this direction will be appreciated. Thanks & Regards Shubham Khandelwal --_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hello,

 

I would like to understand how is pass through achieve= d on XEN on ARM for devices which do not have a PCI bus controller, like for exa= mple embedded devices. Any pointers in this direction will be appreciated.<= /o:p>

 

Thanks & Regards

 

Shubham Khandelwal

 

--_000_3A6586556649FF42BA3240F179473FD11454A64270HIKAWSEX01adh_-- --===============5869781872578339416== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-arm mailing list Xen-arm@lists.xen.org http://lists.xen.org/cgi-bin/mailman/listinfo/xen-arm --===============5869781872578339416==--