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From: patchbot@xen.org
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Subject: [xen staging] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1tTQb5-00E5ec-2S@xenbits.xenproject.org>
Date: Thu, 02 Jan 2025 19:11:07 +0000

commit a1746cd4434dd27ca2da8430dfb10edc76264bb3
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Mon Mar 25 15:14:46 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 2 18:44:49 2025 +0000

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 1dd8f714d3..08b0053f9c 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2456,7 +2456,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2605,6 +2605,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 78bc9872b0..060b34d913 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -625,6 +626,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 7da0423039..597b0f073d 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 9cdb5b2625..22d9e76e55 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102cU
 #define MSR_AMD64_BP_CFG		0xc001102eU
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3U
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027U
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 75a4177a75..ced8475001 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -145,6 +146,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -365,6 +367,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -507,7 +511,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -531,10 +535,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -553,7 +558,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1113,7 +1119,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1138,22 +1144,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 8fa3fb711a..16207e3817 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -325,7 +325,9 @@ XEN_CPUFEATURE(FSRSC,              11*32+19) /*A  Fast Short REP SCASB */
 XEN_CPUFEATURE(AMD_PREFETCHI,      11*32+20) /*A  PREFETCHIT{0,1} Instructions */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/scripts: Fix regex syntax warnings with Python 3.12
Message-Id: <E1tTQwN-00EAb5-2T@xenbits.xenproject.org>
Date: Thu, 02 Jan 2025 19:33:07 +0000

commit 4288576c161bf1204f2295e43cf70839a25828a8
Author:     Ariel Otilibili <Ariel.Otilibili-Anieli@eurecom.fr>
AuthorDate: Thu Dec 19 19:10:43 2024 +0100
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Thu Jan 2 11:27:57 2025 -0800

    xen/scripts: Fix regex syntax warnings with Python 3.12
    
    Same fix than commit 826a9eb072 (tools: Fix regex syntax warnings with Python 3.12).
    
    It clears out the warning:
    
    ```
    $ xen/scripts/xen-analysis.py
    xen/scripts/xen_analysis/cppcheck_analysis.py:94: SyntaxWarning: invalid escape sequence '\*'
      comment_line_starts = re.match('^[ \t]*/\*.*$', line)
    ```
    
    The  warning appears only the first time the command is run, then it disappears.
    
    Fixes: 02b26c02c7 (xen/scripts: add cppcheck tool to the xen-analysis.py script)
    Signed-off-by: Ariel Otilibili <Ariel.Otilibili-Anieli@eurecom.fr>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    --
    Cc: Andrew Cooper <andrew.cooper3@citrix.com>
    Cc: Anthony PERARD <anthony.perard@vates.tech>
    Cc: Michal Orzel <michal.orzel@amd.com>
    Cc: Jan Beulich <jbeulich@suse.com>
    Cc: Julien Grall <julien@xen.org>
    Cc: "Roger Pau Monné" <roger.pau@citrix.com>
    Cc: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/scripts/xen_analysis/cppcheck_analysis.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/scripts/xen_analysis/cppcheck_analysis.py b/xen/scripts/xen_analysis/cppcheck_analysis.py
index ce7bda91b6..532a14b0ad 100644
--- a/xen/scripts/xen_analysis/cppcheck_analysis.py
+++ b/xen/scripts/xen_analysis/cppcheck_analysis.py
@@ -91,7 +91,7 @@ def __generate_suppression_list(out_file):
                         line = header_content[tmp_line]
                         # Matches a line with just optional spaces/tabs and the
                         # start of a comment '/*'
-                        comment_line_starts = re.match('^[ \t]*/\*.*$', line)
+                        comment_line_starts = re.match(r'^[ \t]*/\*.*$', line)
                         # Matches a line with text and the end of a comment '*/'
                         comment_line_stops = re.match(r'^.*\*/$', line)
                         if (not comment_section) and comment_line_starts:
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1tTW2j-00Ek1K-1p@xenbits.xenproject.org>
Date: Fri, 03 Jan 2025 01:00:01 +0000

commit a1746cd4434dd27ca2da8430dfb10edc76264bb3
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Mon Mar 25 15:14:46 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 2 18:44:49 2025 +0000

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 1dd8f714d3..08b0053f9c 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2456,7 +2456,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2605,6 +2605,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 78bc9872b0..060b34d913 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -625,6 +626,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 7da0423039..597b0f073d 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 9cdb5b2625..22d9e76e55 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102cU
 #define MSR_AMD64_BP_CFG		0xc001102eU
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3U
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027U
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 75a4177a75..ced8475001 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -145,6 +146,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -365,6 +367,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -507,7 +511,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -531,10 +535,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -553,7 +558,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1113,7 +1119,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1138,22 +1144,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 8fa3fb711a..16207e3817 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -325,7 +325,9 @@ XEN_CPUFEATURE(FSRSC,              11*32+19) /*A  Fast Short REP SCASB */
 XEN_CPUFEATURE(AMD_PREFETCHI,      11*32+20) /*A  PREFETCHIT{0,1} Instructions */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/scripts: Fix regex syntax warnings with Python 3.12
Message-Id: <E1tTnFB-00GdUb-1N@xenbits.xenproject.org>
Date: Fri, 03 Jan 2025 19:22:01 +0000

commit 4288576c161bf1204f2295e43cf70839a25828a8
Author:     Ariel Otilibili <Ariel.Otilibili-Anieli@eurecom.fr>
AuthorDate: Thu Dec 19 19:10:43 2024 +0100
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Thu Jan 2 11:27:57 2025 -0800

    xen/scripts: Fix regex syntax warnings with Python 3.12
    
    Same fix than commit 826a9eb072 (tools: Fix regex syntax warnings with Python 3.12).
    
    It clears out the warning:
    
    ```
    $ xen/scripts/xen-analysis.py
    xen/scripts/xen_analysis/cppcheck_analysis.py:94: SyntaxWarning: invalid escape sequence '\*'
      comment_line_starts = re.match('^[ \t]*/\*.*$', line)
    ```
    
    The  warning appears only the first time the command is run, then it disappears.
    
    Fixes: 02b26c02c7 (xen/scripts: add cppcheck tool to the xen-analysis.py script)
    Signed-off-by: Ariel Otilibili <Ariel.Otilibili-Anieli@eurecom.fr>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    --
    Cc: Andrew Cooper <andrew.cooper3@citrix.com>
    Cc: Anthony PERARD <anthony.perard@vates.tech>
    Cc: Michal Orzel <michal.orzel@amd.com>
    Cc: Jan Beulich <jbeulich@suse.com>
    Cc: Julien Grall <julien@xen.org>
    Cc: "Roger Pau Monné" <roger.pau@citrix.com>
    Cc: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/scripts/xen_analysis/cppcheck_analysis.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/scripts/xen_analysis/cppcheck_analysis.py b/xen/scripts/xen_analysis/cppcheck_analysis.py
index ce7bda91b6..532a14b0ad 100644
--- a/xen/scripts/xen_analysis/cppcheck_analysis.py
+++ b/xen/scripts/xen_analysis/cppcheck_analysis.py
@@ -91,7 +91,7 @@ def __generate_suppression_list(out_file):
                         line = header_content[tmp_line]
                         # Matches a line with just optional spaces/tabs and the
                         # start of a comment '/*'
-                        comment_line_starts = re.match('^[ \t]*/\*.*$', line)
+                        comment_line_starts = re.match(r'^[ \t]*/\*.*$', line)
                         # Matches a line with text and the end of a comment '*/'
                         comment_line_stops = re.match(r'^.*\*/$', line)
                         if (not comment_section) and comment_line_starts:
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] eclair-analysis: tidy toolchain.ecl configuration and mark Rule 1.1 clean
Message-Id: <E1tTqE7-00H9e5-1a@xenbits.xenproject.org>
Date: Fri, 03 Jan 2025 22:33:07 +0000

commit 7e6edeaee38c66266a941bfa66d17eeeeb492fbe
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Sun Dec 22 15:04:08 2024 +0100
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Fri Jan 3 14:20:49 2025 -0800

    eclair-analysis: tidy toolchain.ecl configuration and mark Rule 1.1 clean
    
    Reformat the list of GNU extensions and non-standard tokens used by Xen
    in the ECLAIR configuration to make it easier to review any changes to it.
    
    The extension "ext_missing_varargs_arg", which captures the GNU extension that
    allows variadic functions and macros not to require at least one named parameter
    before C23 has been renamed to "ext_c_missing_varargs_arg" in the current version
    of ECLAIR used in CI, therefore this resolves regressions on MISRA C Rule 1.1:
    
    "The program shall contain no violations of the standard C syntax and constraints,
    and shall not exceed the implementation's translation limits."
    
    As a result, Rule 1.1 now has no violations and is tagged as such.
    
    Remove two unused configurations, that were already commented out.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Fixes: 631f535a3d4f ("xen: update ECLAIR service identifiers from MC3R1 to MC3A2.")
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/eclair_analysis/ECLAIR/tagging.ecl   |  1 +
 automation/eclair_analysis/ECLAIR/toolchain.ecl | 93 +++++++++++++++++++------
 2 files changed, 74 insertions(+), 20 deletions(-)

diff --git a/automation/eclair_analysis/ECLAIR/tagging.ecl b/automation/eclair_analysis/ECLAIR/tagging.ecl
index 982f506cc7..4a1d3b3a98 100644
--- a/automation/eclair_analysis/ECLAIR/tagging.ecl
+++ b/automation/eclair_analysis/ECLAIR/tagging.ecl
@@ -25,6 +25,7 @@ MC3A2.D2.1||
 MC3A2.D4.1||
 MC3A2.D4.11||
 MC3A2.D4.14||
+MC3A2.R1.1||
 MC3A2.R1.3||
 MC3A2.R1.4||
 MC3A2.R2.6||
diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl b/automation/eclair_analysis/ECLAIR/toolchain.ecl
index 86e9a79b52..8ebf9f132c 100644
--- a/automation/eclair_analysis/ECLAIR/toolchain.ecl
+++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl
@@ -12,25 +12,47 @@
 -setq=C99_STD,"ISO/IEC 9899:1999"
 
 -doc_begin="
-    _Static_assert: see Section \"2.1 C Language\" of "GCC_MANUAL".
-    asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
-    __volatile__: see Sections \"6.48 Alternate Keywords\" and \"6.47.2.1 Volatile\" of "GCC_MANUAL".
-    __const__ : see Section \"6.48 Alternate Keywords\" of "GCC_MANUAL".
-    typeof, __typeof__: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
     __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" and \"6.44 Determining the Alignment of Functions, Types or Variables\" of "GCC_MANUAL".
+    asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
     __attribute__: see Section \"6.39 Attribute Syntax\" of "GCC_MANUAL".
+    __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_MANUAL".
     __builtin_types_compatible_p: see Section \"6.59 Other Built-in Functions Provided by GCC\" of "GCC_MANUAL".
     __builtin_va_arg: non-documented GCC extension.
-    __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_MANUAL".
+    __const__, __inline__, __inline: see Section \"6.48 Alternate Keywords\" of "GCC_MANUAL".
+    _Static_assert: see Section \"2.1 C Language\" of "GCC_MANUAL".
+    typeof, __typeof__: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
+    __volatile__: see Sections \"6.48 Alternate Keywords\" and \"6.47.2.1 Volatile\" of "GCC_MANUAL".
 "
--config=STD.tokenext,behavior+={c99, GCC_ARM64, "^(_Static_assert|asm|__asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__attribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof)$"}
--config=STD.tokenext,behavior+={c99, GCC_X86_64, "^(_Static_assert|asm|__asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__alignof|__attribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof)$"}
+-name_selector+={alignof, "^(__alignof__|__alignof)$"}
+-name_selector+={asm, "^(__asm__|asm)$"}
+-name_selector+={attribute, "^__attribute__$"}
+-name_selector+={builtin_offsetof, "^__builtin_offsetof$"}
+-name_selector+={builtin_types_p, "^__builtin_types_compatible_p$"}
+-name_selector+={builtin_va_arg, "^__builtin_va_arg$"}
+-name_selector+={const, "^__const__$"}
+-name_selector+={inline, "^(__inline__|__inline)$"}
+-name_selector+={static_assert, "^_Static_assert$"}
+-name_selector+={typeof, "^(__typeof__|typeof)$"}
+-name_selector+={volatile, "^__volatile__$"}
+
+-config=STD.tokenext,behavior+={c99, GCC_ARM64||GCC_X86_64,
+"alignof||
+asm||
+attribute||
+builtin_offsetof||
+builtin_types_p||
+builtin_va_arg||
+const||
+inline||
+static_assert||
+typeof||
+volatile"
+}
 -doc_end
 
 -doc_begin="Non-documented GCC extension."
 -config=STD.emptinit,behavior+={c99,GCC_ARM64,specified}
 -config=STD.emptinit,behavior+={c99,GCC_X86_64,specified}
-#-config=STD.emptinit,behavior+={c18,GCC_X86_64,specified}
 -doc_end
 
 -doc_begin="See Section \"6.24 Arithmetic on void- and Function-Pointers\" of "GCC_MANUAL"."
@@ -80,7 +102,6 @@
 -doc_begin="Non-documented GCC extension."
 -config=STD.pteincmp,behavior+={c99,GCC_ARM64,specified}
 -config=STD.pteincmp,behavior+={c99,GCC_X86_64,specified}
-#-config=STD.pteincmp,behavior+={c18,GCC_X86_64,specified}
 -doc_end
 
 -doc_begin="Non-documented GCC extension."
@@ -88,20 +109,52 @@
 -doc_end
 
 -doc_begin="
-    ext_paste_comma: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
-    ext_missing_varargs_arg: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_c_missing_varargs_arg: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_enum_value_not_int: non-documented GCC extension.
+    ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
+    ext_flexible_array_in_struct: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
+    ext_forward_ref_enum_def: see Section \"6.49 Incomplete enum Types\" of "GCC_MANUAL".
+    ext_gnu_array_range: see Section \"6.29 Designated Initializers\" of "GCC_MANUAL".
+    ext_gnu_statement_expr_macro: see Section \"6.1 Statements and Declarations in Expressions\" of "GCC_MANUAL".
     ext_named_variadic_macro: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_paste_comma: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
     ext_return_has_void_expr: see the documentation for -Wreturn-type in Section \"3.8 Options to Request or Suppress Warnings\" of "GCC_MANUAL".
-    ext_gnu_statement_expr_macro: see Section \"6.1 Statements and Declarations in Expressions\" of "GCC_MANUAL".
     ext_sizeof_alignof_void_type: see Section \"6.24 Arithmetic on void- and Function-Pointers\" of "GCC_MANUAL".
-    ext_forward_ref_enum_def: see Section \"6.49 Incomplete enum Types\" of "GCC_MANUAL".
-    ext_flexible_array_in_struct: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
-    ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
-    ext_enum_value_not_int: non-documented GCC extension.
-    ext_gnu_array_range: see Section \"6.29 Designated Initializers\" of "GCC_MANUAL".
 "
--config=STD.diag,behavior+={c99,GCC_ARM64,"^(ext_paste_comma|ext_missing_varargs_arg|ext_named_variadic_macro|ext_return_has_void_expr|ext_gnu_statement_expr_macro|ext_sizeof_alignof_void_type|ext_forward_ref_enum_def|ext_gnu_array_range)$"}
--config=STD.diag,behavior+={c99,GCC_X86_64,"^(ext_paste_comma|ext_missing_varargs_arg|ext_named_variadic_macro|ext_return_has_void_expr|ext_gnu_statement_expr_macro|ext_sizeof_alignof_void_type|ext_flexible_array_in_struct|ext_flexible_array_in_array|ext_enum_value_not_int|ext_gnu_array_range)$"}
+-name_selector+={ext_c_missing_varargs_arg, "^ext_c_missing_varargs_arg$"}
+-name_selector+={ext_enum_value_not_int, "^ext_enum_value_not_int$"}
+-name_selector+={ext_flexible_array_in_array, "^ext_flexible_array_in_array$"}
+-name_selector+={ext_flexible_array_in_struct, "^ext_flexible_array_in_struct$"}
+-name_selector+={ext_forward_ref_enum_def, "^ext_forward_ref_enum_def$"}
+-name_selector+={ext_gnu_array_range, "^ext_gnu_array_range$"}
+-name_selector+={ext_gnu_statement_expr_macro, "^ext_gnu_statement_expr_macro$"}
+-name_selector+={ext_named_variadic_macro, "^ext_named_variadic_macro$"}
+-name_selector+={ext_paste_comma, "^ext_paste_comma$"}
+-name_selector+={ext_return_has_void_expr, "^ext_return_has_void_expr$"}
+-name_selector+={ext_sizeof_alignof_void_type, "^ext_sizeof_alignof_void_type$"}
+
+-config=STD.diag,behavior+={c99,GCC_ARM64,
+"ext_c_missing_varargs_arg||
+ext_forward_ref_enum_def||
+ext_gnu_array_range||
+ext_gnu_statement_expr_macro||
+ext_named_variadic_macro||
+ext_paste_comma||
+ext_return_has_void_expr||
+ext_sizeof_alignof_void_type"
+}
+-config=STD.diag,behavior+={c99,GCC_X86_64,
+"ext_c_missing_varargs_arg||
+ext_enum_value_not_int||
+ext_flexible_array_in_array||
+ext_flexible_array_in_struct||
+ext_gnu_array_range||
+ext_gnu_statement_expr_macro||
+ext_named_variadic_macro||
+ext_paste_comma||
+ext_return_has_void_expr||
+ext_sizeof_alignof_void_type"
+}
 -doc_end
 
 -doc_begin="The maximum size of an object is defined in the MAX_SIZE macro, and for a 32 bit architecture is 8MB.
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] eclair-analysis: tidy toolchain.ecl configuration and mark Rule 1.1 clean
Message-Id: <E1tTrA6-00HKSb-0H@xenbits.xenproject.org>
Date: Fri, 03 Jan 2025 23:33:02 +0000

commit 7e6edeaee38c66266a941bfa66d17eeeeb492fbe
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Sun Dec 22 15:04:08 2024 +0100
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Fri Jan 3 14:20:49 2025 -0800

    eclair-analysis: tidy toolchain.ecl configuration and mark Rule 1.1 clean
    
    Reformat the list of GNU extensions and non-standard tokens used by Xen
    in the ECLAIR configuration to make it easier to review any changes to it.
    
    The extension "ext_missing_varargs_arg", which captures the GNU extension that
    allows variadic functions and macros not to require at least one named parameter
    before C23 has been renamed to "ext_c_missing_varargs_arg" in the current version
    of ECLAIR used in CI, therefore this resolves regressions on MISRA C Rule 1.1:
    
    "The program shall contain no violations of the standard C syntax and constraints,
    and shall not exceed the implementation's translation limits."
    
    As a result, Rule 1.1 now has no violations and is tagged as such.
    
    Remove two unused configurations, that were already commented out.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Fixes: 631f535a3d4f ("xen: update ECLAIR service identifiers from MC3R1 to MC3A2.")
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/eclair_analysis/ECLAIR/tagging.ecl   |  1 +
 automation/eclair_analysis/ECLAIR/toolchain.ecl | 93 +++++++++++++++++++------
 2 files changed, 74 insertions(+), 20 deletions(-)

diff --git a/automation/eclair_analysis/ECLAIR/tagging.ecl b/automation/eclair_analysis/ECLAIR/tagging.ecl
index 982f506cc7..4a1d3b3a98 100644
--- a/automation/eclair_analysis/ECLAIR/tagging.ecl
+++ b/automation/eclair_analysis/ECLAIR/tagging.ecl
@@ -25,6 +25,7 @@ MC3A2.D2.1||
 MC3A2.D4.1||
 MC3A2.D4.11||
 MC3A2.D4.14||
+MC3A2.R1.1||
 MC3A2.R1.3||
 MC3A2.R1.4||
 MC3A2.R2.6||
diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl b/automation/eclair_analysis/ECLAIR/toolchain.ecl
index 86e9a79b52..8ebf9f132c 100644
--- a/automation/eclair_analysis/ECLAIR/toolchain.ecl
+++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl
@@ -12,25 +12,47 @@
 -setq=C99_STD,"ISO/IEC 9899:1999"
 
 -doc_begin="
-    _Static_assert: see Section \"2.1 C Language\" of "GCC_MANUAL".
-    asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
-    __volatile__: see Sections \"6.48 Alternate Keywords\" and \"6.47.2.1 Volatile\" of "GCC_MANUAL".
-    __const__ : see Section \"6.48 Alternate Keywords\" of "GCC_MANUAL".
-    typeof, __typeof__: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
     __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" and \"6.44 Determining the Alignment of Functions, Types or Variables\" of "GCC_MANUAL".
+    asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
     __attribute__: see Section \"6.39 Attribute Syntax\" of "GCC_MANUAL".
+    __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_MANUAL".
     __builtin_types_compatible_p: see Section \"6.59 Other Built-in Functions Provided by GCC\" of "GCC_MANUAL".
     __builtin_va_arg: non-documented GCC extension.
-    __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_MANUAL".
+    __const__, __inline__, __inline: see Section \"6.48 Alternate Keywords\" of "GCC_MANUAL".
+    _Static_assert: see Section \"2.1 C Language\" of "GCC_MANUAL".
+    typeof, __typeof__: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
+    __volatile__: see Sections \"6.48 Alternate Keywords\" and \"6.47.2.1 Volatile\" of "GCC_MANUAL".
 "
--config=STD.tokenext,behavior+={c99, GCC_ARM64, "^(_Static_assert|asm|__asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__attribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof)$"}
--config=STD.tokenext,behavior+={c99, GCC_X86_64, "^(_Static_assert|asm|__asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__alignof|__attribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof)$"}
+-name_selector+={alignof, "^(__alignof__|__alignof)$"}
+-name_selector+={asm, "^(__asm__|asm)$"}
+-name_selector+={attribute, "^__attribute__$"}
+-name_selector+={builtin_offsetof, "^__builtin_offsetof$"}
+-name_selector+={builtin_types_p, "^__builtin_types_compatible_p$"}
+-name_selector+={builtin_va_arg, "^__builtin_va_arg$"}
+-name_selector+={const, "^__const__$"}
+-name_selector+={inline, "^(__inline__|__inline)$"}
+-name_selector+={static_assert, "^_Static_assert$"}
+-name_selector+={typeof, "^(__typeof__|typeof)$"}
+-name_selector+={volatile, "^__volatile__$"}
+
+-config=STD.tokenext,behavior+={c99, GCC_ARM64||GCC_X86_64,
+"alignof||
+asm||
+attribute||
+builtin_offsetof||
+builtin_types_p||
+builtin_va_arg||
+const||
+inline||
+static_assert||
+typeof||
+volatile"
+}
 -doc_end
 
 -doc_begin="Non-documented GCC extension."
 -config=STD.emptinit,behavior+={c99,GCC_ARM64,specified}
 -config=STD.emptinit,behavior+={c99,GCC_X86_64,specified}
-#-config=STD.emptinit,behavior+={c18,GCC_X86_64,specified}
 -doc_end
 
 -doc_begin="See Section \"6.24 Arithmetic on void- and Function-Pointers\" of "GCC_MANUAL"."
@@ -80,7 +102,6 @@
 -doc_begin="Non-documented GCC extension."
 -config=STD.pteincmp,behavior+={c99,GCC_ARM64,specified}
 -config=STD.pteincmp,behavior+={c99,GCC_X86_64,specified}
-#-config=STD.pteincmp,behavior+={c18,GCC_X86_64,specified}
 -doc_end
 
 -doc_begin="Non-documented GCC extension."
@@ -88,20 +109,52 @@
 -doc_end
 
 -doc_begin="
-    ext_paste_comma: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
-    ext_missing_varargs_arg: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_c_missing_varargs_arg: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_enum_value_not_int: non-documented GCC extension.
+    ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
+    ext_flexible_array_in_struct: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
+    ext_forward_ref_enum_def: see Section \"6.49 Incomplete enum Types\" of "GCC_MANUAL".
+    ext_gnu_array_range: see Section \"6.29 Designated Initializers\" of "GCC_MANUAL".
+    ext_gnu_statement_expr_macro: see Section \"6.1 Statements and Declarations in Expressions\" of "GCC_MANUAL".
     ext_named_variadic_macro: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
+    ext_paste_comma: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
     ext_return_has_void_expr: see the documentation for -Wreturn-type in Section \"3.8 Options to Request or Suppress Warnings\" of "GCC_MANUAL".
-    ext_gnu_statement_expr_macro: see Section \"6.1 Statements and Declarations in Expressions\" of "GCC_MANUAL".
     ext_sizeof_alignof_void_type: see Section \"6.24 Arithmetic on void- and Function-Pointers\" of "GCC_MANUAL".
-    ext_forward_ref_enum_def: see Section \"6.49 Incomplete enum Types\" of "GCC_MANUAL".
-    ext_flexible_array_in_struct: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
-    ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
-    ext_enum_value_not_int: non-documented GCC extension.
-    ext_gnu_array_range: see Section \"6.29 Designated Initializers\" of "GCC_MANUAL".
 "
--config=STD.diag,behavior+={c99,GCC_ARM64,"^(ext_paste_comma|ext_missing_varargs_arg|ext_named_variadic_macro|ext_return_has_void_expr|ext_gnu_statement_expr_macro|ext_sizeof_alignof_void_type|ext_forward_ref_enum_def|ext_gnu_array_range)$"}
--config=STD.diag,behavior+={c99,GCC_X86_64,"^(ext_paste_comma|ext_missing_varargs_arg|ext_named_variadic_macro|ext_return_has_void_expr|ext_gnu_statement_expr_macro|ext_sizeof_alignof_void_type|ext_flexible_array_in_struct|ext_flexible_array_in_array|ext_enum_value_not_int|ext_gnu_array_range)$"}
+-name_selector+={ext_c_missing_varargs_arg, "^ext_c_missing_varargs_arg$"}
+-name_selector+={ext_enum_value_not_int, "^ext_enum_value_not_int$"}
+-name_selector+={ext_flexible_array_in_array, "^ext_flexible_array_in_array$"}
+-name_selector+={ext_flexible_array_in_struct, "^ext_flexible_array_in_struct$"}
+-name_selector+={ext_forward_ref_enum_def, "^ext_forward_ref_enum_def$"}
+-name_selector+={ext_gnu_array_range, "^ext_gnu_array_range$"}
+-name_selector+={ext_gnu_statement_expr_macro, "^ext_gnu_statement_expr_macro$"}
+-name_selector+={ext_named_variadic_macro, "^ext_named_variadic_macro$"}
+-name_selector+={ext_paste_comma, "^ext_paste_comma$"}
+-name_selector+={ext_return_has_void_expr, "^ext_return_has_void_expr$"}
+-name_selector+={ext_sizeof_alignof_void_type, "^ext_sizeof_alignof_void_type$"}
+
+-config=STD.diag,behavior+={c99,GCC_ARM64,
+"ext_c_missing_varargs_arg||
+ext_forward_ref_enum_def||
+ext_gnu_array_range||
+ext_gnu_statement_expr_macro||
+ext_named_variadic_macro||
+ext_paste_comma||
+ext_return_has_void_expr||
+ext_sizeof_alignof_void_type"
+}
+-config=STD.diag,behavior+={c99,GCC_X86_64,
+"ext_c_missing_varargs_arg||
+ext_enum_value_not_int||
+ext_flexible_array_in_array||
+ext_flexible_array_in_struct||
+ext_gnu_array_range||
+ext_gnu_statement_expr_macro||
+ext_named_variadic_macro||
+ext_paste_comma||
+ext_return_has_void_expr||
+ext_sizeof_alignof_void_type"
+}
 -doc_end
 
 -doc_begin="The maximum size of an object is defined in the MAX_SIZE macro, and for a 32 bit architecture is 8MB.
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1tUnEB-00GGvo-2N@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 13:33:07 +0000

commit 555866cb56002849014a1409ecdfa3f436c0c2c4
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Dec 31 14:06:19 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 12:24:05 2025 +0000

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index fd8a4448e3..87b30ce4df 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -114,7 +114,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2092,56 +2092,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2201,6 +2155,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2226,6 +2216,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/pv: Fix build with Clang and CONFIG_PERF_COUNTERS
Message-Id: <E1tUnEL-00GGwT-2q@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 13:33:17 +0000

commit 0009feff8b54b55b4dfdea0c26b2c6ba9ecdf2ba
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 2 19:46:19 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 12:26:42 2025 +0000

    x86/pv: Fix build with Clang and CONFIG_PERF_COUNTERS
    
    Clang, of at least verion 17 complains:
    
      arch/x86/pv/hypercall.c:30:10: error: variable 'eax' is used uninitialized
      whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
         30 |     if ( !compat )
            |          ^~~~~~~
      arch/x86/pv/hypercall.c:87:29: note: uninitialized use occurs here
         87 |     perfc_incra(hypercalls, eax);
            |                             ^~~
    
    This function is forced always_inline to cause compat to be
    constant-propagated through, but that is only a heuristic to try and get the
    compiler to do what we want, not a gurantee that it does.
    
    Clang doesn't appear to be able to see that the only case where compat is
    true (and therefore the if() is false) is when there's an else clause on the
    end which sets eax too.
    
    Initialise eax to -1, which ought to be optimised out, but if for whatever
    reason it happens not to be, then perfc_incra() will fail it's bounds check
    and do nothing.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/pv/hypercall.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/pv/hypercall.c b/xen/arch/x86/pv/hypercall.c
index 2febade44b..17581d232e 100644
--- a/xen/arch/x86/pv/hypercall.c
+++ b/xen/arch/x86/pv/hypercall.c
@@ -21,7 +21,7 @@ static void always_inline
 _pv_hypercall(struct cpu_user_regs *regs, bool compat)
 {
     struct vcpu *curr = current;
-    unsigned long eax;
+    unsigned long eax = -1; /* Clang -Wsometimes-uninitialized */
 
     ASSERT(guest_kernel_mode(curr, regs));
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1tUnzW-00GN0M-00@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 14:22:02 +0000

commit 555866cb56002849014a1409ecdfa3f436c0c2c4
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Dec 31 14:06:19 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 12:24:05 2025 +0000

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index fd8a4448e3..87b30ce4df 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -114,7 +114,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2092,56 +2092,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2201,6 +2155,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2226,6 +2216,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/pv: Fix build with Clang and CONFIG_PERF_COUNTERS
Message-Id: <E1tUnzg-00GN16-0P@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 14:22:12 +0000

commit 0009feff8b54b55b4dfdea0c26b2c6ba9ecdf2ba
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 2 19:46:19 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 12:26:42 2025 +0000

    x86/pv: Fix build with Clang and CONFIG_PERF_COUNTERS
    
    Clang, of at least verion 17 complains:
    
      arch/x86/pv/hypercall.c:30:10: error: variable 'eax' is used uninitialized
      whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
         30 |     if ( !compat )
            |          ^~~~~~~
      arch/x86/pv/hypercall.c:87:29: note: uninitialized use occurs here
         87 |     perfc_incra(hypercalls, eax);
            |                             ^~~
    
    This function is forced always_inline to cause compat to be
    constant-propagated through, but that is only a heuristic to try and get the
    compiler to do what we want, not a gurantee that it does.
    
    Clang doesn't appear to be able to see that the only case where compat is
    true (and therefore the if() is false) is when there's an else clause on the
    end which sets eax too.
    
    Initialise eax to -1, which ought to be optimised out, but if for whatever
    reason it happens not to be, then perfc_incra() will fail it's bounds check
    and do nothing.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/pv/hypercall.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/pv/hypercall.c b/xen/arch/x86/pv/hypercall.c
index 2febade44b..17581d232e 100644
--- a/xen/arch/x86/pv/hypercall.c
+++ b/xen/arch/x86/pv/hypercall.c
@@ -21,7 +21,7 @@ static void always_inline
 _pv_hypercall(struct cpu_user_regs *regs, bool compat)
 {
     struct vcpu *curr = current;
-    unsigned long eax;
+    unsigned long eax = -1; /* Clang -Wsometimes-uninitialized */
 
     ASSERT(guest_kernel_mode(curr, regs));
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1tUrjr-00Gmod-3B@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 18:22:07 +0000

commit f29cc14de1d195bcd8312dcab2b5f8e634b57288
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Dec 31 14:15:22 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 18:01:32 2025 +0000

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 876317fad0..420198406d 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1417,6 +1417,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index ba7668a946..210736f580 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index a082450e92..a6117dfebf 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -568,6 +568,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1tUsVB-00GsF1-1e@xenbits.xenproject.org>
Date: Mon, 06 Jan 2025 19:11:01 +0000

commit f29cc14de1d195bcd8312dcab2b5f8e634b57288
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Dec 31 14:15:22 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 6 18:01:32 2025 +0000

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 876317fad0..420198406d 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1417,6 +1417,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index ba7668a946..210736f580 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index a082450e92..a6117dfebf 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -568,6 +568,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/perfc: Drop arch_perfc_{gather,reset}()
Message-Id: <E1tV8QN-003tF5-2G@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 12:11:07 +0000

commit 8900010501121411160562f2086d98831b392c99
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:31:32 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Drop arch_perfc_{gather,reset}()
    
    These were only ever used by the IA64 port, which was droped in commit
    570c311ca2c7 ("remove ia64") in 2012.
    
    Remove them, and clean up the arm/x86 stub headers.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/include/asm/perfc.h | 21 ---------------------
 xen/arch/x86/include/asm/perfc.h | 12 ------------
 xen/common/perfc.c               |  6 ------
 3 files changed, 39 deletions(-)

diff --git a/xen/arch/arm/include/asm/perfc.h b/xen/arch/arm/include/asm/perfc.h
deleted file mode 100644
index 95c4b2b6b7..0000000000
--- a/xen/arch/arm/include/asm/perfc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_PERFC_H__
-#define __ASM_PERFC_H__
-
-static inline void arch_perfc_reset(void)
-{
-}
-
-static inline void arch_perfc_gather(void)
-{
-}
-
-#endif
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
diff --git a/xen/arch/x86/include/asm/perfc.h b/xen/arch/x86/include/asm/perfc.h
deleted file mode 100644
index a1a591e803..0000000000
--- a/xen/arch/x86/include/asm/perfc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ASM_PERFC_H__
-#define __ASM_PERFC_H__
-
-static inline void arch_perfc_reset(void)
-{
-}
-
-static inline void arch_perfc_gather(void)
-{
-}
-
-#endif
diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index 80480aa776..ed4dba36f1 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -8,7 +8,6 @@
 #include <xen/mm.h>
 #include <xen/guest_access.h>
 #include <public/sysctl.h>
-#include <asm/perfc.h>
 
 #define PERFCOUNTER( var, name )              { name, TYPE_SINGLE, 0 },
 #define PERFCOUNTER_ARRAY( var, name, size )  { name, TYPE_ARRAY,  size },
@@ -148,8 +147,6 @@ void cf_check perfc_reset(unsigned char key)
             break;
         }
     }
-
-    arch_perfc_reset();
 }
 
 static struct xen_sysctl_perfc_desc perfc_d[NR_PERFCTRS];
@@ -199,9 +196,6 @@ static int perfc_copy_info(XEN_GUEST_HANDLE_64(xen_sysctl_perfc_desc_t) desc,
     if ( perfc_vals == NULL )
         return -ENOMEM;
 
-    /* Architecture may fill counters from hardware.  */
-    arch_perfc_gather();
-
     /* We gather the counts together every time. */
     for ( i = j = v = 0; i < NR_PERFCTRS; i++ )
     {
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/perfc: Add perfc_defn.h to asm-generic
Message-Id: <E1tV8QX-003tGW-2t@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 12:11:17 +0000

commit 02c24a1325d37bdf089b980b5618b2b0616260a7
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:18:22 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Add perfc_defn.h to asm-generic
    
    ... and hook it up for RISC-V and PPC.
    
    On RISC-V at least, no combination of headers pulls in errno.h, so include it
    explicitly.
    
    Guard the hypercalls array declaration based on NR_hypercalls existing.  This
    is sufficient to get PERF_COUNTERS fully working on RISC-V and PPC, so drop
    the randconfig override.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Oleksii Kurohcko <oleksii.kurochko@gmail.com>
---
 automation/gitlab-ci/build.yaml         | 1 -
 xen/arch/ppc/include/asm/Makefile       | 1 +
 xen/arch/riscv/configs/tiny64_defconfig | 1 -
 xen/arch/riscv/include/asm/Makefile     | 1 +
 xen/common/perfc.c                      | 1 +
 xen/include/asm-generic/perfc_defn.h    | 5 +++++
 xen/include/xen/perfc_defn.h            | 2 ++
 7 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 1b884cc81c..41f17ed456 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -734,7 +734,6 @@ debian-12-riscv64-gcc:
       CONFIG_GRANT_TABLE=n
       CONFIG_LIVEPATCH=n
       CONFIG_MEM_ACCESS=n
-      CONFIG_PERF_COUNTERS=n
       CONFIG_QEMU_PLATFORM=y
       CONFIG_XSM=n
 
diff --git a/xen/arch/ppc/include/asm/Makefile b/xen/arch/ppc/include/asm/Makefile
index ced02e26ed..c989a7f89b 100644
--- a/xen/arch/ppc/include/asm/Makefile
+++ b/xen/arch/ppc/include/asm/Makefile
@@ -7,6 +7,7 @@ generic-y += hypercall.h
 generic-y += iocap.h
 generic-y += paging.h
 generic-y += percpu.h
+generic-y += perfc_defn.h
 generic-y += random.h
 generic-y += softirq.h
 generic-y += vm_event.h
diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig
index 6af563bd73..bb3ae26a44 100644
--- a/xen/arch/riscv/configs/tiny64_defconfig
+++ b/xen/arch/riscv/configs/tiny64_defconfig
@@ -1,7 +1,6 @@
 # CONFIG_BOOT_TIME_CPUPOOLS is not set
 # CONFIG_GRANT_TABLE is not set
 # CONFIG_MEM_ACCESS is not set
-# CONFIG_PERF_COUNTERS is not set
 # CONFIG_COVERAGE is not set
 # CONFIG_LIVEPATCH is not set
 # CONFIG_XSM is not set
diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile
index ced02e26ed..c989a7f89b 100644
--- a/xen/arch/riscv/include/asm/Makefile
+++ b/xen/arch/riscv/include/asm/Makefile
@@ -7,6 +7,7 @@ generic-y += hypercall.h
 generic-y += iocap.h
 generic-y += paging.h
 generic-y += percpu.h
+generic-y += perfc_defn.h
 generic-y += random.h
 generic-y += softirq.h
 generic-y += vm_event.h
diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index ed4dba36f1..8c967ab900 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -1,4 +1,5 @@
 
+#include <xen/errno.h>
 #include <xen/lib.h>
 #include <xen/smp.h>
 #include <xen/time.h>
diff --git a/xen/include/asm-generic/perfc_defn.h b/xen/include/asm-generic/perfc_defn.h
new file mode 100644
index 0000000000..8237636d83
--- /dev/null
+++ b/xen/include/asm-generic/perfc_defn.h
@@ -0,0 +1,5 @@
+/* This file is legitimately included multiple times. */
+/* #ifndef ASM_GENERIC_PERFC_DEFN_H */
+/* #define ASM_GENERIC_PERFC_DEFN_H */
+
+/* #endif ASM_GENERIC_PERFC_DEFN_H */
diff --git a/xen/include/xen/perfc_defn.h b/xen/include/xen/perfc_defn.h
index 0027d95a60..a987d80dd6 100644
--- a/xen/include/xen/perfc_defn.h
+++ b/xen/include/xen/perfc_defn.h
@@ -4,7 +4,9 @@
 
 #include <asm/perfc_defn.h>
 
+#ifdef NR_hypercalls
 PERFCOUNTER_ARRAY(hypercalls,           "hypercalls", NR_hypercalls)
+#endif
 
 PERFCOUNTER(calls_from_multicall,       "calls from multicall")
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/perfc: Trim includes
Message-Id: <E1tV8Qi-003tHx-09@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 12:11:28 +0000

commit e7ea1de7746c94f0e5349ab7bb3d236c5475eb4d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:01:34 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Trim includes
    
    This is mostly for the removal of xen/lib.h and xen/smp.h from perfc.h.  All
    that is needed is xen/macros.h.
    
    Trim and sort the includes for perfc.c too.  There's no need for smp.h,
    keyhandler.h or mm.h, but cpumask.h is needed.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/common/perfc.c      | 9 ++++-----
 xen/include/xen/perfc.h | 3 +--
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index 8c967ab900..b748c8af85 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -1,13 +1,12 @@
 
+#include <xen/cpumask.h>
 #include <xen/errno.h>
+#include <xen/guest_access.h>
 #include <xen/lib.h>
-#include <xen/smp.h>
-#include <xen/time.h>
 #include <xen/perfc.h>
-#include <xen/keyhandler.h> 
 #include <xen/spinlock.h>
-#include <xen/mm.h>
-#include <xen/guest_access.h>
+#include <xen/time.h>
+
 #include <public/sysctl.h>
 
 #define PERFCOUNTER( var, name )              { name, TYPE_SINGLE, 0 },
diff --git a/xen/include/xen/perfc.h b/xen/include/xen/perfc.h
index f9009dc388..324b476655 100644
--- a/xen/include/xen/perfc.h
+++ b/xen/include/xen/perfc.h
@@ -3,8 +3,7 @@
 
 #ifdef CONFIG_PERF_COUNTERS
 
-#include <xen/lib.h>
-#include <xen/smp.h>
+#include <xen/macros.h>
 #include <xen/percpu.h>
 
 /*
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/perfc: Cleanup
Message-Id: <E1tV8Qs-003tKj-0V@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 12:11:38 +0000

commit 25492368ea429fe3357748660c72456b9ba16528
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 19:36:34 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Cleanup
    
     * Strip trailing whitspace.
     * Remove PRIperfc.  It has never been used and isn't useful.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/common/perfc.c      | 10 +++++-----
 xen/include/xen/perfc.h | 23 +++++++++++------------
 2 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index b748c8af85..8302b7cf6d 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -46,7 +46,7 @@ void cf_check perfc_printall(unsigned char key)
         case TYPE_S_SINGLE:
             for_each_online_cpu ( cpu )
                 sum += per_cpu(perfcounters, cpu)[j];
-            if ( perfc_info[i].type == TYPE_S_SINGLE ) 
+            if ( perfc_info[i].type == TYPE_S_SINGLE )
                 sum = (perfc_t) sum;
             printk("TOTAL[%12Lu]", sum);
             if ( sum )
@@ -56,7 +56,7 @@ void cf_check perfc_printall(unsigned char key)
                 {
                     if ( k > 0 && (k % 4) == 0 )
                         printk("\n%53s", "");
-                    printk("  CPU%02u[%10"PRIperfc"u]", cpu, per_cpu(perfcounters, cpu)[j]);
+                    printk("  CPU%02u[%10u]", cpu, per_cpu(perfcounters, cpu)[j]);
                     ++k;
                 }
             }
@@ -71,7 +71,7 @@ void cf_check perfc_printall(unsigned char key)
                 for ( k = 0; k < perfc_info[i].nr_elements; k++ )
                     sum += counters[k];
             }
-            if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+            if ( perfc_info[i].type == TYPE_S_ARRAY )
                 sum = (perfc_t) sum;
             printk("TOTAL[%12Lu]", sum);
             if (sum)
@@ -82,7 +82,7 @@ void cf_check perfc_printall(unsigned char key)
                     sum = 0;
                     for_each_online_cpu ( cpu )
                         sum += per_cpu(perfcounters, cpu)[j + k];
-                    if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+                    if ( perfc_info[i].type == TYPE_S_ARRAY )
                         sum = (perfc_t) sum;
                     if ( (k % 4) == 0 )
                         printk("\n%16s", "");
@@ -98,7 +98,7 @@ void cf_check perfc_printall(unsigned char key)
                     sum = 0;
                     for ( n = 0; n < perfc_info[i].nr_elements; n++ )
                         sum += counters[n];
-                    if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+                    if ( perfc_info[i].type == TYPE_S_ARRAY )
                         sum = (perfc_t) sum;
                     if ( k > 0 && (k % 4) == 0 )
                         printk("\n%53s", "");
diff --git a/xen/include/xen/perfc.h b/xen/include/xen/perfc.h
index 324b476655..bf0eb032f7 100644
--- a/xen/include/xen/perfc.h
+++ b/xen/include/xen/perfc.h
@@ -8,24 +8,24 @@
 
 /*
  * NOTE: new counters must be defined in perfc_defn.h
- * 
+ *
  * Counter declarations:
  * PERFCOUNTER (counter, string)              define a new performance counter
  * PERFCOUNTER_ARRAY (counter, string, size)  define an array of counters
- * 
+ *
  * Unlike counters, status variables do not reset:
  * PERFSTATUS (counter, string)               define a new performance stauts
  * PERFSTATUS_ARRAY (counter, string, size)   define an array of status vars
- * 
- * unsigned long perfc_value  (counter)        get value of a counter  
+ *
+ * unsigned long perfc_value  (counter)        get value of a counter
  * unsigned long perfc_valuea (counter, index) get value of an array counter
- * unsigned long perfc_set  (counter, val)     set value of a counter  
+ * unsigned long perfc_set  (counter, val)     set value of a counter
  * unsigned long perfc_seta (counter, index, val) set value of an array counter
- * void perfc_incr  (counter)                  increment a counter          
+ * void perfc_incr  (counter)                  increment a counter
  * void perfc_decr  (counter)                  decrement a status
- * void perfc_incra (counter, index)           increment an array counter   
- * void perfc_add   (counter, value)           add a value to a counter     
- * void perfc_adda  (counter, index, value)    add a value to array counter 
+ * void perfc_incra (counter, index)           increment an array counter
+ * void perfc_add   (counter, value)           add a value to a counter
+ * void perfc_adda  (counter, index, value)    add a value to array counter
  * void perfc_print (counter)                  print out the counter
  */
 
@@ -49,7 +49,6 @@ enum {
 #undef PERFSTATUS_ARRAY
 
 typedef unsigned int perfc_t;
-#define PRIperfc ""
 
 DECLARE_PER_CPU(perfc_t[NUM_PERFCOUNTERS], perfcounters);
 
@@ -72,7 +71,7 @@ DECLARE_PER_CPU(perfc_t[NUM_PERFCOUNTERS], perfcounters);
 	 this_cpu(perfcounters)[PERFC_ ## x + (y)] = (v) : (v) )
 
 /*
- * Histogram: special treatment for 0 and 1 count. After that equally spaced 
+ * Histogram: special treatment for 0 and 1 count. After that equally spaced
  * with last bucket taking the rest.
  */
 #ifdef CONFIG_PERF_ARRAYS
@@ -98,7 +97,7 @@ int perfc_control(struct xen_sysctl_perfc_op *pc);
 extern void cf_check perfc_printall(unsigned char key);
 extern void cf_check perfc_reset(unsigned char key);
 
-    
+
 #else /* CONFIG_PERF_COUNTERS */
 
 #define perfc_value(x)    (0)
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/perfc: Drop arch_perfc_{gather,reset}()
Message-Id: <E1tV9sH-0048MO-2L@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 13:44:01 +0000

commit 8900010501121411160562f2086d98831b392c99
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:31:32 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Drop arch_perfc_{gather,reset}()
    
    These were only ever used by the IA64 port, which was droped in commit
    570c311ca2c7 ("remove ia64") in 2012.
    
    Remove them, and clean up the arm/x86 stub headers.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/include/asm/perfc.h | 21 ---------------------
 xen/arch/x86/include/asm/perfc.h | 12 ------------
 xen/common/perfc.c               |  6 ------
 3 files changed, 39 deletions(-)

diff --git a/xen/arch/arm/include/asm/perfc.h b/xen/arch/arm/include/asm/perfc.h
deleted file mode 100644
index 95c4b2b6b7..0000000000
--- a/xen/arch/arm/include/asm/perfc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_PERFC_H__
-#define __ASM_PERFC_H__
-
-static inline void arch_perfc_reset(void)
-{
-}
-
-static inline void arch_perfc_gather(void)
-{
-}
-
-#endif
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
diff --git a/xen/arch/x86/include/asm/perfc.h b/xen/arch/x86/include/asm/perfc.h
deleted file mode 100644
index a1a591e803..0000000000
--- a/xen/arch/x86/include/asm/perfc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ASM_PERFC_H__
-#define __ASM_PERFC_H__
-
-static inline void arch_perfc_reset(void)
-{
-}
-
-static inline void arch_perfc_gather(void)
-{
-}
-
-#endif
diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index 80480aa776..ed4dba36f1 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -8,7 +8,6 @@
 #include <xen/mm.h>
 #include <xen/guest_access.h>
 #include <public/sysctl.h>
-#include <asm/perfc.h>
 
 #define PERFCOUNTER( var, name )              { name, TYPE_SINGLE, 0 },
 #define PERFCOUNTER_ARRAY( var, name, size )  { name, TYPE_ARRAY,  size },
@@ -148,8 +147,6 @@ void cf_check perfc_reset(unsigned char key)
             break;
         }
     }
-
-    arch_perfc_reset();
 }
 
 static struct xen_sysctl_perfc_desc perfc_d[NR_PERFCTRS];
@@ -199,9 +196,6 @@ static int perfc_copy_info(XEN_GUEST_HANDLE_64(xen_sysctl_perfc_desc_t) desc,
     if ( perfc_vals == NULL )
         return -ENOMEM;
 
-    /* Architecture may fill counters from hardware.  */
-    arch_perfc_gather();
-
     /* We gather the counts together every time. */
     for ( i = j = v = 0; i < NR_PERFCTRS; i++ )
     {
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/perfc: Add perfc_defn.h to asm-generic
Message-Id: <E1tV9sR-0048Ou-2q@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 13:44:11 +0000

commit 02c24a1325d37bdf089b980b5618b2b0616260a7
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:18:22 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Add perfc_defn.h to asm-generic
    
    ... and hook it up for RISC-V and PPC.
    
    On RISC-V at least, no combination of headers pulls in errno.h, so include it
    explicitly.
    
    Guard the hypercalls array declaration based on NR_hypercalls existing.  This
    is sufficient to get PERF_COUNTERS fully working on RISC-V and PPC, so drop
    the randconfig override.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Oleksii Kurohcko <oleksii.kurochko@gmail.com>
---
 automation/gitlab-ci/build.yaml         | 1 -
 xen/arch/ppc/include/asm/Makefile       | 1 +
 xen/arch/riscv/configs/tiny64_defconfig | 1 -
 xen/arch/riscv/include/asm/Makefile     | 1 +
 xen/common/perfc.c                      | 1 +
 xen/include/asm-generic/perfc_defn.h    | 5 +++++
 xen/include/xen/perfc_defn.h            | 2 ++
 7 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 1b884cc81c..41f17ed456 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -734,7 +734,6 @@ debian-12-riscv64-gcc:
       CONFIG_GRANT_TABLE=n
       CONFIG_LIVEPATCH=n
       CONFIG_MEM_ACCESS=n
-      CONFIG_PERF_COUNTERS=n
       CONFIG_QEMU_PLATFORM=y
       CONFIG_XSM=n
 
diff --git a/xen/arch/ppc/include/asm/Makefile b/xen/arch/ppc/include/asm/Makefile
index ced02e26ed..c989a7f89b 100644
--- a/xen/arch/ppc/include/asm/Makefile
+++ b/xen/arch/ppc/include/asm/Makefile
@@ -7,6 +7,7 @@ generic-y += hypercall.h
 generic-y += iocap.h
 generic-y += paging.h
 generic-y += percpu.h
+generic-y += perfc_defn.h
 generic-y += random.h
 generic-y += softirq.h
 generic-y += vm_event.h
diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig
index 6af563bd73..bb3ae26a44 100644
--- a/xen/arch/riscv/configs/tiny64_defconfig
+++ b/xen/arch/riscv/configs/tiny64_defconfig
@@ -1,7 +1,6 @@
 # CONFIG_BOOT_TIME_CPUPOOLS is not set
 # CONFIG_GRANT_TABLE is not set
 # CONFIG_MEM_ACCESS is not set
-# CONFIG_PERF_COUNTERS is not set
 # CONFIG_COVERAGE is not set
 # CONFIG_LIVEPATCH is not set
 # CONFIG_XSM is not set
diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile
index ced02e26ed..c989a7f89b 100644
--- a/xen/arch/riscv/include/asm/Makefile
+++ b/xen/arch/riscv/include/asm/Makefile
@@ -7,6 +7,7 @@ generic-y += hypercall.h
 generic-y += iocap.h
 generic-y += paging.h
 generic-y += percpu.h
+generic-y += perfc_defn.h
 generic-y += random.h
 generic-y += softirq.h
 generic-y += vm_event.h
diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index ed4dba36f1..8c967ab900 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -1,4 +1,5 @@
 
+#include <xen/errno.h>
 #include <xen/lib.h>
 #include <xen/smp.h>
 #include <xen/time.h>
diff --git a/xen/include/asm-generic/perfc_defn.h b/xen/include/asm-generic/perfc_defn.h
new file mode 100644
index 0000000000..8237636d83
--- /dev/null
+++ b/xen/include/asm-generic/perfc_defn.h
@@ -0,0 +1,5 @@
+/* This file is legitimately included multiple times. */
+/* #ifndef ASM_GENERIC_PERFC_DEFN_H */
+/* #define ASM_GENERIC_PERFC_DEFN_H */
+
+/* #endif ASM_GENERIC_PERFC_DEFN_H */
diff --git a/xen/include/xen/perfc_defn.h b/xen/include/xen/perfc_defn.h
index 0027d95a60..a987d80dd6 100644
--- a/xen/include/xen/perfc_defn.h
+++ b/xen/include/xen/perfc_defn.h
@@ -4,7 +4,9 @@
 
 #include <asm/perfc_defn.h>
 
+#ifdef NR_hypercalls
 PERFCOUNTER_ARRAY(hypercalls,           "hypercalls", NR_hypercalls)
+#endif
 
 PERFCOUNTER(calls_from_multicall,       "calls from multicall")
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/perfc: Trim includes
Message-Id: <E1tV9sc-0048Pl-00@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 13:44:22 +0000

commit e7ea1de7746c94f0e5349ab7bb3d236c5475eb4d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 18:01:34 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Trim includes
    
    This is mostly for the removal of xen/lib.h and xen/smp.h from perfc.h.  All
    that is needed is xen/macros.h.
    
    Trim and sort the includes for perfc.c too.  There's no need for smp.h,
    keyhandler.h or mm.h, but cpumask.h is needed.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/common/perfc.c      | 9 ++++-----
 xen/include/xen/perfc.h | 3 +--
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index 8c967ab900..b748c8af85 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -1,13 +1,12 @@
 
+#include <xen/cpumask.h>
 #include <xen/errno.h>
+#include <xen/guest_access.h>
 #include <xen/lib.h>
-#include <xen/smp.h>
-#include <xen/time.h>
 #include <xen/perfc.h>
-#include <xen/keyhandler.h> 
 #include <xen/spinlock.h>
-#include <xen/mm.h>
-#include <xen/guest_access.h>
+#include <xen/time.h>
+
 #include <public/sysctl.h>
 
 #define PERFCOUNTER( var, name )              { name, TYPE_SINGLE, 0 },
diff --git a/xen/include/xen/perfc.h b/xen/include/xen/perfc.h
index f9009dc388..324b476655 100644
--- a/xen/include/xen/perfc.h
+++ b/xen/include/xen/perfc.h
@@ -3,8 +3,7 @@
 
 #ifdef CONFIG_PERF_COUNTERS
 
-#include <xen/lib.h>
-#include <xen/smp.h>
+#include <xen/macros.h>
 #include <xen/percpu.h>
 
 /*
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/perfc: Cleanup
Message-Id: <E1tV9sm-0048Qz-0S@xenbits.xenproject.org>
Date: Tue, 07 Jan 2025 13:44:32 +0000

commit 25492368ea429fe3357748660c72456b9ba16528
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Sun Dec 29 19:36:34 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 7 11:50:25 2025 +0000

    xen/perfc: Cleanup
    
     * Strip trailing whitspace.
     * Remove PRIperfc.  It has never been used and isn't useful.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/common/perfc.c      | 10 +++++-----
 xen/include/xen/perfc.h | 23 +++++++++++------------
 2 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/xen/common/perfc.c b/xen/common/perfc.c
index b748c8af85..8302b7cf6d 100644
--- a/xen/common/perfc.c
+++ b/xen/common/perfc.c
@@ -46,7 +46,7 @@ void cf_check perfc_printall(unsigned char key)
         case TYPE_S_SINGLE:
             for_each_online_cpu ( cpu )
                 sum += per_cpu(perfcounters, cpu)[j];
-            if ( perfc_info[i].type == TYPE_S_SINGLE ) 
+            if ( perfc_info[i].type == TYPE_S_SINGLE )
                 sum = (perfc_t) sum;
             printk("TOTAL[%12Lu]", sum);
             if ( sum )
@@ -56,7 +56,7 @@ void cf_check perfc_printall(unsigned char key)
                 {
                     if ( k > 0 && (k % 4) == 0 )
                         printk("\n%53s", "");
-                    printk("  CPU%02u[%10"PRIperfc"u]", cpu, per_cpu(perfcounters, cpu)[j]);
+                    printk("  CPU%02u[%10u]", cpu, per_cpu(perfcounters, cpu)[j]);
                     ++k;
                 }
             }
@@ -71,7 +71,7 @@ void cf_check perfc_printall(unsigned char key)
                 for ( k = 0; k < perfc_info[i].nr_elements; k++ )
                     sum += counters[k];
             }
-            if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+            if ( perfc_info[i].type == TYPE_S_ARRAY )
                 sum = (perfc_t) sum;
             printk("TOTAL[%12Lu]", sum);
             if (sum)
@@ -82,7 +82,7 @@ void cf_check perfc_printall(unsigned char key)
                     sum = 0;
                     for_each_online_cpu ( cpu )
                         sum += per_cpu(perfcounters, cpu)[j + k];
-                    if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+                    if ( perfc_info[i].type == TYPE_S_ARRAY )
                         sum = (perfc_t) sum;
                     if ( (k % 4) == 0 )
                         printk("\n%16s", "");
@@ -98,7 +98,7 @@ void cf_check perfc_printall(unsigned char key)
                     sum = 0;
                     for ( n = 0; n < perfc_info[i].nr_elements; n++ )
                         sum += counters[n];
-                    if ( perfc_info[i].type == TYPE_S_ARRAY ) 
+                    if ( perfc_info[i].type == TYPE_S_ARRAY )
                         sum = (perfc_t) sum;
                     if ( k > 0 && (k % 4) == 0 )
                         printk("\n%53s", "");
diff --git a/xen/include/xen/perfc.h b/xen/include/xen/perfc.h
index 324b476655..bf0eb032f7 100644
--- a/xen/include/xen/perfc.h
+++ b/xen/include/xen/perfc.h
@@ -8,24 +8,24 @@
 
 /*
  * NOTE: new counters must be defined in perfc_defn.h
- * 
+ *
  * Counter declarations:
  * PERFCOUNTER (counter, string)              define a new performance counter
  * PERFCOUNTER_ARRAY (counter, string, size)  define an array of counters
- * 
+ *
  * Unlike counters, status variables do not reset:
  * PERFSTATUS (counter, string)               define a new performance stauts
  * PERFSTATUS_ARRAY (counter, string, size)   define an array of status vars
- * 
- * unsigned long perfc_value  (counter)        get value of a counter  
+ *
+ * unsigned long perfc_value  (counter)        get value of a counter
  * unsigned long perfc_valuea (counter, index) get value of an array counter
- * unsigned long perfc_set  (counter, val)     set value of a counter  
+ * unsigned long perfc_set  (counter, val)     set value of a counter
  * unsigned long perfc_seta (counter, index, val) set value of an array counter
- * void perfc_incr  (counter)                  increment a counter          
+ * void perfc_incr  (counter)                  increment a counter
  * void perfc_decr  (counter)                  decrement a status
- * void perfc_incra (counter, index)           increment an array counter   
- * void perfc_add   (counter, value)           add a value to a counter     
- * void perfc_adda  (counter, index, value)    add a value to array counter 
+ * void perfc_incra (counter, index)           increment an array counter
+ * void perfc_add   (counter, value)           add a value to a counter
+ * void perfc_adda  (counter, index, value)    add a value to array counter
  * void perfc_print (counter)                  print out the counter
  */
 
@@ -49,7 +49,6 @@ enum {
 #undef PERFSTATUS_ARRAY
 
 typedef unsigned int perfc_t;
-#define PRIperfc ""
 
 DECLARE_PER_CPU(perfc_t[NUM_PERFCOUNTERS], perfcounters);
 
@@ -72,7 +71,7 @@ DECLARE_PER_CPU(perfc_t[NUM_PERFCOUNTERS], perfcounters);
 	 this_cpu(perfcounters)[PERFC_ ## x + (y)] = (v) : (v) )
 
 /*
- * Histogram: special treatment for 0 and 1 count. After that equally spaced 
+ * Histogram: special treatment for 0 and 1 count. After that equally spaced
  * with last bucket taking the rest.
  */
 #ifdef CONFIG_PERF_ARRAYS
@@ -98,7 +97,7 @@ int perfc_control(struct xen_sysctl_perfc_op *pc);
 extern void cf_check perfc_printall(unsigned char key);
 extern void cf_check perfc_reset(unsigned char key);
 
-    
+
 #else /* CONFIG_PERF_COUNTERS */
 
 #define perfc_value(x)    (0)
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] libxl: drop setting XEN_QEMU_CONSOLE_LIMIT in the environment (XSA-180 / CVE-2014-3672)
Message-Id: <E1tVT1n-006RX6-1v@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 10:11:07 +0000

commit 15bbbecad5a69c8ce34c8b68352cf378d891ac97
Author:     James Dingwall <james@dingwall.me.uk>
AuthorDate: Wed Jan 8 11:00:54 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:00:54 2025 +0100

    libxl: drop setting XEN_QEMU_CONSOLE_LIMIT in the environment (XSA-180 / CVE-2014-3672)
    
    The corresponding code in the Xen qemu repository was not applied from
    qemu-xen-4.18.0.
    
    Signed-off-by: James Dingwall <james@dingwall.me.uk>
    Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
---
 tools/libs/light/libxl_dm.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c
index 1f2f5bd97a..b193a5dc37 100644
--- a/tools/libs/light/libxl_dm.c
+++ b/tools/libs/light/libxl_dm.c
@@ -638,20 +638,6 @@ int libxl__domain_device_construct_rdm(libxl__gc *gc,
     return ERROR_FAIL;
 }
 
-/* XSA-180 / CVE-2014-3672
- *
- * The QEMU shipped with Xen has a bodge. It checks for
- * XEN_QEMU_CONSOLE_LIMIT to see how much data QEMU is allowed
- * to write to stderr. We set that to 1MB if it is not set by
- * system administrator.
- */
-static void libxl__set_qemu_env_for_xsa_180(libxl__gc *gc,
-                                            flexarray_t *dm_envs)
-{
-    if (getenv("XEN_QEMU_CONSOLE_LIMIT")) return;
-    flexarray_append_pair(dm_envs, "XEN_QEMU_CONSOLE_LIMIT", "1048576");
-}
-
 const libxl_vnc_info *libxl__dm_vnc(const libxl_domain_config *guest_config)
 {
     const libxl_vnc_info *vnc = NULL;
@@ -704,8 +690,6 @@ static int libxl__build_device_model_args_old(libxl__gc *gc,
 
     assert(state->dm_monitor_fd == -1);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
-
     flexarray_vappend(dm_args, dm,
                       "-d", GCSPRINTF("%d", domid), NULL);
 
@@ -1210,8 +1194,6 @@ static int libxl__build_device_model_args_new(libxl__gc *gc,
     dm_args = flexarray_make(gc, 16, 1);
     dm_envs = flexarray_make(gc, 16, 1);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
-
     flexarray_vappend(dm_args, dm,
                       "-xen-domid",
                       GCSPRINTF("%d", guest_domid), NULL);
@@ -3656,7 +3638,6 @@ void libxl__spawn_qemu_xenpv_backend(libxl__egc *egc,
     flexarray_append(dm_args, NULL);
     args = (char **) flexarray_contents(dm_args);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
     envs = (char **) flexarray_contents(dm_envs);
 
     logfile_w = libxl__create_qemu_logfile(gc, GCSPRINTF("qdisk-%u", domid));
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1tVT1x-006RXu-2Y@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 10:11:17 +0000

commit d3709d1324aa140f064b9c68da37547f459f8e8d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed Jan 8 11:01:17 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:01:17 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index b89d440133..762fc34778 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3596,12 +3596,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4819,7 +4822,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1tVT27-006RYm-36@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 10:11:27 +0000

commit 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed Jan 8 11:02:16 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:02:16 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 762fc34778..7e12b19805 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] libxl: drop setting XEN_QEMU_CONSOLE_LIMIT in the environment (XSA-180 / CVE-2014-3672)
Message-Id: <E1tVUJ4-006bas-0D@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 11:33:02 +0000

commit 15bbbecad5a69c8ce34c8b68352cf378d891ac97
Author:     James Dingwall <james@dingwall.me.uk>
AuthorDate: Wed Jan 8 11:00:54 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:00:54 2025 +0100

    libxl: drop setting XEN_QEMU_CONSOLE_LIMIT in the environment (XSA-180 / CVE-2014-3672)
    
    The corresponding code in the Xen qemu repository was not applied from
    qemu-xen-4.18.0.
    
    Signed-off-by: James Dingwall <james@dingwall.me.uk>
    Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
---
 tools/libs/light/libxl_dm.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c
index 1f2f5bd97a..b193a5dc37 100644
--- a/tools/libs/light/libxl_dm.c
+++ b/tools/libs/light/libxl_dm.c
@@ -638,20 +638,6 @@ int libxl__domain_device_construct_rdm(libxl__gc *gc,
     return ERROR_FAIL;
 }
 
-/* XSA-180 / CVE-2014-3672
- *
- * The QEMU shipped with Xen has a bodge. It checks for
- * XEN_QEMU_CONSOLE_LIMIT to see how much data QEMU is allowed
- * to write to stderr. We set that to 1MB if it is not set by
- * system administrator.
- */
-static void libxl__set_qemu_env_for_xsa_180(libxl__gc *gc,
-                                            flexarray_t *dm_envs)
-{
-    if (getenv("XEN_QEMU_CONSOLE_LIMIT")) return;
-    flexarray_append_pair(dm_envs, "XEN_QEMU_CONSOLE_LIMIT", "1048576");
-}
-
 const libxl_vnc_info *libxl__dm_vnc(const libxl_domain_config *guest_config)
 {
     const libxl_vnc_info *vnc = NULL;
@@ -704,8 +690,6 @@ static int libxl__build_device_model_args_old(libxl__gc *gc,
 
     assert(state->dm_monitor_fd == -1);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
-
     flexarray_vappend(dm_args, dm,
                       "-d", GCSPRINTF("%d", domid), NULL);
 
@@ -1210,8 +1194,6 @@ static int libxl__build_device_model_args_new(libxl__gc *gc,
     dm_args = flexarray_make(gc, 16, 1);
     dm_envs = flexarray_make(gc, 16, 1);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
-
     flexarray_vappend(dm_args, dm,
                       "-xen-domid",
                       GCSPRINTF("%d", guest_domid), NULL);
@@ -3656,7 +3638,6 @@ void libxl__spawn_qemu_xenpv_backend(libxl__egc *egc,
     flexarray_append(dm_args, NULL);
     args = (char **) flexarray_contents(dm_args);
 
-    libxl__set_qemu_env_for_xsa_180(gc, dm_envs);
     envs = (char **) flexarray_contents(dm_envs);
 
     logfile_w = libxl__create_qemu_logfile(gc, GCSPRINTF("qdisk-%u", domid));
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1tVUJE-006bdT-0f@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 11:33:12 +0000

commit d3709d1324aa140f064b9c68da37547f459f8e8d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed Jan 8 11:01:17 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:01:17 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index b89d440133..762fc34778 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3596,12 +3596,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4819,7 +4822,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1tVUJO-006be3-13@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 11:33:22 +0000

commit 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed Jan 8 11:02:16 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 8 11:02:16 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 762fc34778..7e12b19805 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1tVWwh-006xj9-20@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 14:22:07 +0000

commit 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:17 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:38 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 2b4efde689..5118f86cf0 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -832,6 +832,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/flask: Wire up XEN_DOMCTL_dt_overlay
Message-Id: <E1tVWwr-006xje-2S@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 14:22:17 +0000

commit 7fa1411676150634b1d6ca030e53b94c26a949dd
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:18 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:50 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_dt_overlay
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only dt overlay operation is attaching that can
    happen only after the domain is created. Dom0 can attach overlay to itself
    as well.
    
    Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/dom0.te  | 2 +-
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index 16b8c9646d..f148bfbf27 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -40,7 +40,7 @@ allow dom0_t dom0_t:domain {
 };
 allow dom0_t dom0_t:domain2 {
 	set_cpu_policy gettsc settsc setscheduler set_vnumainfo
-	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy
+	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy dt_overlay
 };
 allow dom0_t dom0_t:resource { add remove };
 
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index ba9e91d302..def60da883 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -94,7 +94,7 @@ define(`manage_domain', `
 			getaddrsize pause unpause trigger shutdown destroy
 			setaffinity setdomainmaxmem getscheduler resume
 			setpodtarget getpodtarget getpagingmempool setpagingmempool };
-    allow $1 $2:domain2 set_vnumainfo;
+    allow $1 $2:domain2 { set_vnumainfo dt_overlay };
 ')
 
 # migrate_domain_out(priv, target)
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 5118f86cf0..e263e745d4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -844,6 +844,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_set_paging_mempool_size:
         return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__SETPAGINGMEMPOOL);
 
+    case XEN_DOMCTL_dt_overlay:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 7cbdb7ea64..78fe37583b 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -253,6 +253,8 @@ class domain2
     get_cpu_policy
 # XEN_DOMCTL_vuart_op
     vuart_op
+# XEN_DOMCTL_dt_overlay
+    dt_overlay
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/flask: Wire up XEN_DOMCTL_set_llc_colors
Message-Id: <E1tVWx1-006xkh-2q@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 14:22:27 +0000

commit 83a4dade0f927d2364172abb8eea6fbae1548c99
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:19 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:58 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_set_llc_colors
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. Setting LLC colors is only possible during domain
    creation.
    
    Fixes: 6985aa5e0c3c ("xen: extend domctl interface for cache coloring")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index def60da883..f7cf7c43c8 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy vuart_op };
+			resource_map get_cpu_policy vuart_op set_llc_colors };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index e263e745d4..14d84df9ca 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -847,6 +847,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_dt_overlay:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
 
+    case XEN_DOMCTL_set_llc_colors:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SET_LLC_COLORS);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 78fe37583b..320d77706d 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -255,6 +255,8 @@ class domain2
     vuart_op
 # XEN_DOMCTL_dt_overlay
     dt_overlay
+# XEN_DOMCTL_set_llc_colors
+    set_llc_colors
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm64: Drop relocate_and_switch_ttbr() stub
Message-Id: <E1tVWxB-006xns-3A@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 14:22:37 +0000

commit 70f5a875becc9444a959830b10a361982c31a366
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed Jan 8 08:57:19 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:06:05 2025 +0100

    xen/arm64: Drop relocate_and_switch_ttbr() stub
    
    In the original patch e7a80636f16e ("xen/arm: add cache coloring support
    for Xen image"), the stub was added under wrong assumption that DCE
    won't remove the function call if it's not static. This assumption is
    incorrect as we already rely on DCE for cases like this one. Therefore
    drop the stub, that otherwise would be a place potentially prone to
    errors in the future.
    
    Suggested-by: Julien Grall <julien@xen.org>
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/arm64/mmu/mm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/xen/arch/arm/arm64/mmu/mm.c b/xen/arch/arm/arm64/mmu/mm.c
index 26361c4fe4..c1efa1348a 100644
--- a/xen/arch/arm/arm64/mmu/mm.c
+++ b/xen/arch/arm/arm64/mmu/mm.c
@@ -171,8 +171,6 @@ void __init relocate_and_switch_ttbr(uint64_t ttbr)
      */
     update_identity_mapping(false);
 }
-#else
-void __init relocate_and_switch_ttbr(uint64_t ttbr) {}
 #endif
 
 void __init switch_ttbr(uint64_t ttbr)
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1tVXi1-00757n-37@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 15:11:01 +0000

commit 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:17 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:38 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 2b4efde689..5118f86cf0 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -832,6 +832,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/flask: Wire up XEN_DOMCTL_dt_overlay
Message-Id: <E1tVXiC-00758d-0M@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 15:11:12 +0000

commit 7fa1411676150634b1d6ca030e53b94c26a949dd
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:18 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:50 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_dt_overlay
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only dt overlay operation is attaching that can
    happen only after the domain is created. Dom0 can attach overlay to itself
    as well.
    
    Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/dom0.te  | 2 +-
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index 16b8c9646d..f148bfbf27 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -40,7 +40,7 @@ allow dom0_t dom0_t:domain {
 };
 allow dom0_t dom0_t:domain2 {
 	set_cpu_policy gettsc settsc setscheduler set_vnumainfo
-	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy
+	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy dt_overlay
 };
 allow dom0_t dom0_t:resource { add remove };
 
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index ba9e91d302..def60da883 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -94,7 +94,7 @@ define(`manage_domain', `
 			getaddrsize pause unpause trigger shutdown destroy
 			setaffinity setdomainmaxmem getscheduler resume
 			setpodtarget getpodtarget getpagingmempool setpagingmempool };
-    allow $1 $2:domain2 set_vnumainfo;
+    allow $1 $2:domain2 { set_vnumainfo dt_overlay };
 ')
 
 # migrate_domain_out(priv, target)
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 5118f86cf0..e263e745d4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -844,6 +844,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_set_paging_mempool_size:
         return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__SETPAGINGMEMPOOL);
 
+    case XEN_DOMCTL_dt_overlay:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 7cbdb7ea64..78fe37583b 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -253,6 +253,8 @@ class domain2
     get_cpu_policy
 # XEN_DOMCTL_vuart_op
     vuart_op
+# XEN_DOMCTL_dt_overlay
+    dt_overlay
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/flask: Wire up XEN_DOMCTL_set_llc_colors
Message-Id: <E1tVXiM-00759G-0k@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 15:11:22 +0000

commit 83a4dade0f927d2364172abb8eea6fbae1548c99
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 7 10:27:19 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:05:58 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_set_llc_colors
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. Setting LLC colors is only possible during domain
    creation.
    
    Fixes: 6985aa5e0c3c ("xen: extend domctl interface for cache coloring")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index def60da883..f7cf7c43c8 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy vuart_op };
+			resource_map get_cpu_policy vuart_op set_llc_colors };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index e263e745d4..14d84df9ca 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -847,6 +847,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_dt_overlay:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
 
+    case XEN_DOMCTL_set_llc_colors:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SET_LLC_COLORS);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 78fe37583b..320d77706d 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -255,6 +255,8 @@ class domain2
     vuart_op
 # XEN_DOMCTL_dt_overlay
     dt_overlay
+# XEN_DOMCTL_set_llc_colors
+    set_llc_colors
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm64: Drop relocate_and_switch_ttbr() stub
Message-Id: <E1tVXiW-0075EG-18@xenbits.xenproject.org>
Date: Wed, 08 Jan 2025 15:11:32 +0000

commit 70f5a875becc9444a959830b10a361982c31a366
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed Jan 8 08:57:19 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 8 13:06:05 2025 +0100

    xen/arm64: Drop relocate_and_switch_ttbr() stub
    
    In the original patch e7a80636f16e ("xen/arm: add cache coloring support
    for Xen image"), the stub was added under wrong assumption that DCE
    won't remove the function call if it's not static. This assumption is
    incorrect as we already rely on DCE for cases like this one. Therefore
    drop the stub, that otherwise would be a place potentially prone to
    errors in the future.
    
    Suggested-by: Julien Grall <julien@xen.org>
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/arm64/mmu/mm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/xen/arch/arm/arm64/mmu/mm.c b/xen/arch/arm/arm64/mmu/mm.c
index 26361c4fe4..c1efa1348a 100644
--- a/xen/arch/arm/arm64/mmu/mm.c
+++ b/xen/arch/arm/arm64/mmu/mm.c
@@ -171,8 +171,6 @@ void __init relocate_and_switch_ttbr(uint64_t ttbr)
      */
     update_identity_mapping(false);
 }
-#else
-void __init relocate_and_switch_ttbr(uint64_t ttbr) {}
 #endif
 
 void __init switch_ttbr(uint64_t ttbr)
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: Update Fedora to 41
Message-Id: <E1tVpfz-009EDn-2U@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 10:22:07 +0000

commit 40f35d07aa14bde44d7baafad171f7c92b053017
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Jan 8 12:05:38 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 9 10:13:47 2025 +0000

    CI: Update Fedora to 41
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/build/fedora/40-x86_64.dockerfile | 77 ----------------------------
 automation/build/fedora/41-x86_64.dockerfile | 77 ++++++++++++++++++++++++++++
 automation/gitlab-ci/build.yaml              |  8 +--
 automation/scripts/containerize              |  2 +-
 4 files changed, 82 insertions(+), 82 deletions(-)

diff --git a/automation/build/fedora/40-x86_64.dockerfile b/automation/build/fedora/40-x86_64.dockerfile
deleted file mode 100644
index 7d4d4cc2ac..0000000000
--- a/automation/build/fedora/40-x86_64.dockerfile
+++ /dev/null
@@ -1,77 +0,0 @@
-# syntax=docker/dockerfile:1
-FROM --platform=linux/amd64 fedora:40
-LABEL maintainer.name="The Xen Project"
-LABEL maintainer.email="xen-devel@lists.xenproject.org"
-
-RUN <<EOF
-    set -e
-
-    useradd --create-home user
-
-    dnf -y update
-
-    DEPS=(
-        # Xen
-        binutils
-        gcc
-        make
-        python3
-        # Kconfig
-        bison
-        flex
-        # Flask
-        checkpolicy
-
-        # Tools (general)
-        git-core
-        gzip
-        patch
-        perl-interpreter
-        perl-File-Find
-        pkgconfig
-        wget
-        # libxenguest dombuilder
-        bzip2-devel
-        libzstd-devel
-        lzo-devel
-        xz-devel
-        zlib-devel
-        # libacpi
-        acpica-tools
-        # libxl
-        libuuid-devel
-        yajl-devel
-        # xen-foreign
-        diffutils
-        # RomBIOS
-        dev86
-        # Header Check
-        gcc-c++
-        # xentop
-        ncurses-devel
-        # Python bindings
-        python3-devel
-        python3-setuptools
-        # Ocaml bindings/oxenstored
-        ocaml
-        ocaml-findlib
-        # Golang bindings
-        golang
-
-        # Stubdom download/extract
-        bzip2
-
-        # Qemu build
-        glib2-devel
-        pixman-devel
-        ninja-build
-    )
-
-    dnf -y --setopt=install_weak_deps=False install "${DEPS[@]}"
-
-    dnf clean all
-    rm -rf /var/cache/dnf
-EOF
-
-USER user
-WORKDIR /build
diff --git a/automation/build/fedora/41-x86_64.dockerfile b/automation/build/fedora/41-x86_64.dockerfile
new file mode 100644
index 0000000000..8032a20986
--- /dev/null
+++ b/automation/build/fedora/41-x86_64.dockerfile
@@ -0,0 +1,77 @@
+# syntax=docker/dockerfile:1
+FROM --platform=linux/amd64 fedora:41
+LABEL maintainer.name="The Xen Project"
+LABEL maintainer.email="xen-devel@lists.xenproject.org"
+
+RUN <<EOF
+    set -e
+
+    useradd --create-home user
+
+    dnf -y update
+
+    DEPS=(
+        # Xen
+        binutils
+        gcc
+        make
+        python3
+        # Kconfig
+        bison
+        flex
+        # Flask
+        checkpolicy
+
+        # Tools (general)
+        git-core
+        gzip
+        patch
+        perl-interpreter
+        perl-File-Find
+        pkgconfig
+        wget
+        # libxenguest dombuilder
+        bzip2-devel
+        libzstd-devel
+        lzo-devel
+        xz-devel
+        zlib-devel
+        # libacpi
+        acpica-tools
+        # libxl
+        libuuid-devel
+        yajl-devel
+        # xen-foreign
+        diffutils
+        # RomBIOS
+        dev86
+        # Header Check
+        gcc-c++
+        # xentop
+        ncurses-devel
+        # Python bindings
+        python3-devel
+        python3-setuptools
+        # Ocaml bindings/oxenstored
+        ocaml
+        ocaml-findlib
+        # Golang bindings
+        golang
+
+        # Stubdom download/extract
+        bzip2
+
+        # Qemu build
+        glib2-devel
+        pixman-devel
+        ninja-build
+    )
+
+    dnf -y --setopt=install_weak_deps=False install "${DEPS[@]}"
+
+    dnf clean all
+    rm -rf /var/cache/dnf
+EOF
+
+USER user
+WORKDIR /build
diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 41f17ed456..3abd2a0c65 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -572,15 +572,15 @@ debian-12-x86_32-gcc-debug:
   variables:
     CONTAINER: debian:12-x86_32
 
-fedora-40-x86_64-gcc:
+fedora-41-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
-    CONTAINER: fedora:40-x86_64
+    CONTAINER: fedora:41-x86_64
 
-fedora-40-x86_64-gcc-debug:
+fedora-41-x86_64-gcc-debug:
   extends: .gcc-x86-64-build-debug
   variables:
-    CONTAINER: fedora:40-x86_64
+    CONTAINER: fedora:41-x86_64
 
 ubuntu-16.04-x86_64-clang:
   extends: .clang-x86-64-build
diff --git a/automation/scripts/containerize b/automation/scripts/containerize
index d72c22c103..bc43136078 100755
--- a/automation/scripts/containerize
+++ b/automation/scripts/containerize
@@ -28,7 +28,7 @@ case "_${CONTAINER}" in
     _alpine-arm64v8) CONTAINER="${BASE}/alpine:3.18-arm64v8" ;;
     _archlinux|_arch) CONTAINER="${BASE}/archlinux:current" ;;
     _centos7) CONTAINER="${BASE}/centos:7" ;;
-    _fedora) CONTAINER="${BASE}/fedora:40-x86_64";;
+    _fedora) CONTAINER="${BASE}/fedora:41-x86_64";;
     _bullseye-ppc64le) CONTAINER="${BASE}/debian:11-ppc64le" ;;
     _bookworm-ppc64le) CONTAINER="${BASE}/debian:12-ppc64le" ;;
     _bullseye-riscv64) CONTAINER="${BASE}/debian:11-riscv64" ;;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: Update Fedora to 41
Message-Id: <E1tVtlR-009YOf-1T@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 14:44:01 +0000

commit 40f35d07aa14bde44d7baafad171f7c92b053017
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Jan 8 12:05:38 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 9 10:13:47 2025 +0000

    CI: Update Fedora to 41
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/build/fedora/40-x86_64.dockerfile | 77 ----------------------------
 automation/build/fedora/41-x86_64.dockerfile | 77 ++++++++++++++++++++++++++++
 automation/gitlab-ci/build.yaml              |  8 +--
 automation/scripts/containerize              |  2 +-
 4 files changed, 82 insertions(+), 82 deletions(-)

diff --git a/automation/build/fedora/40-x86_64.dockerfile b/automation/build/fedora/40-x86_64.dockerfile
deleted file mode 100644
index 7d4d4cc2ac..0000000000
--- a/automation/build/fedora/40-x86_64.dockerfile
+++ /dev/null
@@ -1,77 +0,0 @@
-# syntax=docker/dockerfile:1
-FROM --platform=linux/amd64 fedora:40
-LABEL maintainer.name="The Xen Project"
-LABEL maintainer.email="xen-devel@lists.xenproject.org"
-
-RUN <<EOF
-    set -e
-
-    useradd --create-home user
-
-    dnf -y update
-
-    DEPS=(
-        # Xen
-        binutils
-        gcc
-        make
-        python3
-        # Kconfig
-        bison
-        flex
-        # Flask
-        checkpolicy
-
-        # Tools (general)
-        git-core
-        gzip
-        patch
-        perl-interpreter
-        perl-File-Find
-        pkgconfig
-        wget
-        # libxenguest dombuilder
-        bzip2-devel
-        libzstd-devel
-        lzo-devel
-        xz-devel
-        zlib-devel
-        # libacpi
-        acpica-tools
-        # libxl
-        libuuid-devel
-        yajl-devel
-        # xen-foreign
-        diffutils
-        # RomBIOS
-        dev86
-        # Header Check
-        gcc-c++
-        # xentop
-        ncurses-devel
-        # Python bindings
-        python3-devel
-        python3-setuptools
-        # Ocaml bindings/oxenstored
-        ocaml
-        ocaml-findlib
-        # Golang bindings
-        golang
-
-        # Stubdom download/extract
-        bzip2
-
-        # Qemu build
-        glib2-devel
-        pixman-devel
-        ninja-build
-    )
-
-    dnf -y --setopt=install_weak_deps=False install "${DEPS[@]}"
-
-    dnf clean all
-    rm -rf /var/cache/dnf
-EOF
-
-USER user
-WORKDIR /build
diff --git a/automation/build/fedora/41-x86_64.dockerfile b/automation/build/fedora/41-x86_64.dockerfile
new file mode 100644
index 0000000000..8032a20986
--- /dev/null
+++ b/automation/build/fedora/41-x86_64.dockerfile
@@ -0,0 +1,77 @@
+# syntax=docker/dockerfile:1
+FROM --platform=linux/amd64 fedora:41
+LABEL maintainer.name="The Xen Project"
+LABEL maintainer.email="xen-devel@lists.xenproject.org"
+
+RUN <<EOF
+    set -e
+
+    useradd --create-home user
+
+    dnf -y update
+
+    DEPS=(
+        # Xen
+        binutils
+        gcc
+        make
+        python3
+        # Kconfig
+        bison
+        flex
+        # Flask
+        checkpolicy
+
+        # Tools (general)
+        git-core
+        gzip
+        patch
+        perl-interpreter
+        perl-File-Find
+        pkgconfig
+        wget
+        # libxenguest dombuilder
+        bzip2-devel
+        libzstd-devel
+        lzo-devel
+        xz-devel
+        zlib-devel
+        # libacpi
+        acpica-tools
+        # libxl
+        libuuid-devel
+        yajl-devel
+        # xen-foreign
+        diffutils
+        # RomBIOS
+        dev86
+        # Header Check
+        gcc-c++
+        # xentop
+        ncurses-devel
+        # Python bindings
+        python3-devel
+        python3-setuptools
+        # Ocaml bindings/oxenstored
+        ocaml
+        ocaml-findlib
+        # Golang bindings
+        golang
+
+        # Stubdom download/extract
+        bzip2
+
+        # Qemu build
+        glib2-devel
+        pixman-devel
+        ninja-build
+    )
+
+    dnf -y --setopt=install_weak_deps=False install "${DEPS[@]}"
+
+    dnf clean all
+    rm -rf /var/cache/dnf
+EOF
+
+USER user
+WORKDIR /build
diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 41f17ed456..3abd2a0c65 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -572,15 +572,15 @@ debian-12-x86_32-gcc-debug:
   variables:
     CONTAINER: debian:12-x86_32
 
-fedora-40-x86_64-gcc:
+fedora-41-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
-    CONTAINER: fedora:40-x86_64
+    CONTAINER: fedora:41-x86_64
 
-fedora-40-x86_64-gcc-debug:
+fedora-41-x86_64-gcc-debug:
   extends: .gcc-x86-64-build-debug
   variables:
-    CONTAINER: fedora:40-x86_64
+    CONTAINER: fedora:41-x86_64
 
 ubuntu-16.04-x86_64-clang:
   extends: .clang-x86-64-build
diff --git a/automation/scripts/containerize b/automation/scripts/containerize
index d72c22c103..bc43136078 100755
--- a/automation/scripts/containerize
+++ b/automation/scripts/containerize
@@ -28,7 +28,7 @@ case "_${CONTAINER}" in
     _alpine-arm64v8) CONTAINER="${BASE}/alpine:3.18-arm64v8" ;;
     _archlinux|_arch) CONTAINER="${BASE}/archlinux:current" ;;
     _centos7) CONTAINER="${BASE}/centos:7" ;;
-    _fedora) CONTAINER="${BASE}/fedora:40-x86_64";;
+    _fedora) CONTAINER="${BASE}/fedora:41-x86_64";;
     _bullseye-ppc64le) CONTAINER="${BASE}/debian:11-ppc64le" ;;
     _bookworm-ppc64le) CONTAINER="${BASE}/debian:12-ppc64le" ;;
     _bullseye-riscv64) CONTAINER="${BASE}/debian:11-riscv64" ;;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: ffa: fix build with clang
Message-Id: <E1tVvdf-009iWG-2P@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 16:44:07 +0000

commit a1a1e2b7dc4f1750ae8421521cb294c5971263cc
Author:     Stewart Hildebrand <stewart.hildebrand@amd.com>
AuthorDate: Thu Jan 9 17:33:14 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 9 17:33:14 2025 +0100

    xen/arm: ffa: fix build with clang
    
    Clang 16 reports:
    
    In file included from arch/arm/tee/ffa.c:72:
    arch/arm/tee/ffa_private.h:329:17: error: 'used' attribute ignored on a non-definition declaration [-Werror,-Wignored-attributes]
    extern uint32_t __ro_after_init ffa_fw_version;
                    ^
    
    The variable ffa_fw_version is only used in ffa.c. Remove the
    declaration in the header and make the definition in ffa.c static.
    
    Fixes: 2f9f240a5e87 ("xen/arm: ffa: Fine granular call support")
    Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/tee/ffa.c         | 2 +-
 xen/arch/arm/tee/ffa_private.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
index 87775ed88f..3bbdd7168a 100644
--- a/xen/arch/arm/tee/ffa.c
+++ b/xen/arch/arm/tee/ffa.c
@@ -72,7 +72,7 @@
 #include "ffa_private.h"
 
 /* Negotiated FF-A version to use with the SPMC, 0 if not there or supported */
-uint32_t __ro_after_init ffa_fw_version;
+static uint32_t __ro_after_init ffa_fw_version;
 
 /* Features supported by the SPMC or secure world when present */
 DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h
index d441c0ca55..c4cd655389 100644
--- a/xen/arch/arm/tee/ffa_private.h
+++ b/xen/arch/arm/tee/ffa_private.h
@@ -326,7 +326,6 @@ extern void *ffa_rx;
 extern void *ffa_tx;
 extern spinlock_t ffa_rx_buffer_lock;
 extern spinlock_t ffa_tx_buffer_lock;
-extern uint32_t __ro_after_init ffa_fw_version;
 extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
 
 bool ffa_shm_domain_destroy(struct domain *d);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1tVvdp-009iXU-2k@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 16:44:17 +0000

commit 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Thu Jan 9 17:34:01 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 9 17:34:01 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 8db2ca4ba2..46281b16ce 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -979,6 +979,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -992,14 +993,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: ffa: fix build with clang
Message-Id: <E1tVwEL-009ske-27@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 17:22:01 +0000

commit a1a1e2b7dc4f1750ae8421521cb294c5971263cc
Author:     Stewart Hildebrand <stewart.hildebrand@amd.com>
AuthorDate: Thu Jan 9 17:33:14 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 9 17:33:14 2025 +0100

    xen/arm: ffa: fix build with clang
    
    Clang 16 reports:
    
    In file included from arch/arm/tee/ffa.c:72:
    arch/arm/tee/ffa_private.h:329:17: error: 'used' attribute ignored on a non-definition declaration [-Werror,-Wignored-attributes]
    extern uint32_t __ro_after_init ffa_fw_version;
                    ^
    
    The variable ffa_fw_version is only used in ffa.c. Remove the
    declaration in the header and make the definition in ffa.c static.
    
    Fixes: 2f9f240a5e87 ("xen/arm: ffa: Fine granular call support")
    Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/tee/ffa.c         | 2 +-
 xen/arch/arm/tee/ffa_private.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
index 87775ed88f..3bbdd7168a 100644
--- a/xen/arch/arm/tee/ffa.c
+++ b/xen/arch/arm/tee/ffa.c
@@ -72,7 +72,7 @@
 #include "ffa_private.h"
 
 /* Negotiated FF-A version to use with the SPMC, 0 if not there or supported */
-uint32_t __ro_after_init ffa_fw_version;
+static uint32_t __ro_after_init ffa_fw_version;
 
 /* Features supported by the SPMC or secure world when present */
 DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h
index d441c0ca55..c4cd655389 100644
--- a/xen/arch/arm/tee/ffa_private.h
+++ b/xen/arch/arm/tee/ffa_private.h
@@ -326,7 +326,6 @@ extern void *ffa_rx;
 extern void *ffa_tx;
 extern spinlock_t ffa_rx_buffer_lock;
 extern spinlock_t ffa_tx_buffer_lock;
-extern uint32_t __ro_after_init ffa_fw_version;
 extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
 
 bool ffa_shm_domain_destroy(struct domain *d);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1tVwEV-009smK-2e@xenbits.xenproject.org>
Date: Thu, 09 Jan 2025 17:22:11 +0000

commit 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Thu Jan 9 17:34:01 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 9 17:34:01 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 8db2ca4ba2..46281b16ce 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -979,6 +979,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -992,14 +993,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs: fusa: Add dom0less domain configuration requirements
Message-Id: <E1tW9Vz-00BD67-3B@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 07:33:07 +0000

commit b9f9b396452aa5fecbe87d8aedbe3c075cf4116c
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed Jan 8 17:03:04 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu Jan 9 17:37:58 2025 +0100

    docs: fusa: Add dom0less domain configuration requirements
    
    Add requirements for dom0less domain creation.
    
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 docs/fusa/reqs/index.rst                   |   1 +
 docs/fusa/reqs/market-reqs/reqs.rst        |  32 ++++++
 docs/fusa/reqs/product-reqs/arm64/reqs.rst | 128 ++++++++++++++++++++++-
 docs/fusa/reqs/product-reqs/reqs.rst       | 160 +++++++++++++++++++++++++++++
 4 files changed, 319 insertions(+), 2 deletions(-)

diff --git a/docs/fusa/reqs/index.rst b/docs/fusa/reqs/index.rst
index 8a4dae6fb2..1088a51d52 100644
--- a/docs/fusa/reqs/index.rst
+++ b/docs/fusa/reqs/index.rst
@@ -8,6 +8,7 @@ Requirements documentation
 
    intro
    market-reqs/reqs
+   product-reqs/reqs
    product-reqs/arm64/reqs
    design-reqs/arm64/generic-timer
    design-reqs/arm64/sbsa-uart
diff --git a/docs/fusa/reqs/market-reqs/reqs.rst b/docs/fusa/reqs/market-reqs/reqs.rst
index f456788d96..2d297ecc13 100644
--- a/docs/fusa/reqs/market-reqs/reqs.rst
+++ b/docs/fusa/reqs/market-reqs/reqs.rst
@@ -47,3 +47,35 @@ Comments:
 
 Needs:
  - XenProd
+
+Static VM definition
+--------------------
+
+`XenMkt~static_vm_definition~1`
+
+Description:
+Xen shall support assigning peripherals to a domain.
+
+Rationale:
+
+Comments:
+Peripheral implies an iomem (input output memory) and/or interrupts.
+
+Needs:
+ - XenProd
+
+Multiple schedulers
+-------------------
+
+`XenMkt~multiple_schedulers~1`
+
+Description:
+Xen shall have configurable scheduling strategies of virtual cpus onto physical
+cpus.
+
+Rationale:
+
+Comments:
+
+Needs:
+ - XenProd
diff --git a/docs/fusa/reqs/product-reqs/arm64/reqs.rst b/docs/fusa/reqs/product-reqs/arm64/reqs.rst
index db91c47a02..ad5c1fdef7 100644
--- a/docs/fusa/reqs/product-reqs/arm64/reqs.rst
+++ b/docs/fusa/reqs/product-reqs/arm64/reqs.rst
@@ -6,7 +6,7 @@ Domain Creation And Runtime
 Emulated Timer
 --------------
 
-`XenProd~emulated_timer~1`
+`XenProd~arm64_emulated_timer~1`
 
 Description:
 Xen shall grant access to "Arm Generic Timer" for the domains.
@@ -25,7 +25,7 @@ Needs:
 Emulated UART
 -------------
 
-`XenProd~emulated_uart~1`
+`XenProd~arm64_emulated_uart~1`
 
 Description:
 Xen shall provide an "Arm SBSA UART" compliant device to the domains.
@@ -40,3 +40,127 @@ Covers:
 
 Needs:
  - XenSwdgn
+
+Linux kernel image
+------------------
+
+`XenProd~arm64_linux_kernel_image~1`
+
+Description:
+Xen shall create a domain with a binary containing header compliant with Arm64
+Linux kernel image [1].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Gzip Linux kernel image
+-----------------------
+
+`XenProd~arm64_linux_kernel_gzip_image~1`
+
+Description:
+Xen shall create a domain with a Gzip compressed binary containing header
+compliant with Arm64 Linux kernel image [1].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Kernel with uImage header
+-------------------------
+
+`XenProd~arm64_kernel_uimage~1`
+
+Description:
+Xen shall create a domain with a binary containing uImage header [2].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Gzip kernel with uImage header
+------------------------------
+
+`XenProd~arm64_gzip_kernel_uimage~1`
+
+Description:
+Xen shall create a domain with a Gzip compressed binary containing uImage
+header [2].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+SPIs
+----
+
+`XenProd~arm64_spis~1`
+
+Description:
+Xen shall assign hardware shared peripheral interrupts specified in the device
+tree to a domain.
+
+Rationale:
+
+Comments:
+Device tree is a data structure and language for describing hardware which is
+readable by an operating system [3].
+A shared peripheral interrupt is a peripheral interrupt that the Arm Generic
+Interrupt Controller's Distributor interface can route to any combination of
+processors [4].
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+Virtual PL011
+-------------
+
+`XenProd~arm64_virtual_pl011~1`
+
+Description:
+Xen shall provide an "Arm PL011 UART" compliant device to the domains.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~provide_console_domains~1`
+
+Needs:
+ - XenSwdgn
+
+| [1] https://github.com/torvalds/linux/blob/master/Documentation/arch/arm64/booting.rst
+| [2] https://source.denx.de/u-boot/u-boot/-/blob/master/include/image.h#L315
+| [3] https://docs.kernel.org/devicetree/usage-model.html
+| [4] https://developer.arm.com/documentation/ihi0048/a/Introduction/Terminology/Interrupt-types?lang=en
diff --git a/docs/fusa/reqs/product-reqs/reqs.rst b/docs/fusa/reqs/product-reqs/reqs.rst
new file mode 100644
index 0000000000..88d8de7811
--- /dev/null
+++ b/docs/fusa/reqs/product-reqs/reqs.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Domain Creation And Runtime
+===========================
+
+Kernel command line arguments
+-----------------------------
+
+`XenProd~kernel_cmd_line_args~1`
+
+Description:
+Xen shall pass kernel command line arguments to a domain via a device tree.
+
+Rationale:
+
+Comments:
+Device tree is a data structure and language for describing hardware which is
+readable by an operating system [1].
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Ramdisk
+-------
+
+`XenProd~ramdisk~1`
+
+Description:
+Xen shall provide the address of an initial ramdisk to a domain via a device
+tree.
+
+Rationale:
+
+Comments:
+The initial ramdisk is contained in memory.
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Memory
+------
+
+`XenProd~memory~1`
+
+Description:
+Xen shall create a domain with the amount of memory specified in a device tree.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+vCPUs
+-----
+
+`XenProd~vcpus~1`
+
+Description:
+A domain shall have a configurable number of virtual CPUs (1 to 128).
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Credit2 CPU pool scheduler
+--------------------------
+
+`XenProd~credit2_cpu_pool_scheduler~1`
+
+Description:
+Xen shall have a credit2 scheduler where a physical cpu can be shared between
+more than one virtual cpu.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~multiple_schedulers~1`
+
+Needs:
+ - XenSwdgn
+
+NUL CPU pool scheduler
+----------------------
+
+`XenProd~nul_cpu_pool_scheduler~1`
+
+Description:
+Xen shall have a nul scheduler where the domain virtual cpu is always running on
+its dedicated physical cpu.
+
+Rationale:
+
+Comments:
+A NUL CPU pool scheduler maps a virtual cpu to a unique physical cpu.
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~multiple_schedulers~1`
+
+Needs:
+ - XenSwdgn
+
+Assign iomem
+------------
+
+`XenProd~assign_iomem~1`
+
+Description:
+Xen shall support assigning pages of iomem (address and size aligned to a page)
+to a domain.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+Forward interrupts
+------------------
+
+`XenProd~forward_irqs~1`
+
+Description:
+Xen shall support forwarding hardware interrupts to a domain.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+| [1] https://docs.kernel.org/devicetree/usage-model.html
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: Fully initialise struct membanks_hdr fields
Message-Id: <E1tW9WA-00BD6x-0i@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 07:33:18 +0000

commit b8f80aca12364e58c02ad67adbde6099391bc080
Author:     Luca Fancellu <luca.fancellu@arm.com>
AuthorDate: Thu Jan 9 13:02:04 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu Jan 9 17:37:58 2025 +0100

    xen/arm: Fully initialise struct membanks_hdr fields
    
    Commit a14593e3995a ("xen/device-tree: Allow region overlapping with
    /memreserve/ ranges") introduced a type in the 'struct membanks_hdr'
    but forgot to update the 'struct kernel_info' initialiser, while
    it doesn't lead to failures because the field is not currently
    used while managing kernel_info structures, it's good to have it
    for completeness.
    
    There are other instance of structures using 'struct membanks_hdr'
    that are dynamically allocated and don't fully initialise these
    fields, provide a static inline helper for that.
    
    Fixes: a14593e3995a ("xen/device-tree: Allow region overlapping with /memreserve/ ranges")
    Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/arm/domain_build.c       | 13 ++++---------
 xen/arch/arm/include/asm/kernel.h |  5 ++++-
 xen/arch/arm/static-shmem.c       |  3 ++-
 xen/include/xen/bootfdt.h         | 16 ++++++++++++++++
 4 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index b072a16249..7b47abade1 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1039,7 +1039,7 @@ void __init allocate_memory(struct domain *d, struct kernel_info *kinfo)
      */
     if ( is_hardware_domain(d) )
     {
-        struct membanks *gnttab = xzalloc_flex_struct(struct membanks, bank, 1);
+        struct membanks *gnttab = membanks_xzalloc(1, MEMORY);
         /*
          * Exclude the following regions:
          * 1) Remove reserved memory
@@ -1057,13 +1057,10 @@ void __init allocate_memory(struct domain *d, struct kernel_info *kinfo)
         gnttab->bank[0].start = kinfo->gnttab_start;
         gnttab->bank[0].size = kinfo->gnttab_size;
 
-        hwdom_free_mem = xzalloc_flex_struct(struct membanks, bank,
-                                             NR_MEM_BANKS);
+        hwdom_free_mem = membanks_xzalloc(NR_MEM_BANKS, MEMORY);
         if ( !hwdom_free_mem )
             goto fail;
 
-        hwdom_free_mem->max_banks = NR_MEM_BANKS;
-
         if ( find_unallocated_memory(kinfo, mem_banks, ARRAY_SIZE(mem_banks),
                                      hwdom_free_mem, add_hwdom_free_regions) )
             goto fail;
@@ -1293,7 +1290,7 @@ static int __init find_host_extended_regions(const struct kernel_info *kinfo,
                                              struct membanks *ext_regions)
 {
     int res;
-    struct membanks *gnttab = xzalloc_flex_struct(struct membanks, bank, 1);
+    struct membanks *gnttab = membanks_xzalloc(1, MEMORY);
 
     /*
      * Exclude the following regions:
@@ -1374,12 +1371,10 @@ int __init make_hypervisor_node(struct domain *d,
     }
     else
     {
-        ext_regions = xzalloc_flex_struct(struct membanks, bank, NR_MEM_BANKS);
+        ext_regions = membanks_xzalloc(NR_MEM_BANKS, MEMORY);
         if ( !ext_regions )
             return -ENOMEM;
 
-        ext_regions->max_banks = NR_MEM_BANKS;
-
         if ( domain_use_host_layout(d) )
         {
             if ( !is_iommu_enabled(d) )
diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h
index 7e6e3c82a4..de3f945ae5 100644
--- a/xen/arch/arm/include/asm/kernel.h
+++ b/xen/arch/arm/include/asm/kernel.h
@@ -92,7 +92,9 @@ kernel_info_get_mem_const(const struct kernel_info *kinfo)
 }
 
 #ifdef CONFIG_STATIC_SHM
-#define KERNEL_INFO_SHM_MEM_INIT .shm_mem.common.max_banks = NR_SHMEM_BANKS,
+#define KERNEL_INFO_SHM_MEM_INIT                \
+    .shm_mem.common.max_banks = NR_SHMEM_BANKS, \
+    .shm_mem.common.type = STATIC_SHARED_MEMORY,
 #else
 #define KERNEL_INFO_SHM_MEM_INIT
 #endif
@@ -100,6 +102,7 @@ kernel_info_get_mem_const(const struct kernel_info *kinfo)
 #define KERNEL_INFO_INIT                        \
 {                                               \
     .mem.common.max_banks = NR_MEM_BANKS,       \
+    .mem.common.type = MEMORY,                  \
     KERNEL_INFO_SHM_MEM_INIT                    \
 }
 
diff --git a/xen/arch/arm/static-shmem.c b/xen/arch/arm/static-shmem.c
index 66088a4267..8f87154c35 100644
--- a/xen/arch/arm/static-shmem.c
+++ b/xen/arch/arm/static-shmem.c
@@ -20,7 +20,8 @@ static struct {
     struct membanks_hdr common;
     struct membank bank[NR_SHMEM_BANKS];
 } shm_heap_banks __initdata = {
-    .common.max_banks = NR_SHMEM_BANKS
+    .common.max_banks = NR_SHMEM_BANKS,
+    .common.type = STATIC_SHARED_MEMORY
 };
 
 static inline struct membanks *get_shmem_heap_banks(void)
diff --git a/xen/include/xen/bootfdt.h b/xen/include/xen/bootfdt.h
index c8bbfd8979..80a90e53c0 100644
--- a/xen/include/xen/bootfdt.h
+++ b/xen/include/xen/bootfdt.h
@@ -4,6 +4,7 @@
 #include <xen/types.h>
 #include <xen/kernel.h>
 #include <xen/macros.h>
+#include <xen/xmalloc.h>
 
 #define MIN_FDT_ALIGN 8
 
@@ -219,4 +220,19 @@ static inline struct shmem_membank_extra *bootinfo_get_shmem_extra(void)
 }
 #endif
 
+static inline struct membanks *membanks_xzalloc(unsigned int nr,
+                                                enum region_type type)
+{
+    struct membanks *banks = xzalloc_flex_struct(struct membanks, bank, nr);
+
+    if ( !banks )
+        goto out;
+
+    banks->max_banks = nr;
+    banks->type = type;
+
+ out:
+    return banks;
+}
+
 #endif /* XEN_BOOTFDT_H */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs: fusa: Add dom0less domain configuration requirements
Message-Id: <E1tWAHJ-00BHnP-1s@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 08:22:01 +0000

commit b9f9b396452aa5fecbe87d8aedbe3c075cf4116c
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed Jan 8 17:03:04 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu Jan 9 17:37:58 2025 +0100

    docs: fusa: Add dom0less domain configuration requirements
    
    Add requirements for dom0less domain creation.
    
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 docs/fusa/reqs/index.rst                   |   1 +
 docs/fusa/reqs/market-reqs/reqs.rst        |  32 ++++++
 docs/fusa/reqs/product-reqs/arm64/reqs.rst | 128 ++++++++++++++++++++++-
 docs/fusa/reqs/product-reqs/reqs.rst       | 160 +++++++++++++++++++++++++++++
 4 files changed, 319 insertions(+), 2 deletions(-)

diff --git a/docs/fusa/reqs/index.rst b/docs/fusa/reqs/index.rst
index 8a4dae6fb2..1088a51d52 100644
--- a/docs/fusa/reqs/index.rst
+++ b/docs/fusa/reqs/index.rst
@@ -8,6 +8,7 @@ Requirements documentation
 
    intro
    market-reqs/reqs
+   product-reqs/reqs
    product-reqs/arm64/reqs
    design-reqs/arm64/generic-timer
    design-reqs/arm64/sbsa-uart
diff --git a/docs/fusa/reqs/market-reqs/reqs.rst b/docs/fusa/reqs/market-reqs/reqs.rst
index f456788d96..2d297ecc13 100644
--- a/docs/fusa/reqs/market-reqs/reqs.rst
+++ b/docs/fusa/reqs/market-reqs/reqs.rst
@@ -47,3 +47,35 @@ Comments:
 
 Needs:
  - XenProd
+
+Static VM definition
+--------------------
+
+`XenMkt~static_vm_definition~1`
+
+Description:
+Xen shall support assigning peripherals to a domain.
+
+Rationale:
+
+Comments:
+Peripheral implies an iomem (input output memory) and/or interrupts.
+
+Needs:
+ - XenProd
+
+Multiple schedulers
+-------------------
+
+`XenMkt~multiple_schedulers~1`
+
+Description:
+Xen shall have configurable scheduling strategies of virtual cpus onto physical
+cpus.
+
+Rationale:
+
+Comments:
+
+Needs:
+ - XenProd
diff --git a/docs/fusa/reqs/product-reqs/arm64/reqs.rst b/docs/fusa/reqs/product-reqs/arm64/reqs.rst
index db91c47a02..ad5c1fdef7 100644
--- a/docs/fusa/reqs/product-reqs/arm64/reqs.rst
+++ b/docs/fusa/reqs/product-reqs/arm64/reqs.rst
@@ -6,7 +6,7 @@ Domain Creation And Runtime
 Emulated Timer
 --------------
 
-`XenProd~emulated_timer~1`
+`XenProd~arm64_emulated_timer~1`
 
 Description:
 Xen shall grant access to "Arm Generic Timer" for the domains.
@@ -25,7 +25,7 @@ Needs:
 Emulated UART
 -------------
 
-`XenProd~emulated_uart~1`
+`XenProd~arm64_emulated_uart~1`
 
 Description:
 Xen shall provide an "Arm SBSA UART" compliant device to the domains.
@@ -40,3 +40,127 @@ Covers:
 
 Needs:
  - XenSwdgn
+
+Linux kernel image
+------------------
+
+`XenProd~arm64_linux_kernel_image~1`
+
+Description:
+Xen shall create a domain with a binary containing header compliant with Arm64
+Linux kernel image [1].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Gzip Linux kernel image
+-----------------------
+
+`XenProd~arm64_linux_kernel_gzip_image~1`
+
+Description:
+Xen shall create a domain with a Gzip compressed binary containing header
+compliant with Arm64 Linux kernel image [1].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Kernel with uImage header
+-------------------------
+
+`XenProd~arm64_kernel_uimage~1`
+
+Description:
+Xen shall create a domain with a binary containing uImage header [2].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Gzip kernel with uImage header
+------------------------------
+
+`XenProd~arm64_gzip_kernel_uimage~1`
+
+Description:
+Xen shall create a domain with a Gzip compressed binary containing uImage
+header [2].
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+SPIs
+----
+
+`XenProd~arm64_spis~1`
+
+Description:
+Xen shall assign hardware shared peripheral interrupts specified in the device
+tree to a domain.
+
+Rationale:
+
+Comments:
+Device tree is a data structure and language for describing hardware which is
+readable by an operating system [3].
+A shared peripheral interrupt is a peripheral interrupt that the Arm Generic
+Interrupt Controller's Distributor interface can route to any combination of
+processors [4].
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+Virtual PL011
+-------------
+
+`XenProd~arm64_virtual_pl011~1`
+
+Description:
+Xen shall provide an "Arm PL011 UART" compliant device to the domains.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~provide_console_domains~1`
+
+Needs:
+ - XenSwdgn
+
+| [1] https://github.com/torvalds/linux/blob/master/Documentation/arch/arm64/booting.rst
+| [2] https://source.denx.de/u-boot/u-boot/-/blob/master/include/image.h#L315
+| [3] https://docs.kernel.org/devicetree/usage-model.html
+| [4] https://developer.arm.com/documentation/ihi0048/a/Introduction/Terminology/Interrupt-types?lang=en
diff --git a/docs/fusa/reqs/product-reqs/reqs.rst b/docs/fusa/reqs/product-reqs/reqs.rst
new file mode 100644
index 0000000000..88d8de7811
--- /dev/null
+++ b/docs/fusa/reqs/product-reqs/reqs.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Domain Creation And Runtime
+===========================
+
+Kernel command line arguments
+-----------------------------
+
+`XenProd~kernel_cmd_line_args~1`
+
+Description:
+Xen shall pass kernel command line arguments to a domain via a device tree.
+
+Rationale:
+
+Comments:
+Device tree is a data structure and language for describing hardware which is
+readable by an operating system [1].
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Ramdisk
+-------
+
+`XenProd~ramdisk~1`
+
+Description:
+Xen shall provide the address of an initial ramdisk to a domain via a device
+tree.
+
+Rationale:
+
+Comments:
+The initial ramdisk is contained in memory.
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Memory
+------
+
+`XenProd~memory~1`
+
+Description:
+Xen shall create a domain with the amount of memory specified in a device tree.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+vCPUs
+-----
+
+`XenProd~vcpus~1`
+
+Description:
+A domain shall have a configurable number of virtual CPUs (1 to 128).
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+
+Needs:
+ - XenSwdgn
+
+Credit2 CPU pool scheduler
+--------------------------
+
+`XenProd~credit2_cpu_pool_scheduler~1`
+
+Description:
+Xen shall have a credit2 scheduler where a physical cpu can be shared between
+more than one virtual cpu.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~multiple_schedulers~1`
+
+Needs:
+ - XenSwdgn
+
+NUL CPU pool scheduler
+----------------------
+
+`XenProd~nul_cpu_pool_scheduler~1`
+
+Description:
+Xen shall have a nul scheduler where the domain virtual cpu is always running on
+its dedicated physical cpu.
+
+Rationale:
+
+Comments:
+A NUL CPU pool scheduler maps a virtual cpu to a unique physical cpu.
+
+Covers:
+ - `XenMkt~run_arm64_domains~1`
+ - `XenMkt~multiple_schedulers~1`
+
+Needs:
+ - XenSwdgn
+
+Assign iomem
+------------
+
+`XenProd~assign_iomem~1`
+
+Description:
+Xen shall support assigning pages of iomem (address and size aligned to a page)
+to a domain.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+Forward interrupts
+------------------
+
+`XenProd~forward_irqs~1`
+
+Description:
+Xen shall support forwarding hardware interrupts to a domain.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~static_vm_definition~1`
+
+Needs:
+ - XenSwdgn
+
+| [1] https://docs.kernel.org/devicetree/usage-model.html
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: Fully initialise struct membanks_hdr fields
Message-Id: <E1tWAHT-00BHoR-2P@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 08:22:11 +0000

commit b8f80aca12364e58c02ad67adbde6099391bc080
Author:     Luca Fancellu <luca.fancellu@arm.com>
AuthorDate: Thu Jan 9 13:02:04 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu Jan 9 17:37:58 2025 +0100

    xen/arm: Fully initialise struct membanks_hdr fields
    
    Commit a14593e3995a ("xen/device-tree: Allow region overlapping with
    /memreserve/ ranges") introduced a type in the 'struct membanks_hdr'
    but forgot to update the 'struct kernel_info' initialiser, while
    it doesn't lead to failures because the field is not currently
    used while managing kernel_info structures, it's good to have it
    for completeness.
    
    There are other instance of structures using 'struct membanks_hdr'
    that are dynamically allocated and don't fully initialise these
    fields, provide a static inline helper for that.
    
    Fixes: a14593e3995a ("xen/device-tree: Allow region overlapping with /memreserve/ ranges")
    Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/arm/domain_build.c       | 13 ++++---------
 xen/arch/arm/include/asm/kernel.h |  5 ++++-
 xen/arch/arm/static-shmem.c       |  3 ++-
 xen/include/xen/bootfdt.h         | 16 ++++++++++++++++
 4 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index b072a16249..7b47abade1 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1039,7 +1039,7 @@ void __init allocate_memory(struct domain *d, struct kernel_info *kinfo)
      */
     if ( is_hardware_domain(d) )
     {
-        struct membanks *gnttab = xzalloc_flex_struct(struct membanks, bank, 1);
+        struct membanks *gnttab = membanks_xzalloc(1, MEMORY);
         /*
          * Exclude the following regions:
          * 1) Remove reserved memory
@@ -1057,13 +1057,10 @@ void __init allocate_memory(struct domain *d, struct kernel_info *kinfo)
         gnttab->bank[0].start = kinfo->gnttab_start;
         gnttab->bank[0].size = kinfo->gnttab_size;
 
-        hwdom_free_mem = xzalloc_flex_struct(struct membanks, bank,
-                                             NR_MEM_BANKS);
+        hwdom_free_mem = membanks_xzalloc(NR_MEM_BANKS, MEMORY);
         if ( !hwdom_free_mem )
             goto fail;
 
-        hwdom_free_mem->max_banks = NR_MEM_BANKS;
-
         if ( find_unallocated_memory(kinfo, mem_banks, ARRAY_SIZE(mem_banks),
                                      hwdom_free_mem, add_hwdom_free_regions) )
             goto fail;
@@ -1293,7 +1290,7 @@ static int __init find_host_extended_regions(const struct kernel_info *kinfo,
                                              struct membanks *ext_regions)
 {
     int res;
-    struct membanks *gnttab = xzalloc_flex_struct(struct membanks, bank, 1);
+    struct membanks *gnttab = membanks_xzalloc(1, MEMORY);
 
     /*
      * Exclude the following regions:
@@ -1374,12 +1371,10 @@ int __init make_hypervisor_node(struct domain *d,
     }
     else
     {
-        ext_regions = xzalloc_flex_struct(struct membanks, bank, NR_MEM_BANKS);
+        ext_regions = membanks_xzalloc(NR_MEM_BANKS, MEMORY);
         if ( !ext_regions )
             return -ENOMEM;
 
-        ext_regions->max_banks = NR_MEM_BANKS;
-
         if ( domain_use_host_layout(d) )
         {
             if ( !is_iommu_enabled(d) )
diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h
index 7e6e3c82a4..de3f945ae5 100644
--- a/xen/arch/arm/include/asm/kernel.h
+++ b/xen/arch/arm/include/asm/kernel.h
@@ -92,7 +92,9 @@ kernel_info_get_mem_const(const struct kernel_info *kinfo)
 }
 
 #ifdef CONFIG_STATIC_SHM
-#define KERNEL_INFO_SHM_MEM_INIT .shm_mem.common.max_banks = NR_SHMEM_BANKS,
+#define KERNEL_INFO_SHM_MEM_INIT                \
+    .shm_mem.common.max_banks = NR_SHMEM_BANKS, \
+    .shm_mem.common.type = STATIC_SHARED_MEMORY,
 #else
 #define KERNEL_INFO_SHM_MEM_INIT
 #endif
@@ -100,6 +102,7 @@ kernel_info_get_mem_const(const struct kernel_info *kinfo)
 #define KERNEL_INFO_INIT                        \
 {                                               \
     .mem.common.max_banks = NR_MEM_BANKS,       \
+    .mem.common.type = MEMORY,                  \
     KERNEL_INFO_SHM_MEM_INIT                    \
 }
 
diff --git a/xen/arch/arm/static-shmem.c b/xen/arch/arm/static-shmem.c
index 66088a4267..8f87154c35 100644
--- a/xen/arch/arm/static-shmem.c
+++ b/xen/arch/arm/static-shmem.c
@@ -20,7 +20,8 @@ static struct {
     struct membanks_hdr common;
     struct membank bank[NR_SHMEM_BANKS];
 } shm_heap_banks __initdata = {
-    .common.max_banks = NR_SHMEM_BANKS
+    .common.max_banks = NR_SHMEM_BANKS,
+    .common.type = STATIC_SHARED_MEMORY
 };
 
 static inline struct membanks *get_shmem_heap_banks(void)
diff --git a/xen/include/xen/bootfdt.h b/xen/include/xen/bootfdt.h
index c8bbfd8979..80a90e53c0 100644
--- a/xen/include/xen/bootfdt.h
+++ b/xen/include/xen/bootfdt.h
@@ -4,6 +4,7 @@
 #include <xen/types.h>
 #include <xen/kernel.h>
 #include <xen/macros.h>
+#include <xen/xmalloc.h>
 
 #define MIN_FDT_ALIGN 8
 
@@ -219,4 +220,19 @@ static inline struct shmem_membank_extra *bootinfo_get_shmem_extra(void)
 }
 #endif
 
+static inline struct membanks *membanks_xzalloc(unsigned int nr,
+                                                enum region_type type)
+{
+    struct membanks *banks = xzalloc_flex_struct(struct membanks, bank, nr);
+
+    if ( !banks )
+        goto out;
+
+    banks->max_banks = nr;
+    banks->type = type;
+
+ out:
+    return banks;
+}
+
 #endif /* XEN_BOOTFDT_H */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] Config.mk: Pin QEMU_UPSTREAM_REVISION
Message-Id: <E1tWH0V-00BzNQ-0c@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 15:33:07 +0000

commit 3604d15d1acd03e8b68e270c05317e86a7efae4d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 9 15:10:01 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri Jan 10 15:26:41 2025 +0000

    Config.mk: Pin QEMU_UPSTREAM_REVISION
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 Config.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Config.mk b/Config.mk
index fa0414055b..13aa6ce3ab 100644
--- a/Config.mk
+++ b/Config.mk
@@ -221,7 +221,7 @@ OVMF_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/ovmf.git
 OVMF_UPSTREAM_REVISION ?= ba91d0292e593df8528b66f99c1b0b14fadc8e16
 
 QEMU_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/qemu-xen.git
-QEMU_UPSTREAM_REVISION ?= master
+QEMU_UPSTREAM_REVISION ?= 3fdb3cd3a27a22a050c7d27126a24807a7a45745
 
 MINIOS_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/mini-os.git
 MINIOS_UPSTREAM_REVISION ?= 6d5159e8410be16a47433bac1627e63f8adc7cd9
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] Update Xen version to 4.20-rc
Message-Id: <E1tWH0f-00BzNt-13@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 15:33:17 +0000

commit 19730dbb3fd8078743d5196bd7fc32f3765557ad
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 9 15:06:34 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri Jan 10 15:26:41 2025 +0000

    Update Xen version to 4.20-rc
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 README       | 16 ++++++++--------
 SUPPORT.md   |  2 +-
 xen/Makefile |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/README b/README
index 72f6b0fcde..373885523c 100644
--- a/README
+++ b/README
@@ -1,11 +1,11 @@
-############################################################
-__  __                                _        _     _
-\ \/ /___ _ __        _   _ _ __  ___| |_ __ _| |__ | | ___
- \  // _ \ '_ \ _____| | | | '_ \/ __| __/ _` | '_ \| |/ _ \
- /  \  __/ | | |_____| |_| | | | \__ \ || (_| | |_) | |  __/
-/_/\_\___|_| |_|      \__,_|_| |_|___/\__\__,_|_.__/|_|\___|
-
-############################################################
+#####################################################
+__  __            _  _    ____   ___
+\ \/ /___ _ __   | || |  |___ \ / _ \       _ __ ___
+ \  // _ \ '_ \  | || |_   __) | | | |_____| '__/ __|
+ /  \  __/ | | | |__   _| / __/| |_| |_____| | | (__
+/_/\_\___|_| |_|    |_|(_)_____|\___/      |_|  \___|
+
+#####################################################
 
 https://www.xen.org/
 
diff --git a/SUPPORT.md b/SUPPORT.md
index 54c78b722d..2bc5bd81ee 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -9,7 +9,7 @@ for the definitions of the support status levels etc.
 
 # Release Support
 
-    Xen-Version: 4.20-unstable
+    Xen-Version: 4.20-rc
     Initial-Release: n/a
     Supported-Until: TBD
     Security-Support-Until: Unreleased - not yet security-supported
diff --git a/xen/Makefile b/xen/Makefile
index 2e1a925c84..838e61f4e9 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -6,7 +6,7 @@ this-makefile := $(call lastword,$(MAKEFILE_LIST))
 # All other places this is stored (eg. compile.h) should be autogenerated.
 export XEN_VERSION       = 4
 export XEN_SUBVERSION    = 20
-export XEN_EXTRAVERSION ?= -unstable$(XEN_VENDORVERSION)
+export XEN_EXTRAVERSION ?= -rc$(XEN_VENDORVERSION)
 export XEN_FULLVERSION   = $(XEN_VERSION).$(XEN_SUBVERSION)$(XEN_EXTRAVERSION)
 -include xen-version
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] Config.mk: Pin QEMU_UPSTREAM_REVISION
Message-Id: <E1tWIXF-00CHLI-1Y@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 17:11:01 +0000

commit 3604d15d1acd03e8b68e270c05317e86a7efae4d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 9 15:10:01 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri Jan 10 15:26:41 2025 +0000

    Config.mk: Pin QEMU_UPSTREAM_REVISION
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 Config.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Config.mk b/Config.mk
index fa0414055b..13aa6ce3ab 100644
--- a/Config.mk
+++ b/Config.mk
@@ -221,7 +221,7 @@ OVMF_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/ovmf.git
 OVMF_UPSTREAM_REVISION ?= ba91d0292e593df8528b66f99c1b0b14fadc8e16
 
 QEMU_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/qemu-xen.git
-QEMU_UPSTREAM_REVISION ?= master
+QEMU_UPSTREAM_REVISION ?= 3fdb3cd3a27a22a050c7d27126a24807a7a45745
 
 MINIOS_UPSTREAM_URL ?= https://xenbits.xen.org/git-http/mini-os.git
 MINIOS_UPSTREAM_REVISION ?= 6d5159e8410be16a47433bac1627e63f8adc7cd9
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] Update Xen version to 4.20-rc
Message-Id: <E1tWIXP-00CHM5-28@xenbits.xenproject.org>
Date: Fri, 10 Jan 2025 17:11:11 +0000

commit 19730dbb3fd8078743d5196bd7fc32f3765557ad
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Thu Jan 9 15:06:34 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri Jan 10 15:26:41 2025 +0000

    Update Xen version to 4.20-rc
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 README       | 16 ++++++++--------
 SUPPORT.md   |  2 +-
 xen/Makefile |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/README b/README
index 72f6b0fcde..373885523c 100644
--- a/README
+++ b/README
@@ -1,11 +1,11 @@
-############################################################
-__  __                                _        _     _
-\ \/ /___ _ __        _   _ _ __  ___| |_ __ _| |__ | | ___
- \  // _ \ '_ \ _____| | | | '_ \/ __| __/ _` | '_ \| |/ _ \
- /  \  __/ | | |_____| |_| | | | \__ \ || (_| | |_) | |  __/
-/_/\_\___|_| |_|      \__,_|_| |_|___/\__\__,_|_.__/|_|\___|
-
-############################################################
+#####################################################
+__  __            _  _    ____   ___
+\ \/ /___ _ __   | || |  |___ \ / _ \       _ __ ___
+ \  // _ \ '_ \  | || |_   __) | | | |_____| '__/ __|
+ /  \  __/ | | | |__   _| / __/| |_| |_____| | | (__
+/_/\_\___|_| |_|    |_|(_)_____|\___/      |_|  \___|
+
+#####################################################
 
 https://www.xen.org/
 
diff --git a/SUPPORT.md b/SUPPORT.md
index 54c78b722d..2bc5bd81ee 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -9,7 +9,7 @@ for the definitions of the support status levels etc.
 
 # Release Support
 
-    Xen-Version: 4.20-unstable
+    Xen-Version: 4.20-rc
     Initial-Release: n/a
     Supported-Until: TBD
     Security-Support-Until: Unreleased - not yet security-supported
diff --git a/xen/Makefile b/xen/Makefile
index 2e1a925c84..838e61f4e9 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -6,7 +6,7 @@ this-makefile := $(call lastword,$(MAKEFILE_LIST))
 # All other places this is stored (eg. compile.h) should be autogenerated.
 export XEN_VERSION       = 4
 export XEN_SUBVERSION    = 20
-export XEN_EXTRAVERSION ?= -unstable$(XEN_VENDORVERSION)
+export XEN_EXTRAVERSION ?= -rc$(XEN_VENDORVERSION)
 export XEN_FULLVERSION   = $(XEN_VERSION).$(XEN_SUBVERSION)$(XEN_EXTRAVERSION)
 -include xen-version
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: Add an x86_64 Clang Randconfig job
Message-Id: <E1tXLfg-001WzJ-2P@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 14:44:04 +0000

commit 2ab44af38fb8d8c245d67126f041fadf4a7de33e
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri Jan 10 16:02:17 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:35:22 2025 +0000

    CI: Add an x86_64 Clang Randconfig job
    
    This was recently identified as a hole in testing.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Alejandro Vallejo <alejandro.vallejo@cloud.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/gitlab-ci/build.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 3abd2a0c65..cb84f379b7 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -551,6 +551,12 @@ debian-12-x86_64-clang:
   variables:
     CONTAINER: debian:12-x86_64
 
+debian-12-x86_64-clang-randconfig:
+  extends: .clang-x86-64-build
+  variables:
+    CONTAINER: debian:12-x86_64
+    RANDCONFIG: y
+
 debian-12-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs/Makefile: Add ppc and riscv to DOC_ARCHES
Message-Id: <E1tXLfq-001X0j-2l@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 14:44:14 +0000

commit 5dd85073d177f0590b68d59df6fba18085b5b313
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Fri Jan 10 22:19:03 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:36:09 2025 +0000

    docs/Makefile: Add ppc and riscv to DOC_ARCHES
    
    Not having ppc and riscv included in DOC_ARCHES causes "multiple
    definitions of ..." message on documentation build, similar to the
    example shown below:
    
    include/public/arch-ppc.h:91: multiple definitions of Typedef
    vcpu_guest_core_regs_t: include/public/arch-arm.h:300
    include/public/arch-ppc.h:91: multiple definitions of Typedef
    vcpu_guest_core_regs_t: include/public/arch-ppc.h:85
    
    It can also make the generated html documentation link to the header
    files of another architecture. This is additionally a problem as it can
    randomly make the documentation build non-reproducible.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Makefile b/docs/Makefile
index b30cc619f8..9f8ba8acd9 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -5,7 +5,7 @@ include $(XEN_ROOT)/Config.mk
 VERSION		:= $(shell $(MAKE) -C $(XEN_ROOT)/xen --no-print-directory xenversion)
 DATE		:= $(shell date +%Y-%m-%d)
 
-DOC_ARCHES      := arm x86_32 x86_64
+DOC_ARCHES      := arm ppc riscv x86_32 x86_64
 MAN_SECTIONS    := 1 5 7 8
 
 # Documentation sources to build
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] build: Set DATE to SOURCE_DATE_EPOCH if available
Message-Id: <E1tXLg0-001X2E-36@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 14:44:24 +0000

commit 8aaf5dc2c94bec5e27071f22cb8bc31c40e6d3f0
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Mon Dec 30 22:00:30 2024 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:51:42 2025 +0000

    build: Set DATE to SOURCE_DATE_EPOCH if available
    
    Use the solution described in [1] to provide a wrapper to the 'date'
    command that uses SOURCE_DATE_EPOCH if available.  This is needed for
    reproducible builds.
    
    The -d "@..." syntax was introduced in GNU date about 2005 (but only
    added to the docuemntation in 2011), so I assume a version supporting
    this syntax is available, if SOURCE_DATE_EPOCH is defined. If
    SOURCE_DATE_EPOCH is not defined, nothing changes with respect to the
    current behavior.
    
    Update all users of 'date' in the tree to use the new wrapper.
    
    [1] https://reproducible-builds.org/docs/source-date-epoch/
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 Config.mk                         |  8 ++++++++
 docs/Makefile                     |  2 +-
 tools/firmware/hvmloader/Makefile |  2 +-
 tools/firmware/vgabios/Makefile   |  5 ++++-
 xen/Makefile                      | 15 +++++++++------
 5 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/Config.mk b/Config.mk
index 13aa6ce3ab..1eb6ed04fe 100644
--- a/Config.mk
+++ b/Config.mk
@@ -141,6 +141,14 @@ export XEN_HAS_BUILD_ID=y
 build_id_linker := --build-id=sha1
 endif
 
+# Wrap date(1) to use SOURCE_DATE_EPOCH if set the environment.
+# See https://reproducible-builds.org/docs/source-date-epoch/
+ifdef SOURCE_DATE_EPOCH
+date = $(shell LC_ALL=C date -u -d "@$(SOURCE_DATE_EPOCH)" $(1) 2>/dev/null || LC_ALL=C date -u -r "$(SOURCE_DATE_EPOCH)" $(1) 2>/dev/null || LC_ALL=C date -u $(1))
+else
+date = $(shell LC_ALL=C date $(1))
+endif
+
 define buildmakevars2shellvars
     export PREFIX="$(prefix)";                                            \
     export XEN_SCRIPT_DIR="$(XEN_SCRIPT_DIR)";                            \
diff --git a/docs/Makefile b/docs/Makefile
index 9f8ba8acd9..37776d303c 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -3,7 +3,7 @@ include $(XEN_ROOT)/Config.mk
 -include $(XEN_ROOT)/config/Docs.mk
 
 VERSION		:= $(shell $(MAKE) -C $(XEN_ROOT)/xen --no-print-directory xenversion)
-DATE		:= $(shell date +%Y-%m-%d)
+DATE		:= $(call date,"+%Y-%m-%d")
 
 DOC_ARCHES      := arm ppc riscv x86_32 x86_64
 MAN_SECTIONS    := 1 5 7 8
diff --git a/tools/firmware/hvmloader/Makefile b/tools/firmware/hvmloader/Makefile
index c7bc400657..cc5dc00498 100644
--- a/tools/firmware/hvmloader/Makefile
+++ b/tools/firmware/hvmloader/Makefile
@@ -23,7 +23,7 @@ include $(XEN_ROOT)/tools/firmware/Rules.mk
 ld-option = $(shell if $(LD) -v $(1) >/dev/null 2>&1; then echo y; else echo n; fi)
 
 # SMBIOS spec requires format mm/dd/yyyy
-SMBIOS_REL_DATE ?= $(shell date +%m/%d/%Y)
+SMBIOS_REL_DATE ?= $(call date,"+%m/%d/%Y")
 
 CFLAGS += $(CFLAGS_xeninclude) -fno-pic -mregparm=3
 
diff --git a/tools/firmware/vgabios/Makefile b/tools/firmware/vgabios/Makefile
index 3284812fde..db5a2624be 100644
--- a/tools/firmware/vgabios/Makefile
+++ b/tools/firmware/vgabios/Makefile
@@ -1,3 +1,6 @@
+XEN_ROOT = $(CURDIR)/../../..
+include $(XEN_ROOT)/Config.mk
+
 CC      = gcc
 
 GCC = gcc
@@ -5,7 +8,7 @@ BCC = bcc
 AS86 = as86
 
 RELEASE = `pwd | sed "s-.*/--"`
-VGABIOS_REL_DATE ?= `date '+%d %b %Y'`
+VGABIOS_REL_DATE ?= $(call date,"+%d %b %Y")
 RELVERS = `pwd | sed "s-.*/--" | sed "s/vgabios//" | sed "s/-//"`
 
 VGABIOS_DATE = "-DVGABIOS_DATE=\"$(VGABIOS_REL_DATE)\""
diff --git a/xen/Makefile b/xen/Makefile
index 838e61f4e9..65b460e2b4 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -14,15 +14,11 @@ export XEN_WHOAMI	?= $(USER)
 ifeq ($(origin XEN_DOMAIN), undefined)
 export XEN_DOMAIN	:= $(shell ([ -x /bin/dnsdomainname ] && /bin/dnsdomainname) || ([ -x /bin/domainname ] && /bin/domainname || echo [unknown]))
 endif
-ifeq ($(origin XEN_BUILD_DATE), undefined)
-export XEN_BUILD_DATE	:= $(shell LC_ALL=C date)
-endif
-ifeq ($(origin XEN_BUILD_TIME), undefined)
-export XEN_BUILD_TIME	:= $(shell LC_ALL=C date +%T)
-endif
 ifeq ($(origin XEN_BUILD_HOST), undefined)
 export XEN_BUILD_HOST	:= $(shell hostname)
 endif
+# XEN_BUILD_DATE and XEN_BUILD_TIME are set further down, as they depend on
+# Config.mk for SOURCE_DATE_EPOCH handling.
 
 # Best effort attempt to find a python interpreter, defaulting to Python 3 if
 # available.  Fall back to just `python`.
@@ -250,6 +246,13 @@ SRCARCH := $(shell echo $(ARCH) | \
         -e 's/riscv.*/riscv/g' -e 's/ppc.*/ppc/g')
 export ARCH SRCARCH
 
+ifeq ($(origin XEN_BUILD_DATE), undefined)
+export XEN_BUILD_DATE	:= $(call date)
+endif
+ifeq ($(origin XEN_BUILD_TIME), undefined)
+export XEN_BUILD_TIME	:= $(call date,"+%T")
+endif
+
 export CONFIG_SHELL := $(SHELL)
 export CC CXX LD NM OBJCOPY OBJDUMP ADDR2LINE
 export YACC = $(if $(BISON),$(BISON),bison)
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: Add an x86_64 Clang Randconfig job
Message-Id: <E1tXNxt-001uaI-1n@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 17:11:01 +0000

commit 2ab44af38fb8d8c245d67126f041fadf4a7de33e
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri Jan 10 16:02:17 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:35:22 2025 +0000

    CI: Add an x86_64 Clang Randconfig job
    
    This was recently identified as a hole in testing.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Alejandro Vallejo <alejandro.vallejo@cloud.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/gitlab-ci/build.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 3abd2a0c65..cb84f379b7 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -551,6 +551,12 @@ debian-12-x86_64-clang:
   variables:
     CONTAINER: debian:12-x86_64
 
+debian-12-x86_64-clang-randconfig:
+  extends: .clang-x86-64-build
+  variables:
+    CONTAINER: debian:12-x86_64
+    RANDCONFIG: y
+
 debian-12-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs/Makefile: Add ppc and riscv to DOC_ARCHES
Message-Id: <E1tXNy3-001uan-28@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 17:11:11 +0000

commit 5dd85073d177f0590b68d59df6fba18085b5b313
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Fri Jan 10 22:19:03 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:36:09 2025 +0000

    docs/Makefile: Add ppc and riscv to DOC_ARCHES
    
    Not having ppc and riscv included in DOC_ARCHES causes "multiple
    definitions of ..." message on documentation build, similar to the
    example shown below:
    
    include/public/arch-ppc.h:91: multiple definitions of Typedef
    vcpu_guest_core_regs_t: include/public/arch-arm.h:300
    include/public/arch-ppc.h:91: multiple definitions of Typedef
    vcpu_guest_core_regs_t: include/public/arch-ppc.h:85
    
    It can also make the generated html documentation link to the header
    files of another architecture. This is additionally a problem as it can
    randomly make the documentation build non-reproducible.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Makefile b/docs/Makefile
index b30cc619f8..9f8ba8acd9 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -5,7 +5,7 @@ include $(XEN_ROOT)/Config.mk
 VERSION		:= $(shell $(MAKE) -C $(XEN_ROOT)/xen --no-print-directory xenversion)
 DATE		:= $(shell date +%Y-%m-%d)
 
-DOC_ARCHES      := arm x86_32 x86_64
+DOC_ARCHES      := arm ppc riscv x86_32 x86_64
 MAN_SECTIONS    := 1 5 7 8
 
 # Documentation sources to build
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] build: Set DATE to SOURCE_DATE_EPOCH if available
Message-Id: <E1tXNyD-001ubN-2R@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 17:11:21 +0000

commit 8aaf5dc2c94bec5e27071f22cb8bc31c40e6d3f0
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Mon Dec 30 22:00:30 2024 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 13:51:42 2025 +0000

    build: Set DATE to SOURCE_DATE_EPOCH if available
    
    Use the solution described in [1] to provide a wrapper to the 'date'
    command that uses SOURCE_DATE_EPOCH if available.  This is needed for
    reproducible builds.
    
    The -d "@..." syntax was introduced in GNU date about 2005 (but only
    added to the docuemntation in 2011), so I assume a version supporting
    this syntax is available, if SOURCE_DATE_EPOCH is defined. If
    SOURCE_DATE_EPOCH is not defined, nothing changes with respect to the
    current behavior.
    
    Update all users of 'date' in the tree to use the new wrapper.
    
    [1] https://reproducible-builds.org/docs/source-date-epoch/
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 Config.mk                         |  8 ++++++++
 docs/Makefile                     |  2 +-
 tools/firmware/hvmloader/Makefile |  2 +-
 tools/firmware/vgabios/Makefile   |  5 ++++-
 xen/Makefile                      | 15 +++++++++------
 5 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/Config.mk b/Config.mk
index 13aa6ce3ab..1eb6ed04fe 100644
--- a/Config.mk
+++ b/Config.mk
@@ -141,6 +141,14 @@ export XEN_HAS_BUILD_ID=y
 build_id_linker := --build-id=sha1
 endif
 
+# Wrap date(1) to use SOURCE_DATE_EPOCH if set the environment.
+# See https://reproducible-builds.org/docs/source-date-epoch/
+ifdef SOURCE_DATE_EPOCH
+date = $(shell LC_ALL=C date -u -d "@$(SOURCE_DATE_EPOCH)" $(1) 2>/dev/null || LC_ALL=C date -u -r "$(SOURCE_DATE_EPOCH)" $(1) 2>/dev/null || LC_ALL=C date -u $(1))
+else
+date = $(shell LC_ALL=C date $(1))
+endif
+
 define buildmakevars2shellvars
     export PREFIX="$(prefix)";                                            \
     export XEN_SCRIPT_DIR="$(XEN_SCRIPT_DIR)";                            \
diff --git a/docs/Makefile b/docs/Makefile
index 9f8ba8acd9..37776d303c 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -3,7 +3,7 @@ include $(XEN_ROOT)/Config.mk
 -include $(XEN_ROOT)/config/Docs.mk
 
 VERSION		:= $(shell $(MAKE) -C $(XEN_ROOT)/xen --no-print-directory xenversion)
-DATE		:= $(shell date +%Y-%m-%d)
+DATE		:= $(call date,"+%Y-%m-%d")
 
 DOC_ARCHES      := arm ppc riscv x86_32 x86_64
 MAN_SECTIONS    := 1 5 7 8
diff --git a/tools/firmware/hvmloader/Makefile b/tools/firmware/hvmloader/Makefile
index c7bc400657..cc5dc00498 100644
--- a/tools/firmware/hvmloader/Makefile
+++ b/tools/firmware/hvmloader/Makefile
@@ -23,7 +23,7 @@ include $(XEN_ROOT)/tools/firmware/Rules.mk
 ld-option = $(shell if $(LD) -v $(1) >/dev/null 2>&1; then echo y; else echo n; fi)
 
 # SMBIOS spec requires format mm/dd/yyyy
-SMBIOS_REL_DATE ?= $(shell date +%m/%d/%Y)
+SMBIOS_REL_DATE ?= $(call date,"+%m/%d/%Y")
 
 CFLAGS += $(CFLAGS_xeninclude) -fno-pic -mregparm=3
 
diff --git a/tools/firmware/vgabios/Makefile b/tools/firmware/vgabios/Makefile
index 3284812fde..db5a2624be 100644
--- a/tools/firmware/vgabios/Makefile
+++ b/tools/firmware/vgabios/Makefile
@@ -1,3 +1,6 @@
+XEN_ROOT = $(CURDIR)/../../..
+include $(XEN_ROOT)/Config.mk
+
 CC      = gcc
 
 GCC = gcc
@@ -5,7 +8,7 @@ BCC = bcc
 AS86 = as86
 
 RELEASE = `pwd | sed "s-.*/--"`
-VGABIOS_REL_DATE ?= `date '+%d %b %Y'`
+VGABIOS_REL_DATE ?= $(call date,"+%d %b %Y")
 RELVERS = `pwd | sed "s-.*/--" | sed "s/vgabios//" | sed "s/-//"`
 
 VGABIOS_DATE = "-DVGABIOS_DATE=\"$(VGABIOS_REL_DATE)\""
diff --git a/xen/Makefile b/xen/Makefile
index 838e61f4e9..65b460e2b4 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -14,15 +14,11 @@ export XEN_WHOAMI	?= $(USER)
 ifeq ($(origin XEN_DOMAIN), undefined)
 export XEN_DOMAIN	:= $(shell ([ -x /bin/dnsdomainname ] && /bin/dnsdomainname) || ([ -x /bin/domainname ] && /bin/domainname || echo [unknown]))
 endif
-ifeq ($(origin XEN_BUILD_DATE), undefined)
-export XEN_BUILD_DATE	:= $(shell LC_ALL=C date)
-endif
-ifeq ($(origin XEN_BUILD_TIME), undefined)
-export XEN_BUILD_TIME	:= $(shell LC_ALL=C date +%T)
-endif
 ifeq ($(origin XEN_BUILD_HOST), undefined)
 export XEN_BUILD_HOST	:= $(shell hostname)
 endif
+# XEN_BUILD_DATE and XEN_BUILD_TIME are set further down, as they depend on
+# Config.mk for SOURCE_DATE_EPOCH handling.
 
 # Best effort attempt to find a python interpreter, defaulting to Python 3 if
 # available.  Fall back to just `python`.
@@ -250,6 +246,13 @@ SRCARCH := $(shell echo $(ARCH) | \
         -e 's/riscv.*/riscv/g' -e 's/ppc.*/ppc/g')
 export ARCH SRCARCH
 
+ifeq ($(origin XEN_BUILD_DATE), undefined)
+export XEN_BUILD_DATE	:= $(call date)
+endif
+ifeq ($(origin XEN_BUILD_TIME), undefined)
+export XEN_BUILD_TIME	:= $(call date,"+%T")
+endif
+
 export CONFIG_SHELL := $(SHELL)
 export CC CXX LD NM OBJCOPY OBJDUMP ADDR2LINE
 export YACC = $(if $(BISON),$(BISON),bison)
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86: Rename _rsvd field to pw and move it to the bit 58
Message-Id: <E1tXO8a-001vy2-28@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 17:22:04 +0000

commit b94305d984fe469bd7c93025fb181f217202d0a5
Author:     Petr Beneš <w1benny@gmail.com>
AuthorDate: Thu Jan 2 17:13:27 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 16:50:29 2025 +0000

    x86: Rename _rsvd field to pw and move it to the bit 58
    
    The EPT Paging-write feature (when enabled by the
    TERTIARY_EXEC_EPT_PAGING_WRITE bit) uses bit 58 of the EPT entry to
    indicate that guest paging may update the page, even if the W access
    is not set.
    
    This patch is a preparation for the EPT Paging-write feature.
    
    Signed-off-by: Petr Beneš <w1benny@gmail.com>
    Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/include/asm/hvm/vmx/vmx.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
index f0ec459622..d920de96b7 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
@@ -34,8 +34,8 @@ typedef union {
                                EPT/VT-d usage */
         mfn         :   40, /* bits 51:12 - Machine physical frame number */
         sa_p2mt     :   6,  /* bits 57:52 - Software available 2 */
-        access      :   4,  /* bits 61:58 - p2m_access_t */
-        _rsvd       :   1,  /* bit 62 - reserved */
+        pw          :   1,  /* bit 58 - Paging-write access */
+        access      :   4,  /* bits 62:59 - p2m_access_t */
         suppress_ve :   1;  /* bit 63 - suppress #VE */
     };
     u64 epte;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86: Add Support for Paging-Write Feature
Message-Id: <E1tXO8k-001vzg-2W@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 17:22:14 +0000

commit ff10aa9d8f90cf18ff198581e83e8401f9e5d950
Author:     Petr Beneš <w1benny@gmail.com>
AuthorDate: Thu Jan 2 17:13:28 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 16:50:29 2025 +0000

    x86: Add Support for Paging-Write Feature
    
    This patch introduces a new XENMEM_access_r_pw permission.
    Functionally, it is similar to XENMEM_access_r, but for processors
    with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake
    and later, Xeon 4th Gen/Sappire Rapids and later), it also permits the
    CPU to write to the page during guest page-table walks (e.g., updating
    A/D bits) without triggering an EPT violation.
    
    This behavior works by both enabling the EPT paging-write feature and
    setting the EPT paging-write flag in the EPT leaf entry.
    
    This feature provides a significant performance boost for
    introspection tools that monitor guest page-table updates. Previously,
    every page-table modification by the guest—including routine updates
    like setting A/D bits—triggered an EPT violation, adding unnecessary
    overhead. The new XENMEM_access_r_pw permission allows these
    "uninteresting" updates to occur without EPT violations, improving
    efficiency.
    
    Additionally, this feature simplifies the handling of race conditions
    in scenarios where an introspection tool:
    
    - Sets an "invisible breakpoint" in the altp2m view for a function F.
    - Monitors guest page-table updates to track whether the page
      containing F is paged out.
    - Encounters a cleared Access (A) bit on the page containing F while
      the guest is about to execute the breakpoint.
    
    In the current implementation:
    
    - If xc_monitor_inguest_pagefault() is enabled, the introspection tool
      must emulate both the breakpoint and the setting of the Access bit.
    - If xc_monitor_inguest_pagefault() is disabled, Xen handles the EPT
      violation without notifying the introspection tool, setting the
      Access bit and emulating the instruction. However, Xen fetches the
      instruction from the default view instead of the altp2m view,
      potentially causing the breakpoint to be missed.
    
    With this patch, setting XENMEM_access_r_pw for monitored guest
    page-tables prevents EPT violations in these cases. This change
    enhances performance and reduces complexity for introspection tools,
    ensuring seamless breakpoint handling while tracking guest page-table
    updates.
    
    Signed-off-by: Petr Beneš <w1benny@gmail.com>
    Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/arm/mem_access.c               | 4 ++++
 xen/arch/arm/mmu/p2m.c                  | 1 +
 xen/arch/x86/hvm/hvm.c                  | 1 +
 xen/arch/x86/hvm/monitor.c              | 1 +
 xen/arch/x86/hvm/vmx/vmcs.c             | 4 +++-
 xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 3 +++
 xen/arch/x86/include/asm/p2m.h          | 1 +
 xen/arch/x86/mm/hap/nested_hap.c        | 3 +++
 xen/arch/x86/mm/mem_access.c            | 3 +++
 xen/arch/x86/mm/p2m-ept.c               | 4 ++++
 xen/include/public/memory.h             | 9 +++++++++
 xen/include/xen/mem_access.h            | 6 ++++++
 12 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c
index 0ec3462364..2af92bb402 100644
--- a/xen/arch/arm/mem_access.c
+++ b/xen/arch/arm/mem_access.c
@@ -32,6 +32,7 @@ static int __p2m_get_mem_access(struct domain *d, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -172,6 +173,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag,
             break;
         else
             goto err;
+    case XENMEM_access_r_pw:
     case XENMEM_access_rx2rw:
     case XENMEM_access_rx:
     case XENMEM_access_r:
@@ -253,6 +255,7 @@ bool p2m_mem_access_check(paddr_t gpa, vaddr_t gla, const struct npfec npfec)
         violation = npfec.read_access || npfec.insn_fetch;
         break;
     case XENMEM_access_r:
+    case XENMEM_access_r_pw:
         violation = npfec.write_access || npfec.insn_fetch;
         break;
     default:
@@ -361,6 +364,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c
index 28df6e5d03..7642dbc7c5 100644
--- a/xen/arch/arm/mmu/p2m.c
+++ b/xen/arch/arm/mmu/p2m.c
@@ -597,6 +597,7 @@ static void p2m_set_permission(lpae_t *e, p2m_type_t t, p2m_access_t a)
         e->p2m.read = 0;
         break;
     case p2m_access_r:
+    case p2m_access_r_pw:
         e->p2m.write = 0;
         e->p2m.xn = 1;
         break;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 922c9b3af6..39e39ce4ce 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1897,6 +1897,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla,
             violation = npfec.read_access || npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_r:
+        case p2m_access_r_pw:
             violation = npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_w:
diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c
index 74621000b2..523586ca98 100644
--- a/xen/arch/x86/hvm/monitor.c
+++ b/xen/arch/x86/hvm/monitor.c
@@ -295,6 +295,7 @@ bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn, uint32_t pfec,
 
     case XENMEM_access_r:
     case XENMEM_access_n:
+    case XENMEM_access_r_pw:
         if ( pfec & PFEC_write_access )
             req.u.mem_access.flags |= MEM_ACCESS_R | MEM_ACCESS_W;
         if ( pfec & PFEC_insn_fetch )
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 147e998371..8c0ea789c1 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -203,6 +203,7 @@ static void __init vmx_display_features(void)
     P(cpu_has_vmx_bus_lock_detection, "Bus Lock Detection");
     P(cpu_has_vmx_notify_vm_exiting, "Notify VM Exit");
     P(cpu_has_vmx_virt_spec_ctrl, "Virtualize SPEC_CTRL");
+    P(cpu_has_vmx_ept_paging_write, "EPT Paging-Write");
 #undef P
 
     if ( !printed )
@@ -366,7 +367,8 @@ static int vmx_init_vmcs_config(bool bsp)
 
     if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS )
     {
-        uint64_t opt = TERTIARY_EXEC_VIRT_SPEC_CTRL;
+        uint64_t opt = (TERTIARY_EXEC_VIRT_SPEC_CTRL |
+                        TERTIARY_EXEC_EPT_PAGING_WRITE);
 
         _vmx_tertiary_exec_control = adjust_vmx_controls2(
             "Tertiary Exec Control", 0, opt,
diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
index 939b87eb50..e1d3398141 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
@@ -273,6 +273,9 @@ extern uint64_t vmx_tertiary_exec_control;
 #define cpu_has_vmx_virt_spec_ctrl \
      (vmx_tertiary_exec_control & TERTIARY_EXEC_VIRT_SPEC_CTRL)
 
+#define cpu_has_vmx_ept_paging_write \
+     (vmx_tertiary_exec_control & TERTIARY_EXEC_EPT_PAGING_WRITE)
+
 #define VMX_EPT_EXEC_ONLY_SUPPORTED                         0x00000001
 #define VMX_EPT_WALK_LENGTH_4_SUPPORTED                     0x00000040
 #define VMX_EPT_MEMORY_TYPE_UC                              0x00000100
diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h
index e6de37f108..aa1bf7c9d0 100644
--- a/xen/arch/x86/include/asm/p2m.h
+++ b/xen/arch/x86/include/asm/p2m.h
@@ -980,6 +980,7 @@ static inline unsigned int p2m_access_to_iommu_flags(p2m_access_t p2ma)
     case p2m_access_r:
     case p2m_access_rx:
     case p2m_access_rx2rw:
+    case p2m_access_r_pw:
         return IOMMUF_readable;
 
     case p2m_access_w:
diff --git a/xen/arch/x86/mm/hap/nested_hap.c b/xen/arch/x86/mm/hap/nested_hap.c
index cc7bc6e5ea..255fba7e1c 100644
--- a/xen/arch/x86/mm/hap/nested_hap.c
+++ b/xen/arch/x86/mm/hap/nested_hap.c
@@ -213,6 +213,9 @@ int nestedhvm_hap_nested_page_fault(
     case p2m_access_n2rwx:
         p2ma_10 = p2m_access_n;
         break;
+    case p2m_access_r_pw:
+        p2ma_10 = p2m_access_r;
+        break;
     default:
         p2ma_10 = p2m_access_n;
         /* For safety, remove all permissions. */
diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c
index 60a0cce68a..21b5b7ecda 100644
--- a/xen/arch/x86/mm/mem_access.c
+++ b/xen/arch/x86/mm/mem_access.c
@@ -45,6 +45,7 @@ static int _p2m_get_mem_access(struct p2m_domain *p2m, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -94,6 +95,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v,
             break;
 
         case XENMEM_access_r:
+        case XENMEM_access_r_pw:
             violation = data->flags & MEM_ACCESS_WX;
             break;
 
@@ -312,6 +314,7 @@ bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c
index 21728397f9..0cf6818c13 100644
--- a/xen/arch/x86/mm/p2m-ept.c
+++ b/xen/arch/x86/mm/p2m-ept.c
@@ -149,12 +149,16 @@ static void ept_p2m_type_to_flags(const struct p2m_domain *p2m,
     }
 
     /* Then restrict with access permissions */
+    entry->pw = 0;
     switch ( entry->access )
     {
         case p2m_access_n:
         case p2m_access_n2rwx:
             entry->r = entry->w = entry->x = 0;
             break;
+        case p2m_access_r_pw:
+            entry->pw = !!cpu_has_vmx_ept_paging_write;
+            fallthrough;
         case p2m_access_r:
             entry->w = entry->x = 0;
             break;
diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h
index 5e545ae9a4..bd9fc37b52 100644
--- a/xen/include/public/memory.h
+++ b/xen/include/public/memory.h
@@ -426,6 +426,15 @@ typedef enum {
      * pausing the vcpu
      */
     XENMEM_access_n2rwx,
+
+    /*
+     * Same as XENMEM_access_r, but on processors with
+     * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+     * CPU-initiated page-table walks can still
+     * write to it (e.g., update A/D bits)
+     */
+    XENMEM_access_r_pw,
+
     /* Take the domain default */
     XENMEM_access_default
 } xenmem_access_t;
diff --git a/xen/include/xen/mem_access.h b/xen/include/xen/mem_access.h
index 87d93b31f6..2231341b5d 100644
--- a/xen/include/xen/mem_access.h
+++ b/xen/include/xen/mem_access.h
@@ -64,6 +64,12 @@ typedef enum {
                            * generates an event but does not pause the
                            * vcpu */
 
+    p2m_access_r_pw = 10, /* Special: same as R, but on processors with
+                           * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+                           * CPU-initiated page-table walks can still
+                           * write to it (e.g., update A/D bits)
+                           */
+
     /* NOTE: Assumed to be only 4 bits right now on x86. */
 } p2m_access_t;
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86: Rename _rsvd field to pw and move it to the bit 58
Message-Id: <E1tXPq1-0028lL-1Y@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 19:11:01 +0000

commit b94305d984fe469bd7c93025fb181f217202d0a5
Author:     Petr Beneš <w1benny@gmail.com>
AuthorDate: Thu Jan 2 17:13:27 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 16:50:29 2025 +0000

    x86: Rename _rsvd field to pw and move it to the bit 58
    
    The EPT Paging-write feature (when enabled by the
    TERTIARY_EXEC_EPT_PAGING_WRITE bit) uses bit 58 of the EPT entry to
    indicate that guest paging may update the page, even if the W access
    is not set.
    
    This patch is a preparation for the EPT Paging-write feature.
    
    Signed-off-by: Petr Beneš <w1benny@gmail.com>
    Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/include/asm/hvm/vmx/vmx.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
index f0ec459622..d920de96b7 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
@@ -34,8 +34,8 @@ typedef union {
                                EPT/VT-d usage */
         mfn         :   40, /* bits 51:12 - Machine physical frame number */
         sa_p2mt     :   6,  /* bits 57:52 - Software available 2 */
-        access      :   4,  /* bits 61:58 - p2m_access_t */
-        _rsvd       :   1,  /* bit 62 - reserved */
+        pw          :   1,  /* bit 58 - Paging-write access */
+        access      :   4,  /* bits 62:59 - p2m_access_t */
         suppress_ve :   1;  /* bit 63 - suppress #VE */
     };
     u64 epte;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86: Add Support for Paging-Write Feature
Message-Id: <E1tXPqB-0028m6-2A@xenbits.xenproject.org>
Date: Mon, 13 Jan 2025 19:11:11 +0000

commit ff10aa9d8f90cf18ff198581e83e8401f9e5d950
Author:     Petr Beneš <w1benny@gmail.com>
AuthorDate: Thu Jan 2 17:13:28 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Mon Jan 13 16:50:29 2025 +0000

    x86: Add Support for Paging-Write Feature
    
    This patch introduces a new XENMEM_access_r_pw permission.
    Functionally, it is similar to XENMEM_access_r, but for processors
    with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake
    and later, Xeon 4th Gen/Sappire Rapids and later), it also permits the
    CPU to write to the page during guest page-table walks (e.g., updating
    A/D bits) without triggering an EPT violation.
    
    This behavior works by both enabling the EPT paging-write feature and
    setting the EPT paging-write flag in the EPT leaf entry.
    
    This feature provides a significant performance boost for
    introspection tools that monitor guest page-table updates. Previously,
    every page-table modification by the guest—including routine updates
    like setting A/D bits—triggered an EPT violation, adding unnecessary
    overhead. The new XENMEM_access_r_pw permission allows these
    "uninteresting" updates to occur without EPT violations, improving
    efficiency.
    
    Additionally, this feature simplifies the handling of race conditions
    in scenarios where an introspection tool:
    
    - Sets an "invisible breakpoint" in the altp2m view for a function F.
    - Monitors guest page-table updates to track whether the page
      containing F is paged out.
    - Encounters a cleared Access (A) bit on the page containing F while
      the guest is about to execute the breakpoint.
    
    In the current implementation:
    
    - If xc_monitor_inguest_pagefault() is enabled, the introspection tool
      must emulate both the breakpoint and the setting of the Access bit.
    - If xc_monitor_inguest_pagefault() is disabled, Xen handles the EPT
      violation without notifying the introspection tool, setting the
      Access bit and emulating the instruction. However, Xen fetches the
      instruction from the default view instead of the altp2m view,
      potentially causing the breakpoint to be missed.
    
    With this patch, setting XENMEM_access_r_pw for monitored guest
    page-tables prevents EPT violations in these cases. This change
    enhances performance and reduces complexity for introspection tools,
    ensuring seamless breakpoint handling while tracking guest page-table
    updates.
    
    Signed-off-by: Petr Beneš <w1benny@gmail.com>
    Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/arm/mem_access.c               | 4 ++++
 xen/arch/arm/mmu/p2m.c                  | 1 +
 xen/arch/x86/hvm/hvm.c                  | 1 +
 xen/arch/x86/hvm/monitor.c              | 1 +
 xen/arch/x86/hvm/vmx/vmcs.c             | 4 +++-
 xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 3 +++
 xen/arch/x86/include/asm/p2m.h          | 1 +
 xen/arch/x86/mm/hap/nested_hap.c        | 3 +++
 xen/arch/x86/mm/mem_access.c            | 3 +++
 xen/arch/x86/mm/p2m-ept.c               | 4 ++++
 xen/include/public/memory.h             | 9 +++++++++
 xen/include/xen/mem_access.h            | 6 ++++++
 12 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c
index 0ec3462364..2af92bb402 100644
--- a/xen/arch/arm/mem_access.c
+++ b/xen/arch/arm/mem_access.c
@@ -32,6 +32,7 @@ static int __p2m_get_mem_access(struct domain *d, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -172,6 +173,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag,
             break;
         else
             goto err;
+    case XENMEM_access_r_pw:
     case XENMEM_access_rx2rw:
     case XENMEM_access_rx:
     case XENMEM_access_r:
@@ -253,6 +255,7 @@ bool p2m_mem_access_check(paddr_t gpa, vaddr_t gla, const struct npfec npfec)
         violation = npfec.read_access || npfec.insn_fetch;
         break;
     case XENMEM_access_r:
+    case XENMEM_access_r_pw:
         violation = npfec.write_access || npfec.insn_fetch;
         break;
     default:
@@ -361,6 +364,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c
index 28df6e5d03..7642dbc7c5 100644
--- a/xen/arch/arm/mmu/p2m.c
+++ b/xen/arch/arm/mmu/p2m.c
@@ -597,6 +597,7 @@ static void p2m_set_permission(lpae_t *e, p2m_type_t t, p2m_access_t a)
         e->p2m.read = 0;
         break;
     case p2m_access_r:
+    case p2m_access_r_pw:
         e->p2m.write = 0;
         e->p2m.xn = 1;
         break;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 922c9b3af6..39e39ce4ce 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1897,6 +1897,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla,
             violation = npfec.read_access || npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_r:
+        case p2m_access_r_pw:
             violation = npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_w:
diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c
index 74621000b2..523586ca98 100644
--- a/xen/arch/x86/hvm/monitor.c
+++ b/xen/arch/x86/hvm/monitor.c
@@ -295,6 +295,7 @@ bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn, uint32_t pfec,
 
     case XENMEM_access_r:
     case XENMEM_access_n:
+    case XENMEM_access_r_pw:
         if ( pfec & PFEC_write_access )
             req.u.mem_access.flags |= MEM_ACCESS_R | MEM_ACCESS_W;
         if ( pfec & PFEC_insn_fetch )
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 147e998371..8c0ea789c1 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -203,6 +203,7 @@ static void __init vmx_display_features(void)
     P(cpu_has_vmx_bus_lock_detection, "Bus Lock Detection");
     P(cpu_has_vmx_notify_vm_exiting, "Notify VM Exit");
     P(cpu_has_vmx_virt_spec_ctrl, "Virtualize SPEC_CTRL");
+    P(cpu_has_vmx_ept_paging_write, "EPT Paging-Write");
 #undef P
 
     if ( !printed )
@@ -366,7 +367,8 @@ static int vmx_init_vmcs_config(bool bsp)
 
     if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS )
     {
-        uint64_t opt = TERTIARY_EXEC_VIRT_SPEC_CTRL;
+        uint64_t opt = (TERTIARY_EXEC_VIRT_SPEC_CTRL |
+                        TERTIARY_EXEC_EPT_PAGING_WRITE);
 
         _vmx_tertiary_exec_control = adjust_vmx_controls2(
             "Tertiary Exec Control", 0, opt,
diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
index 939b87eb50..e1d3398141 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
@@ -273,6 +273,9 @@ extern uint64_t vmx_tertiary_exec_control;
 #define cpu_has_vmx_virt_spec_ctrl \
      (vmx_tertiary_exec_control & TERTIARY_EXEC_VIRT_SPEC_CTRL)
 
+#define cpu_has_vmx_ept_paging_write \
+     (vmx_tertiary_exec_control & TERTIARY_EXEC_EPT_PAGING_WRITE)
+
 #define VMX_EPT_EXEC_ONLY_SUPPORTED                         0x00000001
 #define VMX_EPT_WALK_LENGTH_4_SUPPORTED                     0x00000040
 #define VMX_EPT_MEMORY_TYPE_UC                              0x00000100
diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h
index e6de37f108..aa1bf7c9d0 100644
--- a/xen/arch/x86/include/asm/p2m.h
+++ b/xen/arch/x86/include/asm/p2m.h
@@ -980,6 +980,7 @@ static inline unsigned int p2m_access_to_iommu_flags(p2m_access_t p2ma)
     case p2m_access_r:
     case p2m_access_rx:
     case p2m_access_rx2rw:
+    case p2m_access_r_pw:
         return IOMMUF_readable;
 
     case p2m_access_w:
diff --git a/xen/arch/x86/mm/hap/nested_hap.c b/xen/arch/x86/mm/hap/nested_hap.c
index cc7bc6e5ea..255fba7e1c 100644
--- a/xen/arch/x86/mm/hap/nested_hap.c
+++ b/xen/arch/x86/mm/hap/nested_hap.c
@@ -213,6 +213,9 @@ int nestedhvm_hap_nested_page_fault(
     case p2m_access_n2rwx:
         p2ma_10 = p2m_access_n;
         break;
+    case p2m_access_r_pw:
+        p2ma_10 = p2m_access_r;
+        break;
     default:
         p2ma_10 = p2m_access_n;
         /* For safety, remove all permissions. */
diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c
index 60a0cce68a..21b5b7ecda 100644
--- a/xen/arch/x86/mm/mem_access.c
+++ b/xen/arch/x86/mm/mem_access.c
@@ -45,6 +45,7 @@ static int _p2m_get_mem_access(struct p2m_domain *p2m, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -94,6 +95,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v,
             break;
 
         case XENMEM_access_r:
+        case XENMEM_access_r_pw:
             violation = data->flags & MEM_ACCESS_WX;
             break;
 
@@ -312,6 +314,7 @@ bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c
index 21728397f9..0cf6818c13 100644
--- a/xen/arch/x86/mm/p2m-ept.c
+++ b/xen/arch/x86/mm/p2m-ept.c
@@ -149,12 +149,16 @@ static void ept_p2m_type_to_flags(const struct p2m_domain *p2m,
     }
 
     /* Then restrict with access permissions */
+    entry->pw = 0;
     switch ( entry->access )
     {
         case p2m_access_n:
         case p2m_access_n2rwx:
             entry->r = entry->w = entry->x = 0;
             break;
+        case p2m_access_r_pw:
+            entry->pw = !!cpu_has_vmx_ept_paging_write;
+            fallthrough;
         case p2m_access_r:
             entry->w = entry->x = 0;
             break;
diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h
index 5e545ae9a4..bd9fc37b52 100644
--- a/xen/include/public/memory.h
+++ b/xen/include/public/memory.h
@@ -426,6 +426,15 @@ typedef enum {
      * pausing the vcpu
      */
     XENMEM_access_n2rwx,
+
+    /*
+     * Same as XENMEM_access_r, but on processors with
+     * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+     * CPU-initiated page-table walks can still
+     * write to it (e.g., update A/D bits)
+     */
+    XENMEM_access_r_pw,
+
     /* Take the domain default */
     XENMEM_access_default
 } xenmem_access_t;
diff --git a/xen/include/xen/mem_access.h b/xen/include/xen/mem_access.h
index 87d93b31f6..2231341b5d 100644
--- a/xen/include/xen/mem_access.h
+++ b/xen/include/xen/mem_access.h
@@ -64,6 +64,12 @@ typedef enum {
                            * generates an event but does not pause the
                            * vcpu */
 
+    p2m_access_r_pw = 10, /* Special: same as R, but on processors with
+                           * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+                           * CPU-initiated page-table walks can still
+                           * write to it (e.g., update A/D bits)
+                           */
+
     /* NOTE: Assumed to be only 4 bits right now on x86. */
 } p2m_access_t;
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] misra: add deviation for MISRA C Rule R11.8
Message-Id: <E1tY52v-006aHS-1e@xenbits.xenproject.org>
Date: Wed, 15 Jan 2025 15:11:05 +0000

commit f4697f7a3532adc7472feb5bccfd20dd10cdf7ef
Author:     Alessandro Zucchelli <alessandro.zucchelli@bugseng.com>
AuthorDate: Wed Jan 15 16:01:13 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:13 2025 +0100

    misra: add deviation for MISRA C Rule R11.8
    
    Rule 11.8 states as following: "A cast shall not remove any `const' or
    `volatile' qualification from the type pointed to by a pointer".
    
    Function `__hvm_copy' in `xen/arch/x86/hvm/hvm.c' is a double-use
    function, where the parameter needs to not be const because it can be
    set for write or not. As it was decided a new const-only function will
    lead to more developer confusion than it's worth, this violation is
    addressed by deviating the function.
    All cases of casting away const-ness are accompanied with a comment
    explaining why it is safe given the other flags passed in; such comment is used
    by the deviation in order to match the appropriate function call.
    
    No functional change.
    
    Signed-off-by: Alessandro Zucchelli <alessandro.zucchelli@bugseng.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
 docs/misra/deviations.rst                        | 9 +++++++++
 2 files changed, 15 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
index ae25eeb76a..a28eb0ae76 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -393,6 +393,12 @@ Fixing this violation would require to increase code complexity and lower readab
 -config=MC3A2.R11.8,reports+={safe,"any_area(any_loc(any_exp(macro(^container_of$))))"}
 -doc_end
 
+-doc_begin="Function __hvm_copy in xen/arch/x86/hvm/hvm.c is a double-use
+function, where the parameter needs to not be const because it can be set for
+write or not"
+-config=MC3A2.R11.8,reports+={safe,"any_area(any_loc(text(^.*__hvm_copy.*HVMCOPY_to_guest doesn't modify.*$)))"}
+-doc_end
+
 -doc_begin="This construct is used to check if the type is scalar, and for this purpose the use of 0 as a null pointer constant is deliberate."
 -config=MC3A2.R11.9,reports+={deliberate, "any_area(any_loc(any_exp(macro(^__ACCESS_ONCE$))))"
 }
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 15a993d050..fe0b1e10a2 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -353,6 +353,15 @@ Deviations related to MISRA C:2012 Rules:
        Fixing this violation would require to increase code complexity and lower readability.
      - Tagged as `safe` for ECLAIR.
 
+   * - R11.8
+     - Violations caused by function __hvm_copy occur when a const void
+       argument is passed, as the const qualifier is stripped. However, in such
+       cases, the function ensures that it does not modify the buffer
+       referenced by the argument, therefore, this use is deemed safe. Fixing
+       this violation would require to increase code complexity and lower
+       readability.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.9
      - __ACCESS_ONCE uses an integer, which happens to be zero, as a
        compile time check. The typecheck uses a cast. The usage of zero or other
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] MAINTAINERS: Change reviewer of the ECLAIR integration
Message-Id: <E1tY535-006aIi-27@xenbits.xenproject.org>
Date: Wed, 15 Jan 2025 15:11:15 +0000

commit 16a670ab5318ae5340cf4bda4846e98f67fd37d3
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Wed Jan 15 16:01:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:25 2025 +0100

    MAINTAINERS: Change reviewer of the ECLAIR integration
    
    Simone Ballarin is no longer actively involved in reviewing
    the ECLAIR integration for Xen. I am stepping up as a reviewer.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Simone Ballarin <simone.ballarin@bugseng.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 392f780f76..c11b82eca9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -297,7 +297,7 @@ F:	xen/include/xen/device_tree.h
 F:	xen/drivers/passthrough/device_tree.c
 
 ECLAIR
-R:	Simone Ballarin <simone.ballarin@bugseng.com>
+R:	Nicola Vetrini <nicola.vetrini@bugseng.com>
 S:	Supported
 F:	automation/eclair_analysis/
 F:	automation/scripts/eclair
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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Subject: [xen staging] docs: Improve spelling of few cases in the documentation
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Date: Wed, 15 Jan 2025 15:11:25 +0000

commit d68de813442fbd6661c7dd259a066eac7d169496
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 16:01:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:39 2025 +0100

    docs: Improve spelling of few cases in the documentation
    
    Skimming the docs, I came across a few places for spelling improvements.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/designs/non-cooperative-migration.md | 4 ++--
 docs/designs/qemu-deprivilege.md          | 2 +-
 docs/guest-guide/x86/hypercall-abi.rst    | 2 +-
 docs/man/xl.conf.5.pod.in                 | 2 +-
 docs/misc/livepatch.pandoc                | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/docs/designs/non-cooperative-migration.md b/docs/designs/non-cooperative-migration.md
index 4b876d809f..54496892ed 100644
--- a/docs/designs/non-cooperative-migration.md
+++ b/docs/designs/non-cooperative-migration.md
@@ -112,7 +112,7 @@ because the guest can sample its own domid from the frontend area and use
 it in hypercalls (e.g. HVMOP_set_param) rather than DOMID_SELF, the guest
 domid must also be preserved to maintain the ABI.
 
-Furthermore, it will necessary to modify backend drivers to re-establish
+Furthermore, it will be necessary to modify backend drivers to re-establish
 communication with frontend drivers without perturbing the content of the
 backend area or requiring any changes to the values of the xenstore state
 nodes.
@@ -259,7 +259,7 @@ Essentially this should skip the check to see if PV drivers and migrate as
 if there are none present, but also enabling the extra save records. Note
 that at least some of the extra records should only form part of a
 non-cooperative migration stream. For example, migrating event channel
-state would be counter productive in a normal migration as this will
+state would be counter-productive in a normal migration as this will
 essentially leak event channel objects at the receiving end. Others, such
 as grant table state, could potentially harmlessly form part of a normal
 migration stream.
diff --git a/docs/designs/qemu-deprivilege.md b/docs/designs/qemu-deprivilege.md
index 81a5f5c05d..f12b1a3ae3 100644
--- a/docs/designs/qemu-deprivilege.md
+++ b/docs/designs/qemu-deprivilege.md
@@ -3,7 +3,7 @@
 The goal of deprilvileging qemu is this: Even if there is a bug (for
 example in qemu) which permits a domain to gain control of the device
 model, the compromised device model process is prevented from
-violating the system's overall security properties.  Ie, a guest
+violating the system's overall security properties.  I.e., a guest
 cannot "escape" from the virtualisation by using a qemu bug.
 
 This document lists the various technical measures which we either
diff --git a/docs/guest-guide/x86/hypercall-abi.rst b/docs/guest-guide/x86/hypercall-abi.rst
index 745fbbb64a..e52ed453bc 100644
--- a/docs/guest-guide/x86/hypercall-abi.rst
+++ b/docs/guest-guide/x86/hypercall-abi.rst
@@ -109,7 +109,7 @@ abstracting away the details of how it is currently running.
 Creating Hypercall Pages
 ------------------------
 
-Guests which are started using the PV boot protocol may set set
+Guests which are started using the PV boot protocol may set
 ``XEN_ELFNOTE_HYPERCALL_PAGE`` to have the nominated page written as a
 hypercall page during construction.  This mechanism is common for PV guests,
 and allows hypercalls to be issued with no additional setup.
diff --git a/docs/man/xl.conf.5.pod.in b/docs/man/xl.conf.5.pod.in
index 44738b80bf..0cfec8587c 100644
--- a/docs/man/xl.conf.5.pod.in
+++ b/docs/man/xl.conf.5.pod.in
@@ -4,7 +4,7 @@
 
 =head1 DESCRIPTION
 
-The F<xl.conf> file allows configuration of hostwide C<xl> toolstack
+The F<xl.conf> file allows configuration of host-wide C<xl> toolstack
 options.
 
 For details of per-domain configuration options please see
diff --git a/docs/misc/livepatch.pandoc b/docs/misc/livepatch.pandoc
index a94fb57eb5..4a0b4fd6d8 100644
--- a/docs/misc/livepatch.pandoc
+++ b/docs/misc/livepatch.pandoc
@@ -2,7 +2,7 @@
 
 ## Rationale
 
-A mechanism is required to binarily patch the running hypervisor with new
+A mechanism is required to binary patch the running hypervisor with new
 opcodes that have come about due to primarily security updates.
 
 This document describes the design of the API that would allow us to
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] misra: add deviation for MISRA C Rule R11.8
Message-Id: <E1tY5oH-006fc2-1W@xenbits.xenproject.org>
Date: Wed, 15 Jan 2025 16:00:01 +0000

commit f4697f7a3532adc7472feb5bccfd20dd10cdf7ef
Author:     Alessandro Zucchelli <alessandro.zucchelli@bugseng.com>
AuthorDate: Wed Jan 15 16:01:13 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:13 2025 +0100

    misra: add deviation for MISRA C Rule R11.8
    
    Rule 11.8 states as following: "A cast shall not remove any `const' or
    `volatile' qualification from the type pointed to by a pointer".
    
    Function `__hvm_copy' in `xen/arch/x86/hvm/hvm.c' is a double-use
    function, where the parameter needs to not be const because it can be
    set for write or not. As it was decided a new const-only function will
    lead to more developer confusion than it's worth, this violation is
    addressed by deviating the function.
    All cases of casting away const-ness are accompanied with a comment
    explaining why it is safe given the other flags passed in; such comment is used
    by the deviation in order to match the appropriate function call.
    
    No functional change.
    
    Signed-off-by: Alessandro Zucchelli <alessandro.zucchelli@bugseng.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
 docs/misra/deviations.rst                        | 9 +++++++++
 2 files changed, 15 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
index ae25eeb76a..a28eb0ae76 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -393,6 +393,12 @@ Fixing this violation would require to increase code complexity and lower readab
 -config=MC3A2.R11.8,reports+={safe,"any_area(any_loc(any_exp(macro(^container_of$))))"}
 -doc_end
 
+-doc_begin="Function __hvm_copy in xen/arch/x86/hvm/hvm.c is a double-use
+function, where the parameter needs to not be const because it can be set for
+write or not"
+-config=MC3A2.R11.8,reports+={safe,"any_area(any_loc(text(^.*__hvm_copy.*HVMCOPY_to_guest doesn't modify.*$)))"}
+-doc_end
+
 -doc_begin="This construct is used to check if the type is scalar, and for this purpose the use of 0 as a null pointer constant is deliberate."
 -config=MC3A2.R11.9,reports+={deliberate, "any_area(any_loc(any_exp(macro(^__ACCESS_ONCE$))))"
 }
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 15a993d050..fe0b1e10a2 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -353,6 +353,15 @@ Deviations related to MISRA C:2012 Rules:
        Fixing this violation would require to increase code complexity and lower readability.
      - Tagged as `safe` for ECLAIR.
 
+   * - R11.8
+     - Violations caused by function __hvm_copy occur when a const void
+       argument is passed, as the const qualifier is stripped. However, in such
+       cases, the function ensures that it does not modify the buffer
+       referenced by the argument, therefore, this use is deemed safe. Fixing
+       this violation would require to increase code complexity and lower
+       readability.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.9
      - __ACCESS_ONCE uses an integer, which happens to be zero, as a
        compile time check. The typecheck uses a cast. The usage of zero or other
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] MAINTAINERS: Change reviewer of the ECLAIR integration
Message-Id: <E1tY5oR-006fdw-1w@xenbits.xenproject.org>
Date: Wed, 15 Jan 2025 16:00:11 +0000

commit 16a670ab5318ae5340cf4bda4846e98f67fd37d3
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Wed Jan 15 16:01:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:25 2025 +0100

    MAINTAINERS: Change reviewer of the ECLAIR integration
    
    Simone Ballarin is no longer actively involved in reviewing
    the ECLAIR integration for Xen. I am stepping up as a reviewer.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Simone Ballarin <simone.ballarin@bugseng.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 392f780f76..c11b82eca9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -297,7 +297,7 @@ F:	xen/include/xen/device_tree.h
 F:	xen/drivers/passthrough/device_tree.c
 
 ECLAIR
-R:	Simone Ballarin <simone.ballarin@bugseng.com>
+R:	Nicola Vetrini <nicola.vetrini@bugseng.com>
 S:	Supported
 F:	automation/eclair_analysis/
 F:	automation/scripts/eclair
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs: Improve spelling of few cases in the documentation
Message-Id: <E1tY5ob-006ff7-2H@xenbits.xenproject.org>
Date: Wed, 15 Jan 2025 16:00:21 +0000

commit d68de813442fbd6661c7dd259a066eac7d169496
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 16:01:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed Jan 15 16:01:39 2025 +0100

    docs: Improve spelling of few cases in the documentation
    
    Skimming the docs, I came across a few places for spelling improvements.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/designs/non-cooperative-migration.md | 4 ++--
 docs/designs/qemu-deprivilege.md          | 2 +-
 docs/guest-guide/x86/hypercall-abi.rst    | 2 +-
 docs/man/xl.conf.5.pod.in                 | 2 +-
 docs/misc/livepatch.pandoc                | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/docs/designs/non-cooperative-migration.md b/docs/designs/non-cooperative-migration.md
index 4b876d809f..54496892ed 100644
--- a/docs/designs/non-cooperative-migration.md
+++ b/docs/designs/non-cooperative-migration.md
@@ -112,7 +112,7 @@ because the guest can sample its own domid from the frontend area and use
 it in hypercalls (e.g. HVMOP_set_param) rather than DOMID_SELF, the guest
 domid must also be preserved to maintain the ABI.
 
-Furthermore, it will necessary to modify backend drivers to re-establish
+Furthermore, it will be necessary to modify backend drivers to re-establish
 communication with frontend drivers without perturbing the content of the
 backend area or requiring any changes to the values of the xenstore state
 nodes.
@@ -259,7 +259,7 @@ Essentially this should skip the check to see if PV drivers and migrate as
 if there are none present, but also enabling the extra save records. Note
 that at least some of the extra records should only form part of a
 non-cooperative migration stream. For example, migrating event channel
-state would be counter productive in a normal migration as this will
+state would be counter-productive in a normal migration as this will
 essentially leak event channel objects at the receiving end. Others, such
 as grant table state, could potentially harmlessly form part of a normal
 migration stream.
diff --git a/docs/designs/qemu-deprivilege.md b/docs/designs/qemu-deprivilege.md
index 81a5f5c05d..f12b1a3ae3 100644
--- a/docs/designs/qemu-deprivilege.md
+++ b/docs/designs/qemu-deprivilege.md
@@ -3,7 +3,7 @@
 The goal of deprilvileging qemu is this: Even if there is a bug (for
 example in qemu) which permits a domain to gain control of the device
 model, the compromised device model process is prevented from
-violating the system's overall security properties.  Ie, a guest
+violating the system's overall security properties.  I.e., a guest
 cannot "escape" from the virtualisation by using a qemu bug.
 
 This document lists the various technical measures which we either
diff --git a/docs/guest-guide/x86/hypercall-abi.rst b/docs/guest-guide/x86/hypercall-abi.rst
index 745fbbb64a..e52ed453bc 100644
--- a/docs/guest-guide/x86/hypercall-abi.rst
+++ b/docs/guest-guide/x86/hypercall-abi.rst
@@ -109,7 +109,7 @@ abstracting away the details of how it is currently running.
 Creating Hypercall Pages
 ------------------------
 
-Guests which are started using the PV boot protocol may set set
+Guests which are started using the PV boot protocol may set
 ``XEN_ELFNOTE_HYPERCALL_PAGE`` to have the nominated page written as a
 hypercall page during construction.  This mechanism is common for PV guests,
 and allows hypercalls to be issued with no additional setup.
diff --git a/docs/man/xl.conf.5.pod.in b/docs/man/xl.conf.5.pod.in
index 44738b80bf..0cfec8587c 100644
--- a/docs/man/xl.conf.5.pod.in
+++ b/docs/man/xl.conf.5.pod.in
@@ -4,7 +4,7 @@
 
 =head1 DESCRIPTION
 
-The F<xl.conf> file allows configuration of hostwide C<xl> toolstack
+The F<xl.conf> file allows configuration of host-wide C<xl> toolstack
 options.
 
 For details of per-domain configuration options please see
diff --git a/docs/misc/livepatch.pandoc b/docs/misc/livepatch.pandoc
index a94fb57eb5..4a0b4fd6d8 100644
--- a/docs/misc/livepatch.pandoc
+++ b/docs/misc/livepatch.pandoc
@@ -2,7 +2,7 @@
 
 ## Rationale
 
-A mechanism is required to binarily patch the running hypervisor with new
+A mechanism is required to binary patch the running hypervisor with new
 opcodes that have come about due to primarily security updates.
 
 This document describes the design of the API that would allow us to
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] automation/eclair: make Misra rule 20.7 blocking
Message-Id: <E1tYLTx-008Grp-0H@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 08:44:05 +0000

commit 405fdcee91d02de02d25d24446f1c484d846539c
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue Jan 14 12:08:22 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:17 2025 +0100

    automation/eclair: make Misra rule 20.7 blocking
    
    There are no violations left, make the rule globally blocking for both x86
    and ARM.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 automation/eclair_analysis/ECLAIR/tagging.ecl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/automation/eclair_analysis/ECLAIR/tagging.ecl b/automation/eclair_analysis/ECLAIR/tagging.ecl
index 4a1d3b3a98..491625e84c 100644
--- a/automation/eclair_analysis/ECLAIR/tagging.ecl
+++ b/automation/eclair_analysis/ECLAIR/tagging.ecl
@@ -80,6 +80,7 @@ MC3A2.R20.2||
 MC3A2.R20.3||
 MC3A2.R20.4||
 MC3A2.R20.6||
+MC3A2.R20.7||
 MC3A2.R20.9||
 MC3A2.R20.11||
 MC3A2.R20.12||
@@ -116,7 +117,7 @@ if(string_equal(target,"x86_64"),
 )
 
 if(string_equal(target,"arm64"),
-    service_selector({"additional_clean_guidelines","MC3A2.R5.3||MC3.R11.2||MC3A2.R16.6||MC3A2.R20.7"})
+    service_selector({"additional_clean_guidelines","MC3A2.R5.3||MC3.R11.2||MC3A2.R16.6"})
 )
 
 -reports+={clean:added,"service(clean_guidelines_common||additional_clean_guidelines)"}
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/time: introduce command line option to select wallclock
Message-Id: <E1tYLU7-008GsW-0g@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 08:44:15 +0000

commit 7eba2f46a14fac55cff8a1a8e23dfcca75593930
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Sep 2 17:51:33 2024 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:17 2025 +0100

    x86/time: introduce command line option to select wallclock
    
    Allow setting the used wallclock from the command line.  When the option is set
    to a value different than `auto` the probing is bypassed and the selected
    implementation is used (as long as it's available).
    
    The `xen` and `efi` options require being booted as a Xen guest (with Xen guest
    supported built-in) or from UEFI firmware respectively.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 docs/misc/xen-command-line.pandoc | 21 ++++++++++++++++++++
 xen/arch/x86/time.c               | 41 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 08b0053f9c..9bbd00baef 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2887,6 +2887,27 @@ vwfi to `native` reduces irq latency significantly. It can also lead to
 suboptimal scheduling decisions, but only when the system is
 oversubscribed (i.e., in total there are more vCPUs than pCPUs).
 
+### wallclock (x86)
+> `= auto | xen | cmos | efi`
+
+> Default: `auto`
+
+Allow forcing the usage of a specific wallclock source.
+
+ * `auto` let the hypervisor select the clocksource based on internal
+   heuristics.
+
+ * `xen` force usage of the Xen shared_info wallclock when booted as a Xen
+   guest.  This option is only available if the hypervisor was compiled with
+   `CONFIG_XEN_GUEST` enabled.
+
+ * `cmos` force usage of the CMOS RTC wallclock.
+
+ * `efi` force usage of the EFI_GET_TIME run-time method when booted from EFI
+   firmware.
+
+If the selected option is invalid or not available Xen will default to `auto`.
+
 ### watchdog (x86)
 > `= force | <boolean>`
 
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index a9aa335d7c..00545c45fd 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1552,6 +1552,37 @@ static const char *__init wallclock_type_to_string(void)
     return "";
 }
 
+static int __init cf_check parse_wallclock(const char *arg)
+{
+    wallclock_source = WALLCLOCK_UNSET;
+
+    if ( !arg )
+        return -EINVAL;
+
+    if ( !strcmp("auto", arg) )
+        ASSERT(wallclock_source == WALLCLOCK_UNSET);
+    else if ( !strcmp("xen", arg) )
+    {
+        if ( !xen_guest )
+            return -EINVAL;
+
+        wallclock_source = WALLCLOCK_XEN;
+    }
+    else if ( !strcmp("cmos", arg) )
+        wallclock_source = WALLCLOCK_CMOS;
+    else if ( !strcmp("efi", arg) )
+        /*
+         * Checking if run-time services are available must be done after
+         * command line parsing.
+         */
+        wallclock_source = WALLCLOCK_EFI;
+    else
+        return -EINVAL;
+
+    return 0;
+}
+custom_param("wallclock", parse_wallclock);
+
 static void __init probe_wallclock(void)
 {
     ASSERT(wallclock_source == WALLCLOCK_UNSET);
@@ -2527,7 +2558,15 @@ int __init init_xen_time(void)
 
     open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
 
-    probe_wallclock();
+    /*
+     * EFI run time services can be disabled from the command line, hence the
+     * check for them cannot be done as part of the wallclock option parsing.
+     */
+    if ( wallclock_source == WALLCLOCK_EFI && !efi_enabled(EFI_RS) )
+        wallclock_source = WALLCLOCK_UNSET;
+
+    if ( wallclock_source == WALLCLOCK_UNSET )
+        probe_wallclock();
 
     printk(XENLOG_INFO "Wallclock source: %s\n", wallclock_type_to_string());
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/time: prefer CMOS over EFI_GET_TIME
Message-Id: <E1tYLUH-008GtM-0x@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 08:44:25 +0000

commit 164ae033adb7df7cd2e7fd5b29329daceff664d2
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Sep 2 16:00:19 2024 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:30 2025 +0100

    x86/time: prefer CMOS over EFI_GET_TIME
    
    The EFI_GET_TIME implementation is well known to be broken for many firmware
    implementations, for Xen the result on such implementations are:
    
    ----[ Xen-4.19-unstable  x86_64  debug=y  Tainted:   C    ]----
    CPU:    0
    RIP:    e008:[<0000000062ccfa70>] 0000000062ccfa70
    [...]
    Xen call trace:
       [<0000000062ccfa70>] R 0000000062ccfa70
       [<00000000732e9a3f>] S 00000000732e9a3f
       [<ffff82d04034f34f>] F arch/x86/time.c#get_cmos_time+0x1b3/0x26e
       [<ffff82d04045926f>] F init_xen_time+0x28/0xa4
       [<ffff82d040454bc4>] F __start_xen+0x1ee7/0x2578
       [<ffff82d040203334>] F __high_start+0x94/0xa0
    
    Pagetable walk from 0000000062ccfa70:
     L4[0x000] = 000000207ef1c063 ffffffffffffffff
     L3[0x001] = 000000005d6c0063 ffffffffffffffff
     L2[0x116] = 8000000062c001e3 ffffffffffffffff (PSE)
    
    ****************************************
    Panic on CPU 0:
    FATAL PAGE FAULT
    [error_code=0011]
    Faulting linear address: 0000000062ccfa70
    ****************************************
    
    Swap the preference to default to CMOS first, and EFI later, in an attempt to
    use EFI_GET_TIME as a last resort option only.  Note that Linux for example
    doesn't allow calling the get_time method, and instead provides a dummy handler
    that unconditionally returns EFI_UNSUPPORTED on x86-64.
    
    Such change in the preferences requires some re-arranging of the function
    logic, so that panic messages with workaround suggestions are suitably printed.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Acked-By: Oleksii Kurochko<oleksii.kurochko@gmail.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 CHANGELOG.md        | 2 ++
 xen/arch/x86/time.c | 8 ++++----
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8507e6556a..1de1d1eca1 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -12,6 +12,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    leaving this to the guest kernel to do in guest context.
  - On x86:
    - Prefer ACPI reboot over UEFI ResetSystem() run time service call.
+   - Prefer CMOS over EFI_GET_TIME as time source.
    - Switched the xAPIC flat driver to use physical destination mode for external
      interrupts instead of logical destination mode.
 
@@ -24,6 +25,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Support for LLC (Last Level Cache) coloring.
  - On x86:
    - xl suspend/resume subcommands.
+   - `wallclock` command line option to select time source.
 
 ### Removed
  - On x86:
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 00545c45fd..59129f419d 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1592,14 +1592,14 @@ static void __init probe_wallclock(void)
         wallclock_source = WALLCLOCK_XEN;
         return;
     }
-    if ( efi_enabled(EFI_RS) && efi_get_time() )
+    if ( cmos_rtc_probe() )
     {
-        wallclock_source = WALLCLOCK_EFI;
+        wallclock_source = WALLCLOCK_CMOS;
         return;
     }
-    if ( cmos_rtc_probe() )
+    if ( efi_enabled(EFI_RS) && efi_get_time() )
     {
-        wallclock_source = WALLCLOCK_CMOS;
+        wallclock_source = WALLCLOCK_EFI;
         return;
     }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] automation/gitlab: disable coverage from clang randconfig
Message-Id: <E1tYLUR-008Gtp-1L@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 08:44:35 +0000

commit 9ee63ef5407d9678daae210fc1244deaaedc8f73
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue Jan 14 15:10:14 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:30:14 2025 +0100

    automation/gitlab: disable coverage from clang randconfig
    
    If randconfig enables coverage support the build times out due to GNU LD
    taking too long.  For the time being prevent coverage from being enabled in
    clang randconfig job.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 automation/gitlab-ci/build.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index cb84f379b7..bc4a8a5ad2 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -556,6 +556,8 @@ debian-12-x86_64-clang-randconfig:
   variables:
     CONTAINER: debian:12-x86_64
     RANDCONFIG: y
+    EXTRA_FIXED_RANDCONFIG: |
+      CONFIG_COVERAGE=n # Disable coverage otherwise build times out.
 
 debian-12-x86_64-gcc:
   extends: .gcc-x86-64-build
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] automation/eclair: make Misra rule 20.7 blocking
Message-Id: <E1tYMq6-008QmG-14@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 10:11:02 +0000

commit 405fdcee91d02de02d25d24446f1c484d846539c
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue Jan 14 12:08:22 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:17 2025 +0100

    automation/eclair: make Misra rule 20.7 blocking
    
    There are no violations left, make the rule globally blocking for both x86
    and ARM.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 automation/eclair_analysis/ECLAIR/tagging.ecl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/automation/eclair_analysis/ECLAIR/tagging.ecl b/automation/eclair_analysis/ECLAIR/tagging.ecl
index 4a1d3b3a98..491625e84c 100644
--- a/automation/eclair_analysis/ECLAIR/tagging.ecl
+++ b/automation/eclair_analysis/ECLAIR/tagging.ecl
@@ -80,6 +80,7 @@ MC3A2.R20.2||
 MC3A2.R20.3||
 MC3A2.R20.4||
 MC3A2.R20.6||
+MC3A2.R20.7||
 MC3A2.R20.9||
 MC3A2.R20.11||
 MC3A2.R20.12||
@@ -116,7 +117,7 @@ if(string_equal(target,"x86_64"),
 )
 
 if(string_equal(target,"arm64"),
-    service_selector({"additional_clean_guidelines","MC3A2.R5.3||MC3.R11.2||MC3A2.R16.6||MC3A2.R20.7"})
+    service_selector({"additional_clean_guidelines","MC3A2.R5.3||MC3.R11.2||MC3A2.R16.6"})
 )
 
 -reports+={clean:added,"service(clean_guidelines_common||additional_clean_guidelines)"}
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/time: introduce command line option to select wallclock
Message-Id: <E1tYMqG-008Qmq-1T@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 10:11:12 +0000

commit 7eba2f46a14fac55cff8a1a8e23dfcca75593930
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Sep 2 17:51:33 2024 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:17 2025 +0100

    x86/time: introduce command line option to select wallclock
    
    Allow setting the used wallclock from the command line.  When the option is set
    to a value different than `auto` the probing is bypassed and the selected
    implementation is used (as long as it's available).
    
    The `xen` and `efi` options require being booted as a Xen guest (with Xen guest
    supported built-in) or from UEFI firmware respectively.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 docs/misc/xen-command-line.pandoc | 21 ++++++++++++++++++++
 xen/arch/x86/time.c               | 41 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 08b0053f9c..9bbd00baef 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2887,6 +2887,27 @@ vwfi to `native` reduces irq latency significantly. It can also lead to
 suboptimal scheduling decisions, but only when the system is
 oversubscribed (i.e., in total there are more vCPUs than pCPUs).
 
+### wallclock (x86)
+> `= auto | xen | cmos | efi`
+
+> Default: `auto`
+
+Allow forcing the usage of a specific wallclock source.
+
+ * `auto` let the hypervisor select the clocksource based on internal
+   heuristics.
+
+ * `xen` force usage of the Xen shared_info wallclock when booted as a Xen
+   guest.  This option is only available if the hypervisor was compiled with
+   `CONFIG_XEN_GUEST` enabled.
+
+ * `cmos` force usage of the CMOS RTC wallclock.
+
+ * `efi` force usage of the EFI_GET_TIME run-time method when booted from EFI
+   firmware.
+
+If the selected option is invalid or not available Xen will default to `auto`.
+
 ### watchdog (x86)
 > `= force | <boolean>`
 
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index a9aa335d7c..00545c45fd 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1552,6 +1552,37 @@ static const char *__init wallclock_type_to_string(void)
     return "";
 }
 
+static int __init cf_check parse_wallclock(const char *arg)
+{
+    wallclock_source = WALLCLOCK_UNSET;
+
+    if ( !arg )
+        return -EINVAL;
+
+    if ( !strcmp("auto", arg) )
+        ASSERT(wallclock_source == WALLCLOCK_UNSET);
+    else if ( !strcmp("xen", arg) )
+    {
+        if ( !xen_guest )
+            return -EINVAL;
+
+        wallclock_source = WALLCLOCK_XEN;
+    }
+    else if ( !strcmp("cmos", arg) )
+        wallclock_source = WALLCLOCK_CMOS;
+    else if ( !strcmp("efi", arg) )
+        /*
+         * Checking if run-time services are available must be done after
+         * command line parsing.
+         */
+        wallclock_source = WALLCLOCK_EFI;
+    else
+        return -EINVAL;
+
+    return 0;
+}
+custom_param("wallclock", parse_wallclock);
+
 static void __init probe_wallclock(void)
 {
     ASSERT(wallclock_source == WALLCLOCK_UNSET);
@@ -2527,7 +2558,15 @@ int __init init_xen_time(void)
 
     open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
 
-    probe_wallclock();
+    /*
+     * EFI run time services can be disabled from the command line, hence the
+     * check for them cannot be done as part of the wallclock option parsing.
+     */
+    if ( wallclock_source == WALLCLOCK_EFI && !efi_enabled(EFI_RS) )
+        wallclock_source = WALLCLOCK_UNSET;
+
+    if ( wallclock_source == WALLCLOCK_UNSET )
+        probe_wallclock();
 
     printk(XENLOG_INFO "Wallclock source: %s\n", wallclock_type_to_string());
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/time: prefer CMOS over EFI_GET_TIME
Message-Id: <E1tYMqQ-008Qow-1m@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 10:11:22 +0000

commit 164ae033adb7df7cd2e7fd5b29329daceff664d2
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Sep 2 16:00:19 2024 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:03:30 2025 +0100

    x86/time: prefer CMOS over EFI_GET_TIME
    
    The EFI_GET_TIME implementation is well known to be broken for many firmware
    implementations, for Xen the result on such implementations are:
    
    ----[ Xen-4.19-unstable  x86_64  debug=y  Tainted:   C    ]----
    CPU:    0
    RIP:    e008:[<0000000062ccfa70>] 0000000062ccfa70
    [...]
    Xen call trace:
       [<0000000062ccfa70>] R 0000000062ccfa70
       [<00000000732e9a3f>] S 00000000732e9a3f
       [<ffff82d04034f34f>] F arch/x86/time.c#get_cmos_time+0x1b3/0x26e
       [<ffff82d04045926f>] F init_xen_time+0x28/0xa4
       [<ffff82d040454bc4>] F __start_xen+0x1ee7/0x2578
       [<ffff82d040203334>] F __high_start+0x94/0xa0
    
    Pagetable walk from 0000000062ccfa70:
     L4[0x000] = 000000207ef1c063 ffffffffffffffff
     L3[0x001] = 000000005d6c0063 ffffffffffffffff
     L2[0x116] = 8000000062c001e3 ffffffffffffffff (PSE)
    
    ****************************************
    Panic on CPU 0:
    FATAL PAGE FAULT
    [error_code=0011]
    Faulting linear address: 0000000062ccfa70
    ****************************************
    
    Swap the preference to default to CMOS first, and EFI later, in an attempt to
    use EFI_GET_TIME as a last resort option only.  Note that Linux for example
    doesn't allow calling the get_time method, and instead provides a dummy handler
    that unconditionally returns EFI_UNSUPPORTED on x86-64.
    
    Such change in the preferences requires some re-arranging of the function
    logic, so that panic messages with workaround suggestions are suitably printed.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Acked-By: Oleksii Kurochko<oleksii.kurochko@gmail.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 CHANGELOG.md        | 2 ++
 xen/arch/x86/time.c | 8 ++++----
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8507e6556a..1de1d1eca1 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -12,6 +12,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    leaving this to the guest kernel to do in guest context.
  - On x86:
    - Prefer ACPI reboot over UEFI ResetSystem() run time service call.
+   - Prefer CMOS over EFI_GET_TIME as time source.
    - Switched the xAPIC flat driver to use physical destination mode for external
      interrupts instead of logical destination mode.
 
@@ -24,6 +25,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Support for LLC (Last Level Cache) coloring.
  - On x86:
    - xl suspend/resume subcommands.
+   - `wallclock` command line option to select time source.
 
 ### Removed
  - On x86:
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 00545c45fd..59129f419d 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1592,14 +1592,14 @@ static void __init probe_wallclock(void)
         wallclock_source = WALLCLOCK_XEN;
         return;
     }
-    if ( efi_enabled(EFI_RS) && efi_get_time() )
+    if ( cmos_rtc_probe() )
     {
-        wallclock_source = WALLCLOCK_EFI;
+        wallclock_source = WALLCLOCK_CMOS;
         return;
     }
-    if ( cmos_rtc_probe() )
+    if ( efi_enabled(EFI_RS) && efi_get_time() )
     {
-        wallclock_source = WALLCLOCK_CMOS;
+        wallclock_source = WALLCLOCK_EFI;
         return;
     }
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] automation/gitlab: disable coverage from clang randconfig
Message-Id: <E1tYMqa-008QpI-25@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 10:11:32 +0000

commit 9ee63ef5407d9678daae210fc1244deaaedc8f73
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue Jan 14 15:10:14 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Thu Jan 16 09:30:14 2025 +0100

    automation/gitlab: disable coverage from clang randconfig
    
    If randconfig enables coverage support the build times out due to GNU LD
    taking too long.  For the time being prevent coverage from being enabled in
    clang randconfig job.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 automation/gitlab-ci/build.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index cb84f379b7..bc4a8a5ad2 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -556,6 +556,8 @@ debian-12-x86_64-clang-randconfig:
   variables:
     CONTAINER: debian:12-x86_64
     RANDCONFIG: y
+    EXTRA_FIXED_RANDCONFIG: |
+      CONFIG_COVERAGE=n # Disable coverage otherwise build times out.
 
 debian-12-x86_64-gcc:
   extends: .gcc-x86-64-build
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs/sphinx: import sys for error reporting
Message-Id: <E1tYO7U-008a0x-30@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:04 +0000

commit f79af67982ef26e0395d81baff39d10705dedcda
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/sphinx: import sys for error reporting
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/conf.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/conf.py b/docs/conf.py
index 5d2e979449..2fb8bafe65 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -6,6 +6,8 @@
 # For the full list of built-in configuration values, see the documentation:
 # https://www.sphinx-doc.org/en/master/usage/configuration.html
 
+import sys
+
 # -- Path setup --------------------------------------------------------------
 
 # If extensions (or modules to document with autodoc) are in another directory,
@@ -13,7 +15,6 @@
 # documentation root, use os.path.abspath to make it absolute, like shown here.
 #
 # import os
-# import sys
 # sys.path.insert(0, os.path.abspath('.'))
 
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs: rationalise .gitignore
Message-Id: <E1tYO7f-008a1l-0D@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:15 +0000

commit 0edb30455b8827dc62a452e45aa0f8b54b847db7
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs: rationalise .gitignore
    
    Note I did not transplant the patterns under doc/txt/ (since the whole
    dir is ignored already), and adjusted sort order to be fully
    alphabetical.
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 .gitignore      | 17 -----------------
 docs/.gitignore | 10 ++++++++++
 2 files changed, 10 insertions(+), 17 deletions(-)

diff --git a/.gitignore b/.gitignore
index 25484a8fd8..53f5df0003 100644
--- a/.gitignore
+++ b/.gitignore
@@ -50,19 +50,6 @@ config/Toplevel.mk
 config/Paths.mk
 
 dist/*
-docs/tmp.*
-docs/html/
-docs/man/xl.cfg.5.pod
-docs/man/xl-disk-configuration.5.pod
-docs/man/xl-network-configuration.5.pod
-docs/man/xl.1.pod
-docs/man/xl.conf.5.pod
-docs/man1/
-docs/man5/
-docs/man7/
-docs/man8/
-docs/pdf/
-docs/txt/
 extras/
 install/*
 
@@ -302,7 +289,3 @@ tools/debugger/kdd/kdd
 tools/firmware/etherboot/ipxe.tar.gz
 tools/firmware/etherboot/ipxe/
 tools/xl/xl
-
-docs/txt/misc/*.txt
-docs/txt/man/*.txt
-docs/figs/*.png
diff --git a/docs/.gitignore b/docs/.gitignore
new file mode 100644
index 0000000000..ded597cab8
--- /dev/null
+++ b/docs/.gitignore
@@ -0,0 +1,10 @@
+/figs/*.png
+/html/
+/man/xl.cfg.5.pod
+/man/xl-disk-configuration.5.pod
+/man/xl-network-configuration.5.pod
+/man/xl.1.pod
+/man/xl.conf.5.pod
+/man[1-9]/
+/pdf/
+/txt/
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs/sphinx: gitignore generated files
Message-Id: <E1tYO7p-008a2j-0h@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:25 +0000

commit 6b97c31146d8f3a3cc1491035b5d0fdede43e088
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/sphinx: gitignore generated files
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/.gitignore b/docs/.gitignore
index ded597cab8..c3ce50335a 100644
--- a/docs/.gitignore
+++ b/docs/.gitignore
@@ -7,4 +7,5 @@
 /man/xl.conf.5.pod
 /man[1-9]/
 /pdf/
+/sphinx/
 /txt/
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/ppc: Fix double xen_ulong_t typedef in public/arch-ppc.h
Message-Id: <E1tYO7z-008a3k-14@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:35 +0000

commit 22d7141d2e39e5e7f28e448dc916abe1b09a8690
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Jan 15 14:22:21 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    xen/ppc: Fix double xen_ulong_t typedef in public/arch-ppc.h
    
    public/arch-ppc.h contains two adjacent #ifndef __ASSEMBLY__ blocks.
    
    With these merged, it becomes very obvious that there's a duplicate
    definition of xen_ulong_t, which is also noticed by the docs build:
    
      /usr/bin/perl -w /local/xen.git/docs/xen-headers -O html/hypercall/ppc \
              -T 'arch-ppc - Xen public headers' \
              -X arch-arm -X arch-riscv -X arch-x86_32 -X arch-x86_64 \
              -X xen-arm -X xen-riscv -X xen-x86_32 -X xen-x86_64 \
              -X arch-x86 \
              /local/xen.git/docs/../xen include/public include/xen/errno.h
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:55
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:61
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:61
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:55
    
    Drop the second typedef.  Finally, annotate the #endif so it's clear
    what it refers to.
    
    Fixes: 08c192cc1127 ("xen/ppc: Add public/arch-ppc.h")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Shawn Anastasio <sanastasio@raptorengineering.com>
---
 xen/include/public/arch-ppc.h | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/xen/include/public/arch-ppc.h b/xen/include/public/arch-ppc.h
index 33a24e3795..4ca453a284 100644
--- a/xen/include/public/arch-ppc.h
+++ b/xen/include/public/arch-ppc.h
@@ -54,11 +54,6 @@ typedef uint64_t xen_pfn_t;
 
 typedef uint64_t xen_ulong_t;
 #define PRI_xen_ulong PRIx64
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef uint64_t xen_ulong_t;
 
 /*
  * User-accessible registers: most of these need to be saved/restored
@@ -107,6 +102,6 @@ struct xen_arch_domainconfig {
 
 typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t;
 
-#endif
+#endif /* !__ASSEMBLY__ */
 
 #endif /* __XEN_PUBLIC_ARCH_PPC_H__ */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs: Fix some typos in the design docs
Message-Id: <E1tYO89-008a4j-1S@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:45 +0000

commit f0f1050d47b4abbececfcf16b757e470f3fff46d
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 14:44:55 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs: Fix some typos in the design docs
    
    Skimming through the design docs, I saw some typos that needed fixing.
    
    Reviewed-by: Frediano Ziglio <frediano.ziglio@cloud.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/designs/argo.pandoc                |  6 +++---
 docs/designs/nested-svm-cpu-features.md | 14 +++++++-------
 docs/designs/qemu-deprivilege.md        | 12 ++++++------
 docs/designs/xenstore-migration.md      |  2 +-
 docs/features/qemu-deprivilege.pandoc   |  2 +-
 5 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/docs/designs/argo.pandoc b/docs/designs/argo.pandoc
index e18aacea7c..6651427cd2 100644
--- a/docs/designs/argo.pandoc
+++ b/docs/designs/argo.pandoc
@@ -58,7 +58,7 @@ concurrency.
 
 Avoidance of deadlock is essential and since state must frequently be updated
 that pertains to more than one domain, a locking protocol defines which locks
-are needed and the order of their acquistion.
+are needed and the order of their acquisition.
 
 ## Structure
 
@@ -127,7 +127,7 @@ by the domain.
 
 ## Hierarchical Locking Model and Protocol
 
-The locking discipline within the Argo code is heirarchical and utilizes
+The locking discipline within the Argo code is hierarchical and utilizes
 reader/writer locks to enable increased concurrency when operations do not
 conflict. None of the Argo locks are reentrant.
 
@@ -283,7 +283,7 @@ state for a domain's own registered ring.
 
 ## Reasoning Model
 
-A common model for reasoning about concurrent code focusses on accesses to
+A common model for reasoning about concurrent code focuses on accesses to
 individual variables: if code touches this variable, see that it first acquires
 the corresponding lock and then drops it afterwards. A challenge with this
 model is in ensuring that the sequence of locks acquired within nested
diff --git a/docs/designs/nested-svm-cpu-features.md b/docs/designs/nested-svm-cpu-features.md
index 837a96df05..ce168e68e1 100644
--- a/docs/designs/nested-svm-cpu-features.md
+++ b/docs/designs/nested-svm-cpu-features.md
@@ -22,7 +22,7 @@ leaf 8000000A:edx
   from the L1 hypervisor's perspective to be as close as possible to
   the original hardware.  In particular, the behavior of the hardware
   on error paths 1) is not easy to understand or test, 2) can be the
-  source of surprising vulnerabiliies.  (See XSA-7 for an example of a
+  source of surprising vulnerabilities.  (See XSA-7 for an example of a
   case where subtle error-handling differences can open up a privilege
   escalation.)  We should avoid emulating any bit of the hardware with
   complex error paths if we can at all help it.
@@ -59,11 +59,11 @@ leaf 8000000A:edx
 
 - 2 `SVML` *SVM Lock*: Not required for L0, not provided to L1
 
-  Seems to be aboult enabling an operating system to prevent "blue
+  Seems to be about enabling an operating system to prevent "blue
   pill" attacks against itself.
 
   Xen doesn't use it, nor provide it; so it would need to be
-  implementend.  The best way to protect a guest OS is to leave nested
+  implemented.  The best way to protect a guest OS is to leave nested
   virt disabled in the tools.
 
 - 3 `NRIPS` NRIP Save: Require for both L0 and L1
@@ -78,8 +78,8 @@ leaf 8000000A:edx
   The main putative use for this would be trying to maintain an
   invariant TSC across cores with different clock speeds, or after a
   migrate.  Unlike others, this doesn't have an error path to worry
-  about compatibility-wise; and according to tests done when nestedSVM
-  was first implemented, it's actually faster to emliate TscRateMSR in
+  about compatibility-wise; and according to tests done when nested SVM
+  was first implemented, it's actually faster to emulate TscRateMSR in
   the L0 hypervisor than for L1 to attempt to emulate it itself.
 
   However, using this properly in L0 will take some implementation
@@ -89,7 +89,7 @@ leaf 8000000A:edx
  - 5 `VmcbClean`: VMCB Clean Bits: Not required by L0, provide to L1
 
   This is a pure optimization, both on the side of the L0 and L1.  The
-  implementaiton for L1 is entirely Xen-side, so can be provided even
+  implementation for L1 is entirely Xen-side, so can be provided even
   on hardware that doesn't provide it.  And it's purely an
   optimization, so could be "implemented" by ignoring the bits
   entirely.
@@ -102,7 +102,7 @@ leaf 8000000A:edx
 - 6 `FlushByAsid`: Require for L0, provide to L1
 
   This is cheap and easy to use for L0 and to provide to the L1;
-  there's no reson not to just pass it through.
+  there's no reason not to just pass it through.
 
 - 7 `DecodeAssists`: Require for L0, provide to L1
 
diff --git a/docs/designs/qemu-deprivilege.md b/docs/designs/qemu-deprivilege.md
index f12b1a3ae3..d593fe8e37 100644
--- a/docs/designs/qemu-deprivilege.md
+++ b/docs/designs/qemu-deprivilege.md
@@ -22,7 +22,7 @@ The following restrictions are currently implemented.
 '''Description''': As mentioned above, having QEMU switch to a
 non-root user, one per domain id.  Not being the root user limits what
 a compromised QEMU process can do to the system, and having one user
-per domain id limits what a comprimised QEMU process can do to the
+per domain id limits what a compromised QEMU process can do to the
 QEMU processes of other VMs.
 
 '''Implementation''': The toolstack adds the following to the qemu command-line:
@@ -79,8 +79,8 @@ Then adds the following to the qemu command-line:
 ## Namespaces for unused functionality (Linux only)
 
 '''Description''': QEMU doesn't use the functionality associated with
-mount and IPC namespaces. (IPC namespaces contol non-file-based IPC
-mechanisms within the kernel; unix and network sockets are not
+mount and IPC namespaces. (IPC namespaces control non-file-based IPC
+mechanisms within the kernel; Unix and network sockets are not
 affected by this.)  Making separate namespaces for these for QEMU
 won't affect normal operation, but it does mean that even if other
 restrictions fail, the process won't be able to even name system mount
@@ -179,7 +179,7 @@ being killed by the target process:
             kill(-1, 9);
     }
 
-Fortunately there is an assymetry we can take advantage of.  From the
+Fortunately there is an asymmetry we can take advantage of.  From the
 POSIX spec:
 
 > For a process to have permission to send a signal to a process
@@ -220,7 +220,7 @@ RLIMIT_NPROC limits total number of processes or threads.  QEMU uses
 threads for some devices, so this would require some thought.
 
 Other things that would take some cleverness / changes to QEMU to
-utilize due to ordering constrants:
+utilize due to ordering constraints:
  - RLIMIT_NOFILES (after all necessary files are opened)
 
 ## libxl: Treat QMP connection as untrusted
@@ -251,7 +251,7 @@ executing QEMU.  (But this would then require other changes to create
 the QMP socket, VNC socket, and so on).
 
 It should be noted that `-sandbox` is implemented as a blacklist, not
-a whitelist; that is, it disables known-unsed functionality which may
+a whitelist; that is, it disables known-unused functionality which may
 be harmful, rather than disabling all functionality except that known
 to be safe and needed.  This is unfortunately necessary since qemu
 doesn't know what system calls libraries might end up making.  (See
diff --git a/docs/designs/xenstore-migration.md b/docs/designs/xenstore-migration.md
index 5022268386..082314bf72 100644
--- a/docs/designs/xenstore-migration.md
+++ b/docs/designs/xenstore-migration.md
@@ -372,7 +372,7 @@ or modified by a transaction for which there is also a `TRANSACTION_DATA`
 record previously present).
 
 Each _committed_ node in the stream is required to have an already known parent
-node. A parent node is known if it was either in the node data base before the
+node. A parent node is known if it was either in the node database before the
 stream was started to be processed, or if a `NODE_DATA` record for that parent
 node has already been processed in the stream.
 
diff --git a/docs/features/qemu-deprivilege.pandoc b/docs/features/qemu-deprivilege.pandoc
index 4ef119c821..915e38d8c9 100644
--- a/docs/features/qemu-deprivilege.pandoc
+++ b/docs/features/qemu-deprivilege.pandoc
@@ -25,7 +25,7 @@ dm_restrict is a set of operations to restrict QEMU running in domain
 
  1. Mechanisms to restrict QEMU to only being able to affect its own
 domain
- 2. Mechanisms to restruct QEMU's ability to interact with domain 0.
+ 2. Mechanisms to restrict QEMU's ability to interact with domain 0.
 
 # User details
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs/misc: Fix a few typos
Message-Id: <E1tYO8J-008a5G-1k@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 11:33:55 +0000

commit a29a1fb5a5b213ce972c925c84c52bebad4d34b7
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 16:09:04 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/misc: Fix a few typos
    
    While skimming through the misc docs, I spotted a few typos.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/misc/livepatch.pandoc            | 44 +++++++++++++++++------------------
 docs/misc/netif-staging-grants.pandoc | 20 ++++++++--------
 docs/misc/printk-formats.txt          |  2 +-
 3 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/docs/misc/livepatch.pandoc b/docs/misc/livepatch.pandoc
index 4a0b4fd6d8..04dd5ed7b2 100644
--- a/docs/misc/livepatch.pandoc
+++ b/docs/misc/livepatch.pandoc
@@ -25,7 +25,7 @@ The document is split in four sections:
  * reloc - telemetries contained in the payload to construct proper trampoline.
  * hook - an auxiliary function being called before, during or after payload
           application or revert.
- * quiescing zone - period when all CPUs are lock-step with each other.
+ * quiescent zone - period when all CPUs are lock-step with each other.
 
 ## History
 
@@ -267,7 +267,7 @@ It may also have some architecture-specific sections. For example:
  * Relocations for each of these sections.
 
 The Xen Live Patch core code loads the payload as a standard ELF binary, relocates it
-and handles the architecture-specifc sections as needed. This process is much
+and handles the architecture-specific sections as needed. This process is much
 like what the Linux kernel module loader does.
 
 The payload contains at least three sections:
@@ -372,7 +372,7 @@ and the core code copies the data from the undo buffer (private internal copy)
 to `old_addr`.
 
 It optionally may contain the address of hooks to be called right before
-being applied and after being reverted (while all CPUs are still in quiescing
+being applied and after being reverted (while all CPUs are still in quiescent
 zone). These hooks do not have access to payload structure.
 
  * `.livepatch.hooks.load` - an array of function pointers.
@@ -380,7 +380,7 @@ zone). These hooks do not have access to payload structure.
 
 It optionally may also contain the address of pre- and post- vetoing hooks to
 be called before (pre) or after (post) apply and revert payload actions (while
-all CPUs are already released from quiescing zone). These hooks do have
+all CPUs are already released from quiescent zone). These hooks do have
 access to payload structure. The pre-apply hook can prevent from loading the
 payload if encoded in it condition is not met. Accordingly, the pre-revert
 hook can prevent from unloading the livepatch if encoded in it condition is not
@@ -392,7 +392,7 @@ met.
 
 Finally, it optionally may also contain the address of apply or revert action
 hooks to be called instead of the default apply and revert payload actions
-(while all CPUs are kept in quiescing zone). These hooks do have access to
+(while all CPUs are kept in quiescent zone). These hooks do have access to
 payload structure.
 
  * `.livepatch.hooks.{apply,revert}`
@@ -463,7 +463,7 @@ The type definition of the function are as follow:
 
 This section contains a pointer to a single function pointer to be executed
 before apply action is scheduled (and thereby before CPUs are put into
-quiescing zone). This is useful to prevent from applying a payload when
+quiescent zone). This is useful to prevent from applying a payload when
 certain expected conditions aren't met or when mutating actions implemented
 in the hook fail or cannot be executed.
 This type of hooks do have access to payload structure.
@@ -477,7 +477,7 @@ The type definition of the function are as follow:
 #### .livepatch.hooks.postapply
 
 This section contains a pointer to a single function pointer to be executed
-after apply action has finished and after all CPUs left the quiescing zone.
+after apply action has finished and after all CPUs left the quiescent zone.
 This is useful to provide an ability to follow up on actions performed by
 the preapply hook. Especially, when module application was successful or to
 be able to undo certain preparation steps of the preapply hook in case of a
@@ -495,7 +495,7 @@ The type definition of the function are as follow:
 
 This section contains a pointer to a single function pointer to be executed
 before revert action is scheduled (and thereby before CPUs are put into
-quiescing zone). This is useful to prevent from reverting a payload when
+quiescent zone). This is useful to prevent from reverting a payload when
 certain expected conditions aren't met or when mutating actions implemented
 in the hook fail or cannot be executed.
 This type of hooks do have access to payload structure.
@@ -509,7 +509,7 @@ The type definition of the function are as follow:
 #### .livepatch.hooks.postrevert
 
 This section contains a pointer to a single function pointer to be executed
-after revert action has finished and after all CPUs left the quiescing zone.
+after revert action has finished and after all CPUs left the quiescent zone.
 This is useful to provide an ability to perform cleanup of all previously
 executed mutating actions in order to restore the original system state from
 before the current payload application. The success/failure error code is
@@ -527,7 +527,7 @@ The type definition of the function are as follow:
 This section contains a pointer to a single function pointer to be executed
 instead of a default apply (or revert) action function. This is useful to
 replace or augment default behavior of the apply (or revert) action that
-requires all CPUs to be in the quiescing zone.
+requires all CPUs to be in the quiescent zone.
 This type of hooks do have access to payload structure.
 
 Each entry in this array is eight bytes.
@@ -539,13 +539,13 @@ The type definition of the function are as follow:
 ### .livepatch.xen_depends, .livepatch.depends and .note.gnu.build-id
 
 To support dependencies checking and safe loading (to load the
-appropiate payload against the right hypervisor) there is a need
-to embbed an build-id dependency.
+appropriate payload against the right hypervisor) there is a need
+to embed a build-id dependency.
 
 This is done by the payload containing sections `.livepatch.xen_depends`
 and `.livepatch.depends` which follow the format of an ELF Note.
 The contents of these (name, and description) are specific to the linker
-utilized to build the hypevisor and payload.
+utilized to build the hypervisor and payload.
 
 If GNU linker is used then the name is `GNU` and the description
 is a NT_GNU_BUILD_ID type ID. The description can be an SHA1
@@ -639,7 +639,7 @@ The `name` could be an UUID that stays fixed forever for a given
 payload. It can be embedded into the ELF payload at creation time
 and extracted by tools.
 
-The return value is zero if the payload was succesfully uploaded.
+The return value is zero if the payload was successfully uploaded.
 Otherwise an -XEN_EXX return value is provided. Duplicate `name` are not supported.
 
 The `payload` is the ELF payload as mentioned in the `Payload format` section.
@@ -819,7 +819,7 @@ The caller provides:
  * `cmd` The command requested:
   * *LIVEPATCH_ACTION_UNLOAD* (1) Unload the payload.
    Any further hypercalls against the `name` will result in failure unless
-   **XEN_SYSCTL_LIVEPATCH_UPLOAD** hypercall is perfomed with same `name`.
+   **XEN_SYSCTL_LIVEPATCH_UPLOAD** hypercall is performed with same `name`.
   * *LIVEPATCH_ACTION_REVERT* (2) Revert the payload. If the operation takes
   more time than the upper bound of time the `rc` in `xen_livepatch_status`
   retrieved via **XEN_SYSCTL_LIVEPATCH_GET** will be -XEN_EBUSY.
@@ -969,7 +969,7 @@ Before we call VMXResume we check whether any soft IRQs need to be executed.
 This is a good spot because all Xen stacks are effectively empty at
 that point.
 
-To randezvous all the CPUs an barrier with an maximum timeout (which
+To rendezvous all the CPUs an barrier with an maximum timeout (which
 could be adjusted), combined with forcing all other CPUs through the
 hypervisor with IPIs, can be utilized to execute lockstep instructions
 on all CPUs.
@@ -990,7 +990,7 @@ be done to the linker scripts to support this.
 
 The design of that is not discussed in this design.
 
-This is implemented in a seperate tool which lives in a seperate
+This is implemented in a separate tool which lives in a separate
 GIT repo.
 
 Currently it resides at https://xenbits.xen.org/git-http/livepatch-build-tools.git
@@ -1066,17 +1066,17 @@ There are the ways this can be addressed:
    grows to accumulate all the code changes.
  * Hotpatch stack - where an mechanism exists that loads the hotpatches
    in the same order they were built in. We would need an build-id
-   of the hypevisor to make sure the hot-patches are build against the
+   of the hypervisor to make sure the hot-patches are build against the
    correct build.
  * Payload containing the old code to check against that. That allows
-   the hotpatches to be loaded indepedently (if they don't overlap) - or
-   if the old code also containst previously patched code - even if they
+   the hotpatches to be loaded independently (if they don't overlap) - or
+   if the old code also contains previously patched code - even if they
    overlap.
 
 The disadvantage of the first large patch is that it can grow over
 time and not provide an bisection mechanism to identify faulty patches.
 
-The hot-patch stack puts stricts requirements on the order of the patches
+The hot-patch stack puts strict requirements on the order of the patches
 being loaded and requires an hypervisor build-id to match against.
 
 The old code allows much more flexibility and an additional guard,
@@ -1263,7 +1263,7 @@ limit that calls the next trampoline.
 
 Please note there is a small limitation for trampolines in
 function entries: The target function (+ trailing padding) must be able
-to accomodate the trampoline. On x86 with +-2 GB relative jumps,
+to accommodate the trampoline. On x86 with +-2 GB relative jumps,
 this means 5 bytes are required which means that `old_size` **MUST** be
 at least five bytes if patching in trampoline.
 
diff --git a/docs/misc/netif-staging-grants.pandoc b/docs/misc/netif-staging-grants.pandoc
index cb33028adc..838b115840 100644
--- a/docs/misc/netif-staging-grants.pandoc
+++ b/docs/misc/netif-staging-grants.pandoc
@@ -9,7 +9,7 @@ Architecture(s): Any
 
 # Background and Motivation
 
-At the Xen hackaton '16 networking session, we spoke about having a permanently
+At the Xen hackathon '16 networking session, we spoke about having a permanently
 mapped region to describe header/linear region of packet buffers. This document
 outlines the proposal covering motivation of this and applicability for other
 use-cases alongside the necessary changes.
@@ -174,8 +174,8 @@ boundary
 
 17) Allocate packet metadata
 
-[ *Linux specific*: This structure emcompasses a linear data region which
-generally accomodates the protocol header and such. Netback allocates up to 128
+[ *Linux specific*: This structure encompasses a linear data region which
+generally accommodates the protocol header and such. Netback allocates up to 128
 bytes for that. ]
 
 18) *Linux specific*: Setup up a `GNTTABOP_copy` to copy up to 128 bytes to this small
@@ -317,7 +317,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
  process the actual like the steps below. This thread has the purpose of
  aggregating as much copies as possible.]
 
-2) Checks if there are enough rx ring slots that can accomodate the packet.
+2) Checks if there are enough rx ring slots that can accommodate the packet.
 
 3) Gets a request from the ring for the first data slot and fetches the `gref`
    from it.
@@ -375,7 +375,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
 
 24) Call packet into the network stack.
 
-25) Allocate new pages and any necessary packet metadata strutures to new
+25) Allocate new pages and any necessary packet metadata structures to new
     requests. These requests will then be used in step 1) and so forth.
 
 26) Update the request producer index (`req_prod`)
@@ -391,7 +391,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
 
 This proposal aims at replacing step 4), 12) and  22) with memcpy if the
 grefs on the Rx ring were requested to be mapped by the guest. Frontend may use
-strategies to allow fast recycling of grants for replinishing the ring,
+strategies to allow fast recycling of grants for replenishing the ring,
 hence letting Domain-0 replace the grant copies with  memcpy instead, which is
 faster.
 
@@ -400,8 +400,8 @@ would need to aggregate as much as grant ops as possible (step 1) and could
 transmit the packet on the transmit function (e.g. Linux ```ndo_start_xmit```)
 as previously proposed
 here\[[0](http://lists.xenproject.org/archives/html/xen-devel/2015-05/msg01504.html)\].
-This would heavily improve efficiency specifially for smaller packets. Which in
-return would decrease RTT, having data being acknoledged much quicker.
+This would heavily improve efficiency specifically for smaller packets. Which in
+return would decrease RTT, having data being acknowledged much quicker.
 
 \clearpage
 
@@ -467,13 +467,13 @@ The entry 'status' field determines if the entry was successfully removed.
 Control ring is only available after backend state is `XenbusConnected`
 therefore only on this state change can the frontend query the total amount of
 maps it can keep. It then grants N entries per queue on both TX and RX ring
-which will create the underying backend gref -> page association (e.g.  stored
+which will create the underlying backend gref -> page association (e.g.  stored
 in hash table). Frontend may wish to recycle these pregranted buffers or choose
 a copy approach to replace granting.
 
 On steps 19) of Guest Transmit and 3) of Guest Receive, data gref is first
 looked up in this table and uses the underlying page if it already exists a
-mapping. On the successfull cases, steps 20) 21) and 27) of Guest Transmit are
+mapping. On the successful cases, steps 20) 21) and 27) of Guest Transmit are
 skipped, with 19) being replaced with a memcpy of up to 128 bytes. On Guest
 Receive, 4) 12) and 22) are replaced with memcpy instead of a grant copy.
 
diff --git a/docs/misc/printk-formats.txt b/docs/misc/printk-formats.txt
index 8f666f696a..ce32829dae 100644
--- a/docs/misc/printk-formats.txt
+++ b/docs/misc/printk-formats.txt
@@ -11,7 +11,7 @@ Raw buffer as hex string:
        %*phN   000102 ... 3f
 
        Up to 64 characters.  Buffer length expected via the field_width
-       paramter. i.e. printk("%*ph", 8, buffer);
+       parameter. i.e. printk("%*ph", 8, buffer);
 
 Bitmaps (e.g. cpumask/nodemask):
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs/sphinx: import sys for error reporting
Message-Id: <E1tYOiE-008eJD-08@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:02 +0000

commit f79af67982ef26e0395d81baff39d10705dedcda
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/sphinx: import sys for error reporting
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/conf.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/conf.py b/docs/conf.py
index 5d2e979449..2fb8bafe65 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -6,6 +6,8 @@
 # For the full list of built-in configuration values, see the documentation:
 # https://www.sphinx-doc.org/en/master/usage/configuration.html
 
+import sys
+
 # -- Path setup --------------------------------------------------------------
 
 # If extensions (or modules to document with autodoc) are in another directory,
@@ -13,7 +15,6 @@
 # documentation root, use os.path.abspath to make it absolute, like shown here.
 #
 # import os
-# import sys
 # sys.path.insert(0, os.path.abspath('.'))
 
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs: rationalise .gitignore
Message-Id: <E1tYOiO-008eKs-0Z@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:12 +0000

commit 0edb30455b8827dc62a452e45aa0f8b54b847db7
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs: rationalise .gitignore
    
    Note I did not transplant the patterns under doc/txt/ (since the whole
    dir is ignored already), and adjusted sort order to be fully
    alphabetical.
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 .gitignore      | 17 -----------------
 docs/.gitignore | 10 ++++++++++
 2 files changed, 10 insertions(+), 17 deletions(-)

diff --git a/.gitignore b/.gitignore
index 25484a8fd8..53f5df0003 100644
--- a/.gitignore
+++ b/.gitignore
@@ -50,19 +50,6 @@ config/Toplevel.mk
 config/Paths.mk
 
 dist/*
-docs/tmp.*
-docs/html/
-docs/man/xl.cfg.5.pod
-docs/man/xl-disk-configuration.5.pod
-docs/man/xl-network-configuration.5.pod
-docs/man/xl.1.pod
-docs/man/xl.conf.5.pod
-docs/man1/
-docs/man5/
-docs/man7/
-docs/man8/
-docs/pdf/
-docs/txt/
 extras/
 install/*
 
@@ -302,7 +289,3 @@ tools/debugger/kdd/kdd
 tools/firmware/etherboot/ipxe.tar.gz
 tools/firmware/etherboot/ipxe/
 tools/xl/xl
-
-docs/txt/misc/*.txt
-docs/txt/man/*.txt
-docs/figs/*.png
diff --git a/docs/.gitignore b/docs/.gitignore
new file mode 100644
index 0000000000..ded597cab8
--- /dev/null
+++ b/docs/.gitignore
@@ -0,0 +1,10 @@
+/figs/*.png
+/html/
+/man/xl.cfg.5.pod
+/man/xl-disk-configuration.5.pod
+/man/xl-network-configuration.5.pod
+/man/xl.1.pod
+/man/xl.conf.5.pod
+/man[1-9]/
+/pdf/
+/txt/
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs/sphinx: gitignore generated files
Message-Id: <E1tYOiY-008ePc-0u@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:22 +0000

commit 6b97c31146d8f3a3cc1491035b5d0fdede43e088
Author:     Yann Dirson <yann.dirson@vates.tech>
AuthorDate: Wed Jan 15 12:27:56 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/sphinx: gitignore generated files
    
    Signed-off-by: Yann Dirson <yann.dirson@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/.gitignore b/docs/.gitignore
index ded597cab8..c3ce50335a 100644
--- a/docs/.gitignore
+++ b/docs/.gitignore
@@ -7,4 +7,5 @@
 /man/xl.conf.5.pod
 /man[1-9]/
 /pdf/
+/sphinx/
 /txt/
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/ppc: Fix double xen_ulong_t typedef in public/arch-ppc.h
Message-Id: <E1tYOii-008eRY-1B@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:32 +0000

commit 22d7141d2e39e5e7f28e448dc916abe1b09a8690
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Jan 15 14:22:21 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    xen/ppc: Fix double xen_ulong_t typedef in public/arch-ppc.h
    
    public/arch-ppc.h contains two adjacent #ifndef __ASSEMBLY__ blocks.
    
    With these merged, it becomes very obvious that there's a duplicate
    definition of xen_ulong_t, which is also noticed by the docs build:
    
      /usr/bin/perl -w /local/xen.git/docs/xen-headers -O html/hypercall/ppc \
              -T 'arch-ppc - Xen public headers' \
              -X arch-arm -X arch-riscv -X arch-x86_32 -X arch-x86_64 \
              -X xen-arm -X xen-riscv -X xen-x86_32 -X xen-x86_64 \
              -X arch-x86 \
              /local/xen.git/docs/../xen include/public include/xen/errno.h
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:55
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:61
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:61
      include/public/memory.h:63: multiple definitions of Typedef xen_ulong_t: include/public/arch-ppc.h:55
    
    Drop the second typedef.  Finally, annotate the #endif so it's clear
    what it refers to.
    
    Fixes: 08c192cc1127 ("xen/ppc: Add public/arch-ppc.h")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Shawn Anastasio <sanastasio@raptorengineering.com>
---
 xen/include/public/arch-ppc.h | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/xen/include/public/arch-ppc.h b/xen/include/public/arch-ppc.h
index 33a24e3795..4ca453a284 100644
--- a/xen/include/public/arch-ppc.h
+++ b/xen/include/public/arch-ppc.h
@@ -54,11 +54,6 @@ typedef uint64_t xen_pfn_t;
 
 typedef uint64_t xen_ulong_t;
 #define PRI_xen_ulong PRIx64
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef uint64_t xen_ulong_t;
 
 /*
  * User-accessible registers: most of these need to be saved/restored
@@ -107,6 +102,6 @@ struct xen_arch_domainconfig {
 
 typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t;
 
-#endif
+#endif /* !__ASSEMBLY__ */
 
 #endif /* __XEN_PUBLIC_ARCH_PPC_H__ */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs: Fix some typos in the design docs
Message-Id: <E1tYOis-008eTK-1b@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:42 +0000

commit f0f1050d47b4abbececfcf16b757e470f3fff46d
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 14:44:55 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs: Fix some typos in the design docs
    
    Skimming through the design docs, I saw some typos that needed fixing.
    
    Reviewed-by: Frediano Ziglio <frediano.ziglio@cloud.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/designs/argo.pandoc                |  6 +++---
 docs/designs/nested-svm-cpu-features.md | 14 +++++++-------
 docs/designs/qemu-deprivilege.md        | 12 ++++++------
 docs/designs/xenstore-migration.md      |  2 +-
 docs/features/qemu-deprivilege.pandoc   |  2 +-
 5 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/docs/designs/argo.pandoc b/docs/designs/argo.pandoc
index e18aacea7c..6651427cd2 100644
--- a/docs/designs/argo.pandoc
+++ b/docs/designs/argo.pandoc
@@ -58,7 +58,7 @@ concurrency.
 
 Avoidance of deadlock is essential and since state must frequently be updated
 that pertains to more than one domain, a locking protocol defines which locks
-are needed and the order of their acquistion.
+are needed and the order of their acquisition.
 
 ## Structure
 
@@ -127,7 +127,7 @@ by the domain.
 
 ## Hierarchical Locking Model and Protocol
 
-The locking discipline within the Argo code is heirarchical and utilizes
+The locking discipline within the Argo code is hierarchical and utilizes
 reader/writer locks to enable increased concurrency when operations do not
 conflict. None of the Argo locks are reentrant.
 
@@ -283,7 +283,7 @@ state for a domain's own registered ring.
 
 ## Reasoning Model
 
-A common model for reasoning about concurrent code focusses on accesses to
+A common model for reasoning about concurrent code focuses on accesses to
 individual variables: if code touches this variable, see that it first acquires
 the corresponding lock and then drops it afterwards. A challenge with this
 model is in ensuring that the sequence of locks acquired within nested
diff --git a/docs/designs/nested-svm-cpu-features.md b/docs/designs/nested-svm-cpu-features.md
index 837a96df05..ce168e68e1 100644
--- a/docs/designs/nested-svm-cpu-features.md
+++ b/docs/designs/nested-svm-cpu-features.md
@@ -22,7 +22,7 @@ leaf 8000000A:edx
   from the L1 hypervisor's perspective to be as close as possible to
   the original hardware.  In particular, the behavior of the hardware
   on error paths 1) is not easy to understand or test, 2) can be the
-  source of surprising vulnerabiliies.  (See XSA-7 for an example of a
+  source of surprising vulnerabilities.  (See XSA-7 for an example of a
   case where subtle error-handling differences can open up a privilege
   escalation.)  We should avoid emulating any bit of the hardware with
   complex error paths if we can at all help it.
@@ -59,11 +59,11 @@ leaf 8000000A:edx
 
 - 2 `SVML` *SVM Lock*: Not required for L0, not provided to L1
 
-  Seems to be aboult enabling an operating system to prevent "blue
+  Seems to be about enabling an operating system to prevent "blue
   pill" attacks against itself.
 
   Xen doesn't use it, nor provide it; so it would need to be
-  implementend.  The best way to protect a guest OS is to leave nested
+  implemented.  The best way to protect a guest OS is to leave nested
   virt disabled in the tools.
 
 - 3 `NRIPS` NRIP Save: Require for both L0 and L1
@@ -78,8 +78,8 @@ leaf 8000000A:edx
   The main putative use for this would be trying to maintain an
   invariant TSC across cores with different clock speeds, or after a
   migrate.  Unlike others, this doesn't have an error path to worry
-  about compatibility-wise; and according to tests done when nestedSVM
-  was first implemented, it's actually faster to emliate TscRateMSR in
+  about compatibility-wise; and according to tests done when nested SVM
+  was first implemented, it's actually faster to emulate TscRateMSR in
   the L0 hypervisor than for L1 to attempt to emulate it itself.
 
   However, using this properly in L0 will take some implementation
@@ -89,7 +89,7 @@ leaf 8000000A:edx
  - 5 `VmcbClean`: VMCB Clean Bits: Not required by L0, provide to L1
 
   This is a pure optimization, both on the side of the L0 and L1.  The
-  implementaiton for L1 is entirely Xen-side, so can be provided even
+  implementation for L1 is entirely Xen-side, so can be provided even
   on hardware that doesn't provide it.  And it's purely an
   optimization, so could be "implemented" by ignoring the bits
   entirely.
@@ -102,7 +102,7 @@ leaf 8000000A:edx
 - 6 `FlushByAsid`: Require for L0, provide to L1
 
   This is cheap and easy to use for L0 and to provide to the L1;
-  there's no reson not to just pass it through.
+  there's no reason not to just pass it through.
 
 - 7 `DecodeAssists`: Require for L0, provide to L1
 
diff --git a/docs/designs/qemu-deprivilege.md b/docs/designs/qemu-deprivilege.md
index f12b1a3ae3..d593fe8e37 100644
--- a/docs/designs/qemu-deprivilege.md
+++ b/docs/designs/qemu-deprivilege.md
@@ -22,7 +22,7 @@ The following restrictions are currently implemented.
 '''Description''': As mentioned above, having QEMU switch to a
 non-root user, one per domain id.  Not being the root user limits what
 a compromised QEMU process can do to the system, and having one user
-per domain id limits what a comprimised QEMU process can do to the
+per domain id limits what a compromised QEMU process can do to the
 QEMU processes of other VMs.
 
 '''Implementation''': The toolstack adds the following to the qemu command-line:
@@ -79,8 +79,8 @@ Then adds the following to the qemu command-line:
 ## Namespaces for unused functionality (Linux only)
 
 '''Description''': QEMU doesn't use the functionality associated with
-mount and IPC namespaces. (IPC namespaces contol non-file-based IPC
-mechanisms within the kernel; unix and network sockets are not
+mount and IPC namespaces. (IPC namespaces control non-file-based IPC
+mechanisms within the kernel; Unix and network sockets are not
 affected by this.)  Making separate namespaces for these for QEMU
 won't affect normal operation, but it does mean that even if other
 restrictions fail, the process won't be able to even name system mount
@@ -179,7 +179,7 @@ being killed by the target process:
             kill(-1, 9);
     }
 
-Fortunately there is an assymetry we can take advantage of.  From the
+Fortunately there is an asymmetry we can take advantage of.  From the
 POSIX spec:
 
 > For a process to have permission to send a signal to a process
@@ -220,7 +220,7 @@ RLIMIT_NPROC limits total number of processes or threads.  QEMU uses
 threads for some devices, so this would require some thought.
 
 Other things that would take some cleverness / changes to QEMU to
-utilize due to ordering constrants:
+utilize due to ordering constraints:
  - RLIMIT_NOFILES (after all necessary files are opened)
 
 ## libxl: Treat QMP connection as untrusted
@@ -251,7 +251,7 @@ executing QEMU.  (But this would then require other changes to create
 the QMP socket, VNC socket, and so on).
 
 It should be noted that `-sandbox` is implemented as a blacklist, not
-a whitelist; that is, it disables known-unsed functionality which may
+a whitelist; that is, it disables known-unused functionality which may
 be harmful, rather than disabling all functionality except that known
 to be safe and needed.  This is unfortunately necessary since qemu
 doesn't know what system calls libraries might end up making.  (See
diff --git a/docs/designs/xenstore-migration.md b/docs/designs/xenstore-migration.md
index 5022268386..082314bf72 100644
--- a/docs/designs/xenstore-migration.md
+++ b/docs/designs/xenstore-migration.md
@@ -372,7 +372,7 @@ or modified by a transaction for which there is also a `TRANSACTION_DATA`
 record previously present).
 
 Each _committed_ node in the stream is required to have an already known parent
-node. A parent node is known if it was either in the node data base before the
+node. A parent node is known if it was either in the node database before the
 stream was started to be processed, or if a `NODE_DATA` record for that parent
 node has already been processed in the stream.
 
diff --git a/docs/features/qemu-deprivilege.pandoc b/docs/features/qemu-deprivilege.pandoc
index 4ef119c821..915e38d8c9 100644
--- a/docs/features/qemu-deprivilege.pandoc
+++ b/docs/features/qemu-deprivilege.pandoc
@@ -25,7 +25,7 @@ dm_restrict is a set of operations to restrict QEMU running in domain
 
  1. Mechanisms to restrict QEMU to only being able to affect its own
 domain
- 2. Mechanisms to restruct QEMU's ability to interact with domain 0.
+ 2. Mechanisms to restrict QEMU's ability to interact with domain 0.
 
 # User details
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs/misc: Fix a few typos
Message-Id: <E1tYOj2-008eYh-1z@xenbits.xenproject.org>
Date: Thu, 16 Jan 2025 12:11:52 +0000

commit a29a1fb5a5b213ce972c925c84c52bebad4d34b7
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Wed Jan 15 16:09:04 2025 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Thu Jan 16 11:22:11 2025 +0000

    docs/misc: Fix a few typos
    
    While skimming through the misc docs, I spotted a few typos.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/misc/livepatch.pandoc            | 44 +++++++++++++++++------------------
 docs/misc/netif-staging-grants.pandoc | 20 ++++++++--------
 docs/misc/printk-formats.txt          |  2 +-
 3 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/docs/misc/livepatch.pandoc b/docs/misc/livepatch.pandoc
index 4a0b4fd6d8..04dd5ed7b2 100644
--- a/docs/misc/livepatch.pandoc
+++ b/docs/misc/livepatch.pandoc
@@ -25,7 +25,7 @@ The document is split in four sections:
  * reloc - telemetries contained in the payload to construct proper trampoline.
  * hook - an auxiliary function being called before, during or after payload
           application or revert.
- * quiescing zone - period when all CPUs are lock-step with each other.
+ * quiescent zone - period when all CPUs are lock-step with each other.
 
 ## History
 
@@ -267,7 +267,7 @@ It may also have some architecture-specific sections. For example:
  * Relocations for each of these sections.
 
 The Xen Live Patch core code loads the payload as a standard ELF binary, relocates it
-and handles the architecture-specifc sections as needed. This process is much
+and handles the architecture-specific sections as needed. This process is much
 like what the Linux kernel module loader does.
 
 The payload contains at least three sections:
@@ -372,7 +372,7 @@ and the core code copies the data from the undo buffer (private internal copy)
 to `old_addr`.
 
 It optionally may contain the address of hooks to be called right before
-being applied and after being reverted (while all CPUs are still in quiescing
+being applied and after being reverted (while all CPUs are still in quiescent
 zone). These hooks do not have access to payload structure.
 
  * `.livepatch.hooks.load` - an array of function pointers.
@@ -380,7 +380,7 @@ zone). These hooks do not have access to payload structure.
 
 It optionally may also contain the address of pre- and post- vetoing hooks to
 be called before (pre) or after (post) apply and revert payload actions (while
-all CPUs are already released from quiescing zone). These hooks do have
+all CPUs are already released from quiescent zone). These hooks do have
 access to payload structure. The pre-apply hook can prevent from loading the
 payload if encoded in it condition is not met. Accordingly, the pre-revert
 hook can prevent from unloading the livepatch if encoded in it condition is not
@@ -392,7 +392,7 @@ met.
 
 Finally, it optionally may also contain the address of apply or revert action
 hooks to be called instead of the default apply and revert payload actions
-(while all CPUs are kept in quiescing zone). These hooks do have access to
+(while all CPUs are kept in quiescent zone). These hooks do have access to
 payload structure.
 
  * `.livepatch.hooks.{apply,revert}`
@@ -463,7 +463,7 @@ The type definition of the function are as follow:
 
 This section contains a pointer to a single function pointer to be executed
 before apply action is scheduled (and thereby before CPUs are put into
-quiescing zone). This is useful to prevent from applying a payload when
+quiescent zone). This is useful to prevent from applying a payload when
 certain expected conditions aren't met or when mutating actions implemented
 in the hook fail or cannot be executed.
 This type of hooks do have access to payload structure.
@@ -477,7 +477,7 @@ The type definition of the function are as follow:
 #### .livepatch.hooks.postapply
 
 This section contains a pointer to a single function pointer to be executed
-after apply action has finished and after all CPUs left the quiescing zone.
+after apply action has finished and after all CPUs left the quiescent zone.
 This is useful to provide an ability to follow up on actions performed by
 the preapply hook. Especially, when module application was successful or to
 be able to undo certain preparation steps of the preapply hook in case of a
@@ -495,7 +495,7 @@ The type definition of the function are as follow:
 
 This section contains a pointer to a single function pointer to be executed
 before revert action is scheduled (and thereby before CPUs are put into
-quiescing zone). This is useful to prevent from reverting a payload when
+quiescent zone). This is useful to prevent from reverting a payload when
 certain expected conditions aren't met or when mutating actions implemented
 in the hook fail or cannot be executed.
 This type of hooks do have access to payload structure.
@@ -509,7 +509,7 @@ The type definition of the function are as follow:
 #### .livepatch.hooks.postrevert
 
 This section contains a pointer to a single function pointer to be executed
-after revert action has finished and after all CPUs left the quiescing zone.
+after revert action has finished and after all CPUs left the quiescent zone.
 This is useful to provide an ability to perform cleanup of all previously
 executed mutating actions in order to restore the original system state from
 before the current payload application. The success/failure error code is
@@ -527,7 +527,7 @@ The type definition of the function are as follow:
 This section contains a pointer to a single function pointer to be executed
 instead of a default apply (or revert) action function. This is useful to
 replace or augment default behavior of the apply (or revert) action that
-requires all CPUs to be in the quiescing zone.
+requires all CPUs to be in the quiescent zone.
 This type of hooks do have access to payload structure.
 
 Each entry in this array is eight bytes.
@@ -539,13 +539,13 @@ The type definition of the function are as follow:
 ### .livepatch.xen_depends, .livepatch.depends and .note.gnu.build-id
 
 To support dependencies checking and safe loading (to load the
-appropiate payload against the right hypervisor) there is a need
-to embbed an build-id dependency.
+appropriate payload against the right hypervisor) there is a need
+to embed a build-id dependency.
 
 This is done by the payload containing sections `.livepatch.xen_depends`
 and `.livepatch.depends` which follow the format of an ELF Note.
 The contents of these (name, and description) are specific to the linker
-utilized to build the hypevisor and payload.
+utilized to build the hypervisor and payload.
 
 If GNU linker is used then the name is `GNU` and the description
 is a NT_GNU_BUILD_ID type ID. The description can be an SHA1
@@ -639,7 +639,7 @@ The `name` could be an UUID that stays fixed forever for a given
 payload. It can be embedded into the ELF payload at creation time
 and extracted by tools.
 
-The return value is zero if the payload was succesfully uploaded.
+The return value is zero if the payload was successfully uploaded.
 Otherwise an -XEN_EXX return value is provided. Duplicate `name` are not supported.
 
 The `payload` is the ELF payload as mentioned in the `Payload format` section.
@@ -819,7 +819,7 @@ The caller provides:
  * `cmd` The command requested:
   * *LIVEPATCH_ACTION_UNLOAD* (1) Unload the payload.
    Any further hypercalls against the `name` will result in failure unless
-   **XEN_SYSCTL_LIVEPATCH_UPLOAD** hypercall is perfomed with same `name`.
+   **XEN_SYSCTL_LIVEPATCH_UPLOAD** hypercall is performed with same `name`.
   * *LIVEPATCH_ACTION_REVERT* (2) Revert the payload. If the operation takes
   more time than the upper bound of time the `rc` in `xen_livepatch_status`
   retrieved via **XEN_SYSCTL_LIVEPATCH_GET** will be -XEN_EBUSY.
@@ -969,7 +969,7 @@ Before we call VMXResume we check whether any soft IRQs need to be executed.
 This is a good spot because all Xen stacks are effectively empty at
 that point.
 
-To randezvous all the CPUs an barrier with an maximum timeout (which
+To rendezvous all the CPUs an barrier with an maximum timeout (which
 could be adjusted), combined with forcing all other CPUs through the
 hypervisor with IPIs, can be utilized to execute lockstep instructions
 on all CPUs.
@@ -990,7 +990,7 @@ be done to the linker scripts to support this.
 
 The design of that is not discussed in this design.
 
-This is implemented in a seperate tool which lives in a seperate
+This is implemented in a separate tool which lives in a separate
 GIT repo.
 
 Currently it resides at https://xenbits.xen.org/git-http/livepatch-build-tools.git
@@ -1066,17 +1066,17 @@ There are the ways this can be addressed:
    grows to accumulate all the code changes.
  * Hotpatch stack - where an mechanism exists that loads the hotpatches
    in the same order they were built in. We would need an build-id
-   of the hypevisor to make sure the hot-patches are build against the
+   of the hypervisor to make sure the hot-patches are build against the
    correct build.
  * Payload containing the old code to check against that. That allows
-   the hotpatches to be loaded indepedently (if they don't overlap) - or
-   if the old code also containst previously patched code - even if they
+   the hotpatches to be loaded independently (if they don't overlap) - or
+   if the old code also contains previously patched code - even if they
    overlap.
 
 The disadvantage of the first large patch is that it can grow over
 time and not provide an bisection mechanism to identify faulty patches.
 
-The hot-patch stack puts stricts requirements on the order of the patches
+The hot-patch stack puts strict requirements on the order of the patches
 being loaded and requires an hypervisor build-id to match against.
 
 The old code allows much more flexibility and an additional guard,
@@ -1263,7 +1263,7 @@ limit that calls the next trampoline.
 
 Please note there is a small limitation for trampolines in
 function entries: The target function (+ trailing padding) must be able
-to accomodate the trampoline. On x86 with +-2 GB relative jumps,
+to accommodate the trampoline. On x86 with +-2 GB relative jumps,
 this means 5 bytes are required which means that `old_size` **MUST** be
 at least five bytes if patching in trampoline.
 
diff --git a/docs/misc/netif-staging-grants.pandoc b/docs/misc/netif-staging-grants.pandoc
index cb33028adc..838b115840 100644
--- a/docs/misc/netif-staging-grants.pandoc
+++ b/docs/misc/netif-staging-grants.pandoc
@@ -9,7 +9,7 @@ Architecture(s): Any
 
 # Background and Motivation
 
-At the Xen hackaton '16 networking session, we spoke about having a permanently
+At the Xen hackathon '16 networking session, we spoke about having a permanently
 mapped region to describe header/linear region of packet buffers. This document
 outlines the proposal covering motivation of this and applicability for other
 use-cases alongside the necessary changes.
@@ -174,8 +174,8 @@ boundary
 
 17) Allocate packet metadata
 
-[ *Linux specific*: This structure emcompasses a linear data region which
-generally accomodates the protocol header and such. Netback allocates up to 128
+[ *Linux specific*: This structure encompasses a linear data region which
+generally accommodates the protocol header and such. Netback allocates up to 128
 bytes for that. ]
 
 18) *Linux specific*: Setup up a `GNTTABOP_copy` to copy up to 128 bytes to this small
@@ -317,7 +317,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
  process the actual like the steps below. This thread has the purpose of
  aggregating as much copies as possible.]
 
-2) Checks if there are enough rx ring slots that can accomodate the packet.
+2) Checks if there are enough rx ring slots that can accommodate the packet.
 
 3) Gets a request from the ring for the first data slot and fetches the `gref`
    from it.
@@ -375,7 +375,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
 
 24) Call packet into the network stack.
 
-25) Allocate new pages and any necessary packet metadata strutures to new
+25) Allocate new pages and any necessary packet metadata structures to new
     requests. These requests will then be used in step 1) and so forth.
 
 26) Update the request producer index (`req_prod`)
@@ -391,7 +391,7 @@ In essence the steps for receiving of a packet in a Linux frontend is as
 
 This proposal aims at replacing step 4), 12) and  22) with memcpy if the
 grefs on the Rx ring were requested to be mapped by the guest. Frontend may use
-strategies to allow fast recycling of grants for replinishing the ring,
+strategies to allow fast recycling of grants for replenishing the ring,
 hence letting Domain-0 replace the grant copies with  memcpy instead, which is
 faster.
 
@@ -400,8 +400,8 @@ would need to aggregate as much as grant ops as possible (step 1) and could
 transmit the packet on the transmit function (e.g. Linux ```ndo_start_xmit```)
 as previously proposed
 here\[[0](http://lists.xenproject.org/archives/html/xen-devel/2015-05/msg01504.html)\].
-This would heavily improve efficiency specifially for smaller packets. Which in
-return would decrease RTT, having data being acknoledged much quicker.
+This would heavily improve efficiency specifically for smaller packets. Which in
+return would decrease RTT, having data being acknowledged much quicker.
 
 \clearpage
 
@@ -467,13 +467,13 @@ The entry 'status' field determines if the entry was successfully removed.
 Control ring is only available after backend state is `XenbusConnected`
 therefore only on this state change can the frontend query the total amount of
 maps it can keep. It then grants N entries per queue on both TX and RX ring
-which will create the underying backend gref -> page association (e.g.  stored
+which will create the underlying backend gref -> page association (e.g.  stored
 in hash table). Frontend may wish to recycle these pregranted buffers or choose
 a copy approach to replace granting.
 
 On steps 19) of Guest Transmit and 3) of Guest Receive, data gref is first
 looked up in this table and uses the underlying page if it already exists a
-mapping. On the successfull cases, steps 20) 21) and 27) of Guest Transmit are
+mapping. On the successful cases, steps 20) 21) and 27) of Guest Transmit are
 skipped, with 19) being replaced with a memcpy of up to 128 bytes. On Guest
 Receive, 4) 12) and 22) are replaced with memcpy instead of a grant copy.
 
diff --git a/docs/misc/printk-formats.txt b/docs/misc/printk-formats.txt
index 8f666f696a..ce32829dae 100644
--- a/docs/misc/printk-formats.txt
+++ b/docs/misc/printk-formats.txt
@@ -11,7 +11,7 @@ Raw buffer as hex string:
        %*phN   000102 ... 3f
 
        Up to 64 characters.  Buffer length expected via the field_width
-       paramter. i.e. printk("%*ph", 8, buffer);
+       parameter. i.e. printk("%*ph", 8, buffer);
 
 Bitmaps (e.g. cpumask/nodemask):
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xentrace: free CPU mask string before overwriting pointer
Message-Id: <E1tYhGv-00Axyw-1K@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:00:05 +0000

commit c33e14abb1aea6769146346f6737288be838f906
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:53:27 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:53:27 2025 +0100

    xentrace: free CPU mask string before overwriting pointer
    
    While multiple -c options may be unexpected, we'd still better deal with
    them properly.
    
    Also restore the blank line that was bogusly zapped by the same commit.
    
    Coverity-ID: 1638723
    Fixes: e4ad2836842a ("xentrace: Implement cpu mask range parsing of human values (-c)")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 tools/xentrace/xentrace.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/xentrace/xentrace.c b/tools/xentrace/xentrace.c
index 63b29f8442..a5aa3c1903 100644
--- a/tools/xentrace/xentrace.c
+++ b/tools/xentrace/xentrace.c
@@ -1105,8 +1105,10 @@ static void parse_args(int argc, char **argv)
             break;
 
         case 'c': /* set new cpu mask for filtering (when xch is set). */
+            free(opts.cpu_mask_str);
             opts.cpu_mask_str = strdup(optarg);
             break;
+
         case 'e': /* set new event mask for filtering*/
             parse_evtmask(optarg);
             break;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xl: properly dispose of vTPM struct instance
Message-Id: <E1tYhH5-00Ay0Z-21@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:00:15 +0000

commit 737e8cc91ba231c64a32520d6330129857aa5780
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:53:50 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:53:50 2025 +0100

    xl: properly dispose of vTPM struct instance
    
    The backend_domname field requires separate freeing; make sure to call
    libxl_device_vtpm_dispose() also on respective error paths.
    
    Coverity-ID: 1638719
    Fixes: dde22055ac3a ("libxl: add vtpm support")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 tools/xl/xl_vtpm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/xl/xl_vtpm.c b/tools/xl/xl_vtpm.c
index 0ba5041609..ef3e11f1ac 100644
--- a/tools/xl/xl_vtpm.c
+++ b/tools/xl/xl_vtpm.c
@@ -44,12 +44,14 @@ int main_vtpmattach(int argc, char **argv)
         if (MATCH_OPTION("uuid", *argv, oparg)) {
             if(libxl_uuid_from_string(&(vtpm.uuid), oparg)) {
                 fprintf(stderr, "Invalid uuid specified (%s)\n", oparg);
+                libxl_device_vtpm_dispose(&vtpm);
                 return 1;
             }
         } else if (MATCH_OPTION("backend", *argv, oparg)) {
             replace_string(&vtpm.backend_domname, oparg);
         } else {
             fprintf(stderr, "unrecognized argument `%s'\n", *argv);
+            libxl_device_vtpm_dispose(&vtpm);
             return 1;
         }
     }
@@ -65,6 +67,7 @@ int main_vtpmattach(int argc, char **argv)
 
     if (libxl_device_vtpm_add(ctx, domid, &vtpm, 0)) {
         fprintf(stderr, "libxl_device_vtpm_add failed.\n");
+        libxl_device_vtpm_dispose(&vtpm);
         return 1;
     }
     libxl_device_vtpm_dispose(&vtpm);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xl: properly dispose of libxl_dominfo struct instances
Message-Id: <E1tYhHF-00Ay1N-2N@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:00:25 +0000

commit 274c509162fe91ec97428e19be58b950af919184
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:54:03 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:03 2025 +0100

    xl: properly dispose of libxl_dominfo struct instances
    
    The ssid_label field requires separate freeing; make sure to call
    libxl_dominfo_dispose() as well as libxl_dominfo_init(). Since vcpuset()
    calls only the former, add a call to the latter there at the same time.
    
    Coverity-ID: 1638727
    Coverity-ID: 1638728
    Fixes: c458c404da16 ("xl: use libxl_domain_info to get the uuid in printf_info")
    Fixes: 48dab9767d2e ("tools/xl: use libxl_domain_info to get domain type for vcpu-pin")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 tools/xl/xl_sxp.c  | 2 ++
 tools/xl/xl_vcpu.c | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/tools/xl/xl_sxp.c b/tools/xl/xl_sxp.c
index 359a001570..4383ad177a 100644
--- a/tools/xl/xl_sxp.c
+++ b/tools/xl/xl_sxp.c
@@ -45,8 +45,10 @@ void printf_info_sexp(int domid, libxl_domain_config *d_config, FILE *fh)
     /* retrieve the UUID from dominfo, since it is probably generated
      * during parsing and thus does not match the real one
      */
+    libxl_dominfo_init(&info);
     if (libxl_domain_info(ctx, &info, domid) == 0) {
         fprintf(fh, "\t(uuid " LIBXL_UUID_FMT ")\n", LIBXL_UUID_BYTES(info.uuid));
+        libxl_dominfo_dispose(&info);
     } else {
         fprintf(fh, "\t(uuid <unknown>)\n");
     }
diff --git a/tools/xl/xl_vcpu.c b/tools/xl/xl_vcpu.c
index 66877a57de..b7dbc3e842 100644
--- a/tools/xl/xl_vcpu.c
+++ b/tools/xl/xl_vcpu.c
@@ -286,6 +286,8 @@ int main_vcpupin(int argc, char **argv)
     if (!ignore_masks && hard) {
         libxl_dominfo dominfo;
 
+        libxl_dominfo_init(&dominfo);
+
         if (libxl_domain_info(ctx, &dominfo, domid)) {
             fprintf(stderr, "Could not get domain info\n");
             goto out;
@@ -293,6 +295,8 @@ int main_vcpupin(int argc, char **argv)
 
         /* HVM and PVH domains use the same global affinity mask */
         apply_global_affinity_masks(dominfo.domain_type, hard, 1);
+
+        libxl_dominfo_dispose(&dominfo);
     }
 
     if (force) {
@@ -348,6 +352,7 @@ static int vcpuset(uint32_t domid, const char* nr_vcpus, int check_host)
         unsigned int online_vcpus, host_cpu = libxl_get_max_cpus(ctx);
         libxl_dominfo dominfo;
 
+        libxl_dominfo_init(&dominfo);
         if (libxl_domain_info(ctx, &dominfo, domid))
             return 1;
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] Manual pages: Fix a few typos
Message-Id: <E1tYhHP-00Ay2g-2u@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:00:35 +0000

commit 24c685286defd05639844656673b90d8fa97d4f0
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Fri Jan 17 08:54:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:25 2025 +0100

    Manual pages: Fix a few typos
    
    While skimming through the manual pages, I spotted a few typos.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/man/xen-vtpmmgr.7.pod       | 2 +-
 docs/man/xl-numa-placement.7.pod | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/man/xen-vtpmmgr.7.pod b/docs/man/xen-vtpmmgr.7.pod
index 3286954568..95854adb08 100644
--- a/docs/man/xen-vtpmmgr.7.pod
+++ b/docs/man/xen-vtpmmgr.7.pod
@@ -297,7 +297,7 @@ extra option to launch vtpmmgr-stubdom domain on TPM 2.0, and ignore it on TPM
     |   Primary Seed   |
     +------------------+
 
-Now the secrets for the vTPMs are only being bound to the presence of thephysical
+Now the secrets for the vTPMs are only being bound to the presence of the physical
 TPM 2.0. Since using PCRs to seal the data can be an important security feature
 that users of the vtpmmgr rely on. I will replace TPM2_Bind/TPM2_Unbind with
 TPM2_Seal/TPM2_Unseal to provide as much security as it did for TPM 1.2 in later
diff --git a/docs/man/xl-numa-placement.7.pod b/docs/man/xl-numa-placement.7.pod
index 802f33060b..4d83f26d41 100644
--- a/docs/man/xl-numa-placement.7.pod
+++ b/docs/man/xl-numa-placement.7.pod
@@ -45,7 +45,7 @@ user, via the proper libxl calls or xl config item, it will be computed
 basing on the vCPUs' scheduling affinity.
 
 Notice that, even if the node affinity of a domain may change on-line,
-it is very important to "place" the domain correctly when it is fist
+it is very important to "place" the domain correctly when it is first
 created, as the most of its memory is allocated at that time and can
 not (for now) be moved easily.
 
@@ -94,7 +94,7 @@ this reason, NUMA aware scheduling has the potential of bringing
 substantial performances benefits, although this will depend on the
 workload.
 
-Notice that, for each vCPU, the following three scenarios are possbile:
+Notice that, for each vCPU, the following three scenarios are possible:
 
 =over
 
@@ -102,7 +102,7 @@ Notice that, for each vCPU, the following three scenarios are possbile:
 
 a vCPU I<is pinned> to some pCPUs and I<does not have> any soft affinity
 In this case, the vCPU is always scheduled on one of the pCPUs to which
-it is pinned, without any specific peference among them.
+it is pinned, without any specific preference among them.
 
 
 =item *
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs/misra: Document ECLAIR extension to Rule 20.7
Message-Id: <E1tYhHa-00Ay4R-01@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:00:46 +0000

commit 75d88297f50531bdad83a513b47e6ffad34499ec
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Fri Jan 17 08:54:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:39 2025 +0100

    docs/misra: Document ECLAIR extension to Rule 20.7
    
    MISRA C Rule 20.7 states:
    "Expressions resulting from the expansion of macro parameters shall
    be enclosed in parentheses".
    
    Document the behaviour of ECLAIR with respect to the CPP extension
    that allows variable macro arguments to be named.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/misra/rules.rst | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index e7763795b8..e1c26030e8 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -671,7 +671,14 @@ maintainers if you want to suggest a change.
        shall be enclosed in parentheses
      - Extra parentheses are not required when macro parameters are used
        as function arguments, as macro arguments, array indices, lhs in
-       assignments or as initializers in initalizer lists.
+       assignments or as initializers in initalizer lists. In addition,
+       the use of a named variable argument in a macro that would constitute
+       a violation of the rule is allowed by ECLAIR as an extension of the
+       MISRA guideline, since it may not always be possible to parenthesize
+       such argument and the feature is non-standard::
+
+         #define M(args...) args
+         #if M(1) + 0 
 
    * - `Rule 20.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_09.c>`_
      - Required
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xentrace: free CPU mask string before overwriting pointer
Message-Id: <E1tYi86-00B360-05@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:55:02 +0000

commit c33e14abb1aea6769146346f6737288be838f906
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:53:27 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:53:27 2025 +0100

    xentrace: free CPU mask string before overwriting pointer
    
    While multiple -c options may be unexpected, we'd still better deal with
    them properly.
    
    Also restore the blank line that was bogusly zapped by the same commit.
    
    Coverity-ID: 1638723
    Fixes: e4ad2836842a ("xentrace: Implement cpu mask range parsing of human values (-c)")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 tools/xentrace/xentrace.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/xentrace/xentrace.c b/tools/xentrace/xentrace.c
index 63b29f8442..a5aa3c1903 100644
--- a/tools/xentrace/xentrace.c
+++ b/tools/xentrace/xentrace.c
@@ -1105,8 +1105,10 @@ static void parse_args(int argc, char **argv)
             break;
 
         case 'c': /* set new cpu mask for filtering (when xch is set). */
+            free(opts.cpu_mask_str);
             opts.cpu_mask_str = strdup(optarg);
             break;
+
         case 'e': /* set new event mask for filtering*/
             parse_evtmask(optarg);
             break;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xl: properly dispose of vTPM struct instance
Message-Id: <E1tYi8G-00B36Y-0Z@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:55:12 +0000

commit 737e8cc91ba231c64a32520d6330129857aa5780
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:53:50 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:53:50 2025 +0100

    xl: properly dispose of vTPM struct instance
    
    The backend_domname field requires separate freeing; make sure to call
    libxl_device_vtpm_dispose() also on respective error paths.
    
    Coverity-ID: 1638719
    Fixes: dde22055ac3a ("libxl: add vtpm support")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 tools/xl/xl_vtpm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/xl/xl_vtpm.c b/tools/xl/xl_vtpm.c
index 0ba5041609..ef3e11f1ac 100644
--- a/tools/xl/xl_vtpm.c
+++ b/tools/xl/xl_vtpm.c
@@ -44,12 +44,14 @@ int main_vtpmattach(int argc, char **argv)
         if (MATCH_OPTION("uuid", *argv, oparg)) {
             if(libxl_uuid_from_string(&(vtpm.uuid), oparg)) {
                 fprintf(stderr, "Invalid uuid specified (%s)\n", oparg);
+                libxl_device_vtpm_dispose(&vtpm);
                 return 1;
             }
         } else if (MATCH_OPTION("backend", *argv, oparg)) {
             replace_string(&vtpm.backend_domname, oparg);
         } else {
             fprintf(stderr, "unrecognized argument `%s'\n", *argv);
+            libxl_device_vtpm_dispose(&vtpm);
             return 1;
         }
     }
@@ -65,6 +67,7 @@ int main_vtpmattach(int argc, char **argv)
 
     if (libxl_device_vtpm_add(ctx, domid, &vtpm, 0)) {
         fprintf(stderr, "libxl_device_vtpm_add failed.\n");
+        libxl_device_vtpm_dispose(&vtpm);
         return 1;
     }
     libxl_device_vtpm_dispose(&vtpm);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xl: properly dispose of libxl_dominfo struct instances
Message-Id: <E1tYi8Q-00B37L-0u@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:55:22 +0000

commit 274c509162fe91ec97428e19be58b950af919184
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 17 08:54:03 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:03 2025 +0100

    xl: properly dispose of libxl_dominfo struct instances
    
    The ssid_label field requires separate freeing; make sure to call
    libxl_dominfo_dispose() as well as libxl_dominfo_init(). Since vcpuset()
    calls only the former, add a call to the latter there at the same time.
    
    Coverity-ID: 1638727
    Coverity-ID: 1638728
    Fixes: c458c404da16 ("xl: use libxl_domain_info to get the uuid in printf_info")
    Fixes: 48dab9767d2e ("tools/xl: use libxl_domain_info to get domain type for vcpu-pin")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 tools/xl/xl_sxp.c  | 2 ++
 tools/xl/xl_vcpu.c | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/tools/xl/xl_sxp.c b/tools/xl/xl_sxp.c
index 359a001570..4383ad177a 100644
--- a/tools/xl/xl_sxp.c
+++ b/tools/xl/xl_sxp.c
@@ -45,8 +45,10 @@ void printf_info_sexp(int domid, libxl_domain_config *d_config, FILE *fh)
     /* retrieve the UUID from dominfo, since it is probably generated
      * during parsing and thus does not match the real one
      */
+    libxl_dominfo_init(&info);
     if (libxl_domain_info(ctx, &info, domid) == 0) {
         fprintf(fh, "\t(uuid " LIBXL_UUID_FMT ")\n", LIBXL_UUID_BYTES(info.uuid));
+        libxl_dominfo_dispose(&info);
     } else {
         fprintf(fh, "\t(uuid <unknown>)\n");
     }
diff --git a/tools/xl/xl_vcpu.c b/tools/xl/xl_vcpu.c
index 66877a57de..b7dbc3e842 100644
--- a/tools/xl/xl_vcpu.c
+++ b/tools/xl/xl_vcpu.c
@@ -286,6 +286,8 @@ int main_vcpupin(int argc, char **argv)
     if (!ignore_masks && hard) {
         libxl_dominfo dominfo;
 
+        libxl_dominfo_init(&dominfo);
+
         if (libxl_domain_info(ctx, &dominfo, domid)) {
             fprintf(stderr, "Could not get domain info\n");
             goto out;
@@ -293,6 +295,8 @@ int main_vcpupin(int argc, char **argv)
 
         /* HVM and PVH domains use the same global affinity mask */
         apply_global_affinity_masks(dominfo.domain_type, hard, 1);
+
+        libxl_dominfo_dispose(&dominfo);
     }
 
     if (force) {
@@ -348,6 +352,7 @@ static int vcpuset(uint32_t domid, const char* nr_vcpus, int check_host)
         unsigned int online_vcpus, host_cpu = libxl_get_max_cpus(ctx);
         libxl_dominfo dominfo;
 
+        libxl_dominfo_init(&dominfo);
         if (libxl_domain_info(ctx, &dominfo, domid))
             return 1;
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] Manual pages: Fix a few typos
Message-Id: <E1tYi8a-00B38Q-1F@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:55:32 +0000

commit 24c685286defd05639844656673b90d8fa97d4f0
Author:     Bernhard Kaindl <bernhard.kaindl@cloud.com>
AuthorDate: Fri Jan 17 08:54:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:25 2025 +0100

    Manual pages: Fix a few typos
    
    While skimming through the manual pages, I spotted a few typos.
    
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@cloud.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 docs/man/xen-vtpmmgr.7.pod       | 2 +-
 docs/man/xl-numa-placement.7.pod | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/man/xen-vtpmmgr.7.pod b/docs/man/xen-vtpmmgr.7.pod
index 3286954568..95854adb08 100644
--- a/docs/man/xen-vtpmmgr.7.pod
+++ b/docs/man/xen-vtpmmgr.7.pod
@@ -297,7 +297,7 @@ extra option to launch vtpmmgr-stubdom domain on TPM 2.0, and ignore it on TPM
     |   Primary Seed   |
     +------------------+
 
-Now the secrets for the vTPMs are only being bound to the presence of thephysical
+Now the secrets for the vTPMs are only being bound to the presence of the physical
 TPM 2.0. Since using PCRs to seal the data can be an important security feature
 that users of the vtpmmgr rely on. I will replace TPM2_Bind/TPM2_Unbind with
 TPM2_Seal/TPM2_Unseal to provide as much security as it did for TPM 1.2 in later
diff --git a/docs/man/xl-numa-placement.7.pod b/docs/man/xl-numa-placement.7.pod
index 802f33060b..4d83f26d41 100644
--- a/docs/man/xl-numa-placement.7.pod
+++ b/docs/man/xl-numa-placement.7.pod
@@ -45,7 +45,7 @@ user, via the proper libxl calls or xl config item, it will be computed
 basing on the vCPUs' scheduling affinity.
 
 Notice that, even if the node affinity of a domain may change on-line,
-it is very important to "place" the domain correctly when it is fist
+it is very important to "place" the domain correctly when it is first
 created, as the most of its memory is allocated at that time and can
 not (for now) be moved easily.
 
@@ -94,7 +94,7 @@ this reason, NUMA aware scheduling has the potential of bringing
 substantial performances benefits, although this will depend on the
 workload.
 
-Notice that, for each vCPU, the following three scenarios are possbile:
+Notice that, for each vCPU, the following three scenarios are possible:
 
 =over
 
@@ -102,7 +102,7 @@ Notice that, for each vCPU, the following three scenarios are possbile:
 
 a vCPU I<is pinned> to some pCPUs and I<does not have> any soft affinity
 In this case, the vCPU is always scheduled on one of the pCPUs to which
-it is pinned, without any specific peference among them.
+it is pinned, without any specific preference among them.
 
 
 =item *
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs/misra: Document ECLAIR extension to Rule 20.7
Message-Id: <E1tYi8k-00B39G-1Z@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 08:55:42 +0000

commit 75d88297f50531bdad83a513b47e6ffad34499ec
Author:     Nicola Vetrini <nicola.vetrini@bugseng.com>
AuthorDate: Fri Jan 17 08:54:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 17 08:54:39 2025 +0100

    docs/misra: Document ECLAIR extension to Rule 20.7
    
    MISRA C Rule 20.7 states:
    "Expressions resulting from the expansion of macro parameters shall
    be enclosed in parentheses".
    
    Document the behaviour of ECLAIR with respect to the CPP extension
    that allows variable macro arguments to be named.
    
    Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/misra/rules.rst | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index e7763795b8..e1c26030e8 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -671,7 +671,14 @@ maintainers if you want to suggest a change.
        shall be enclosed in parentheses
      - Extra parentheses are not required when macro parameters are used
        as function arguments, as macro arguments, array indices, lhs in
-       assignments or as initializers in initalizer lists.
+       assignments or as initializers in initalizer lists. In addition,
+       the use of a named variable argument in a macro that would constitute
+       a violation of the rule is allowed by ECLAIR as an extension of the
+       MISRA guideline, since it may not always be possible to parenthesize
+       such argument and the feature is non-standard::
+
+         #define M(args...) args
+         #if M(1) + 0 
 
    * - `Rule 20.9 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_20_09.c>`_
      - Required
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] automation/cirrus-ci: update FreeBSD to 13.4
Message-Id: <E1tYoAe-00Bnze-22@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 15:22:04 +0000

commit 850a263b7863ae9c22296a357a50573d5e6ae9d7
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Jan 16 09:07:31 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Fri Jan 17 16:00:14 2025 +0100

    automation/cirrus-ci: update FreeBSD to 13.4
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 .cirrus.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.cirrus.yml b/.cirrus.yml
index 4a120fad41..ee80152890 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -18,7 +18,7 @@ freebsd_template: &FREEBSD_TEMPLATE
 task:
   name: 'FreeBSD 13'
   freebsd_instance:
-    image_family: freebsd-13-3
+    image_family: freebsd-13-4
   << : *FREEBSD_TEMPLATE
 
 task:
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] automation/cirrus-ci: introduce FreeBSD randconfig builds
Message-Id: <E1tYoAo-00Bo06-2P@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 15:22:14 +0000

commit c3f5d1bb40b57d467cb4051eafa86f5933ec9003
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Jan 16 09:06:26 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Fri Jan 17 16:00:14 2025 +0100

    automation/cirrus-ci: introduce FreeBSD randconfig builds
    
    Add a new randconfig job for each FreeBSD version.  This requires some
    rework of the template so common parts can be shared between the full and
    the randconfig builds.  Such randconfig builds are relevant because FreeBSD
    is the only tested system that has a full non-GNU toolchain.
    
    While there replace the usage of the python311 package with python3, which is
    already using 3.11, and remove the install of the plain python package for full
    builds.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 .cirrus.yml | 67 ++++++++++++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 51 insertions(+), 16 deletions(-)

diff --git a/.cirrus.yml b/.cirrus.yml
index ee80152890..7216729b69 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -1,34 +1,69 @@
 # https://cirrus-ci.org/guide/tips-and-tricks/#sharing-configuration-between-tasks
-freebsd_template: &FREEBSD_TEMPLATE
+freebsd_13: &FREEBSD_13
+  freebsd_instance:
+    image_family: freebsd-13-4
+freebsd_14: &FREEBSD_14
+  freebsd_instance:
+    image_family: freebsd-14-2
+freebsd_15: &FREEBSD_15
+  freebsd_instance:
+    image_family: freebsd-15-0-snap
+
+freebsd_template: &FREEBSD_ENV
   environment:
     APPEND_LIB: /usr/local/lib
     APPEND_INCLUDES: /usr/local/include
 
+freebsd_full_build_template: &FREEBSD_FULL_BUILD_TEMPLATE
+  << : *FREEBSD_ENV
+
   install_script: pkg install -y seabios gmake ninja bash
-                                 pkgconf python bison perl5
+                                 pkgconf bison perl5
                                  yajl lzo2 pixman argp-standalone
-                                 libxml2 glib git python311
+                                 libxml2 glib git python3
 
   build_script:
     - cc --version
-    - export PYTHON=/usr/local/bin/python3.11
     - ./configure --with-system-seabios=/usr/local/share/seabios/bios.bin
     - gmake -j`sysctl -n hw.ncpu` clang=y
 
+freebsd_randconfig_template: &FREEBSD_RANDCONFIG_TEMPLATE
+  << : *FREEBSD_ENV
+
+  install_script: pkg install -y gmake python3 bison
+
+  build_script:
+    - cc --version
+    - gmake -j`sysctl -n hw.ncpu` -C xen clang=y \
+            KCONFIG_ALLCONFIG=tools/kconfig/allrandom.config randconfig
+    - gmake -j`sysctl -n hw.ncpu` build-xen clang=y
+
 task:
-  name: 'FreeBSD 13'
-  freebsd_instance:
-    image_family: freebsd-13-4
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 13: full build'
+  << : *FREEBSD_13
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
 
 task:
-  name: 'FreeBSD 14'
-  freebsd_instance:
-    image_family: freebsd-14-2
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 14: full build'
+  << : *FREEBSD_14
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
 
 task:
-  name: 'FreeBSD 15'
-  freebsd_instance:
-    image_family: freebsd-15-0-snap
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 15: full build'
+  << : *FREEBSD_15
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
+
+task:
+  name: 'FreeBSD 13: randconfig'
+  << : *FREEBSD_13
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
+
+task:
+  name: 'FreeBSD 14: randconfig'
+  << : *FREEBSD_14
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
+
+task:
+  name: 'FreeBSD 15: randconfig'
+  << : *FREEBSD_15
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] automation/cirrus-ci: update FreeBSD to 13.4
Message-Id: <E1tYpcb-00C2SU-1V@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 16:55:01 +0000

commit 850a263b7863ae9c22296a357a50573d5e6ae9d7
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Jan 16 09:07:31 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Fri Jan 17 16:00:14 2025 +0100

    automation/cirrus-ci: update FreeBSD to 13.4
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 .cirrus.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.cirrus.yml b/.cirrus.yml
index 4a120fad41..ee80152890 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -18,7 +18,7 @@ freebsd_template: &FREEBSD_TEMPLATE
 task:
   name: 'FreeBSD 13'
   freebsd_instance:
-    image_family: freebsd-13-3
+    image_family: freebsd-13-4
   << : *FREEBSD_TEMPLATE
 
 task:
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] automation/cirrus-ci: introduce FreeBSD randconfig builds
Message-Id: <E1tYpcl-00C2TL-23@xenbits.xenproject.org>
Date: Fri, 17 Jan 2025 16:55:11 +0000

commit c3f5d1bb40b57d467cb4051eafa86f5933ec9003
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Jan 16 09:06:26 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Fri Jan 17 16:00:14 2025 +0100

    automation/cirrus-ci: introduce FreeBSD randconfig builds
    
    Add a new randconfig job for each FreeBSD version.  This requires some
    rework of the template so common parts can be shared between the full and
    the randconfig builds.  Such randconfig builds are relevant because FreeBSD
    is the only tested system that has a full non-GNU toolchain.
    
    While there replace the usage of the python311 package with python3, which is
    already using 3.11, and remove the install of the plain python package for full
    builds.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
---
 .cirrus.yml | 67 ++++++++++++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 51 insertions(+), 16 deletions(-)

diff --git a/.cirrus.yml b/.cirrus.yml
index ee80152890..7216729b69 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -1,34 +1,69 @@
 # https://cirrus-ci.org/guide/tips-and-tricks/#sharing-configuration-between-tasks
-freebsd_template: &FREEBSD_TEMPLATE
+freebsd_13: &FREEBSD_13
+  freebsd_instance:
+    image_family: freebsd-13-4
+freebsd_14: &FREEBSD_14
+  freebsd_instance:
+    image_family: freebsd-14-2
+freebsd_15: &FREEBSD_15
+  freebsd_instance:
+    image_family: freebsd-15-0-snap
+
+freebsd_template: &FREEBSD_ENV
   environment:
     APPEND_LIB: /usr/local/lib
     APPEND_INCLUDES: /usr/local/include
 
+freebsd_full_build_template: &FREEBSD_FULL_BUILD_TEMPLATE
+  << : *FREEBSD_ENV
+
   install_script: pkg install -y seabios gmake ninja bash
-                                 pkgconf python bison perl5
+                                 pkgconf bison perl5
                                  yajl lzo2 pixman argp-standalone
-                                 libxml2 glib git python311
+                                 libxml2 glib git python3
 
   build_script:
     - cc --version
-    - export PYTHON=/usr/local/bin/python3.11
     - ./configure --with-system-seabios=/usr/local/share/seabios/bios.bin
     - gmake -j`sysctl -n hw.ncpu` clang=y
 
+freebsd_randconfig_template: &FREEBSD_RANDCONFIG_TEMPLATE
+  << : *FREEBSD_ENV
+
+  install_script: pkg install -y gmake python3 bison
+
+  build_script:
+    - cc --version
+    - gmake -j`sysctl -n hw.ncpu` -C xen clang=y \
+            KCONFIG_ALLCONFIG=tools/kconfig/allrandom.config randconfig
+    - gmake -j`sysctl -n hw.ncpu` build-xen clang=y
+
 task:
-  name: 'FreeBSD 13'
-  freebsd_instance:
-    image_family: freebsd-13-4
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 13: full build'
+  << : *FREEBSD_13
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
 
 task:
-  name: 'FreeBSD 14'
-  freebsd_instance:
-    image_family: freebsd-14-2
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 14: full build'
+  << : *FREEBSD_14
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
 
 task:
-  name: 'FreeBSD 15'
-  freebsd_instance:
-    image_family: freebsd-15-0-snap
-  << : *FREEBSD_TEMPLATE
+  name: 'FreeBSD 15: full build'
+  << : *FREEBSD_15
+  << : *FREEBSD_FULL_BUILD_TEMPLATE
+
+task:
+  name: 'FreeBSD 13: randconfig'
+  << : *FREEBSD_13
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
+
+task:
+  name: 'FreeBSD 14: randconfig'
+  << : *FREEBSD_14
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
+
+task:
+  name: 'FreeBSD 15: randconfig'
+  << : *FREEBSD_15
+  << : *FREEBSD_RANDCONFIG_TEMPLATE
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
Message-Id: <E1ta9WO-007aUT-1W@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:04 +0000

commit 0a14438052e65507041cf205c517ab0b4c786813
Author:     Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
AuthorDate: Tue Jan 21 09:17:44 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:17:44 2025 +0100

    tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
    
    Linux 6.12-rc2 fails to decompress with the current 128MiB, contrary to
    the code comment. It results in a failure like this:
    
        domainbuilder: detail: xc_dom_kernel_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/vmlinuz"
        domainbuilder: detail: xc_dom_malloc_filemap    : 12104 kB
        domainbuilder: detail: xc_dom_module_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/initramfs"
        domainbuilder: detail: xc_dom_malloc_filemap    : 7711 kB
        domainbuilder: detail: xc_dom_boot_xen_init: ver 4.19, caps xen-3.0-x86_64 hvm-3.0-x86_32 hvm-3.0-x86_32p hvm-3.0-x86_64
        domainbuilder: detail: xc_dom_parse_image: called
        domainbuilder: detail: xc_dom_find_loader: trying multiboot-binary loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying HVM-generic loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying Linux bzImage loader ...
        domainbuilder: detail: _xc_try_lzma_decode: XZ decompression error: Memory usage limit reached
        xc: error: panic: xg_dom_bzimageloader.c:761: xc_dom_probe_bzimage_kernel unable to XZ decompress kernel: Invalid kernel
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying ELF-generic loader ...
        domainbuilder: detail: loader probe failed
        xc: error: panic: xg_dom_core.c:689: xc_dom_find_loader: no loader found: Invalid kernel
        libxl: error: libxl_dom.c:566:libxl__build_dom: xc_dom_parse_image failed
    
    The important part: XZ decompression error: Memory usage limit reached
    
    This looks to be related to the following change in Linux:
    8653c909922743bceb4800e5cc26087208c9e0e6 ("xz: use 128 MiB dictionary and force single-threaded mode")
    
    Fix this by increasing the block size to 256MiB. And remove the
    misleading comment (from lack of better ideas).
    
    Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: e6472d46680ccd2b804ad73c19042a5811d036f0
    master date: 2024-12-19 17:33:54 +0000
---
 tools/libs/guest/xg_dom_bzimageloader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/libs/guest/xg_dom_bzimageloader.c b/tools/libs/guest/xg_dom_bzimageloader.c
index c6ee6d83e7..1fb4e5a1f7 100644
--- a/tools/libs/guest/xg_dom_bzimageloader.c
+++ b/tools/libs/guest/xg_dom_bzimageloader.c
@@ -272,8 +272,7 @@ static int _xc_try_lzma_decode(
     return retval;
 }
 
-/* 128 Mb is the minimum size (half-way) documented to work for all inputs. */
-#define LZMA_BLOCK_SIZE (128*1024*1024)
+#define LZMA_BLOCK_SIZE (256*1024*1024)
 
 static int xc_try_xz_decode(
     struct xc_dom_image *dom, void **blob, size_t *size)
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] xen/arch/x86: make objdump output user locale agnostic
Message-Id: <E1ta9WY-007aUw-1v@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:14 +0000

commit d260f797843417e65c4d035198f7a171b0dfa1f1
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Tue Jan 21 09:17:58 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:17:58 2025 +0100

    xen/arch/x86: make objdump output user locale agnostic
    
    The objdump output is fed to grep, so make sure it doesn't change with
    different user locales and break the grep parsing.
    This problem was identified while updating xen in Debian and the fix is
    needed for generating reproducible builds in varying environments.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 0d729221ab74c5d2571e71501dc63838acbf752a
    master date: 2024-12-30 21:40:37 +0000
---
 xen/arch/x86/arch.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk
index a683d4bedc..b88d097a84 100644
--- a/xen/arch/x86/arch.mk
+++ b/xen/arch/x86/arch.mk
@@ -111,7 +111,7 @@ endif
 ifeq ($(XEN_BUILD_PE),y)
 
 # Check if the linker produces fixups in PE by default
-efi-nr-fixups := $(shell $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
+efi-nr-fixups := $(shell LC_ALL=C $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
 
 ifeq ($(efi-nr-fixups),2)
 MKRELOC := :
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1ta9Wi-007aVx-2T@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:24 +0000

commit 816235e311e1dca0b2e37b1036e8e7e7f5f22433
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:18:08 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:18:08 2025 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    master commit: a1746cd4434dd27ca2da8430dfb10edc76264bb3
    master date: 2025-01-02 18:44:49 +0000
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 98a4521155..a398891bc0 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2392,7 +2392,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2541,6 +2541,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index fd8a20afa1..52caad5162 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -622,6 +623,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index ab92333673..c448997be5 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 9cdb5b2625..22d9e76e55 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102cU
 #define MSR_AMD64_BP_CFG		0xc001102eU
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3U
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027U
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 40f6ae0170..35351044f9 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -143,6 +144,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -363,6 +365,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -505,7 +509,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -529,10 +533,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -551,7 +556,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1120,7 +1126,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1145,22 +1151,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index d9eba5e9a7..9c98e49928 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -312,7 +312,9 @@ XEN_CPUFEATURE(FSRSC,              11*32+19) /*A  Fast Short REP SCASB */
 XEN_CPUFEATURE(AMD_PREFETCHI,      11*32+20) /*A  PREFETCHIT{0,1} Instructions */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1ta9Ws-007aXB-2r@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:34 +0000

commit 1b88dc9afcac6c33db309ac12969c1e60fce71fb
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:18:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:18:42 2025 +0100

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 555866cb56002849014a1409ecdfa3f436c0c2c4
    master date: 2025-01-06 12:24:05 +0000
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ccb5a37a72..ae573ee4c0 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -114,7 +114,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2093,56 +2093,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2202,6 +2156,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2227,6 +2217,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1ta9X2-007aYn-3D@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:44 +0000

commit 71d626f2f7da6003f5dccbd479a6818147ce66fd
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:19:14 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:14 2025 +0100

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    master commit: f29cc14de1d195bcd8312dcab2b5f8e634b57288
    master date: 2025-01-06 18:01:32 +0000
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 57ac984790..52808f9809 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1429,6 +1429,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index 9fe6e29751..31fbd326e5 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 97e6315bd9..d31e5db5b1 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -567,6 +567,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1ta9XD-007aaa-0N@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:22:55 +0000

commit 4abf7f1d6174b74640c219e1cc7cb768e8d7ea32
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:19:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:39 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: d3709d1324aa140f064b9c68da37547f459f8e8d
    master date: 2025-01-08 11:01:17 +0100
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 09ab75d035..4ef868de3d 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3592,12 +3592,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4815,7 +4818,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1ta9XN-007acT-0i@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:23:05 +0000

commit 4df28706ad8756b36de23b5173e8f4ce4c086c57
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:19:56 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:56 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
    master date: 2025-01-08 11:02:16 +0100
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 4ef868de3d..31475208d1 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1ta9XX-007adz-12@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:23:15 +0000

commit 30a8d910ca97ba460236bce53fb8e3c3035ea8fe
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:20:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:20:42 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
    master date: 2025-01-08 13:05:38 +0100
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 278ad38c2a..35237a00c4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -829,6 +829,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] xen/flask: Wire up XEN_DOMCTL_dt_overlay
Message-Id: <E1ta9Xh-007agw-1L@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:23:25 +0000

commit e7f96aa3f3d8b1ad2f0475a627f62763261df743
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:20:51 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:20:51 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_dt_overlay
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only dt overlay operation is attaching that can
    happen only after the domain is created. Dom0 can attach overlay to itself
    as well.
    
    Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 7fa1411676150634b1d6ca030e53b94c26a949dd
    master date: 2025-01-08 13:05:50 +0100
---
 tools/flask/policy/modules/dom0.te  | 2 +-
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index 16b8c9646d..f148bfbf27 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -40,7 +40,7 @@ allow dom0_t dom0_t:domain {
 };
 allow dom0_t dom0_t:domain2 {
 	set_cpu_policy gettsc settsc setscheduler set_vnumainfo
-	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy
+	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy dt_overlay
 };
 allow dom0_t dom0_t:resource { add remove };
 
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index ba9e91d302..def60da883 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -94,7 +94,7 @@ define(`manage_domain', `
 			getaddrsize pause unpause trigger shutdown destroy
 			setaffinity setdomainmaxmem getscheduler resume
 			setpodtarget getpodtarget getpagingmempool setpagingmempool };
-    allow $1 $2:domain2 set_vnumainfo;
+    allow $1 $2:domain2 { set_vnumainfo dt_overlay };
 ')
 
 # migrate_domain_out(priv, target)
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 35237a00c4..415edee251 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -841,6 +841,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_set_paging_mempool_size:
         return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__SETPAGINGMEMPOOL);
 
+    case XEN_DOMCTL_dt_overlay:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 7cbdb7ea64..78fe37583b 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -253,6 +253,8 @@ class domain2
     get_cpu_policy
 # XEN_DOMCTL_vuart_op
     vuart_op
+# XEN_DOMCTL_dt_overlay
+    dt_overlay
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1ta9Xr-007aiA-1e@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:23:35 +0000

commit 4803a3c5b5f1f131bd87386c33b285a67126c851
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue Jan 21 09:21:01 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:21:01 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
    master date: 2025-01-09 17:34:01 +0100
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index aac7d4b93f..cc93c52849 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -977,6 +977,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -990,14 +991,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] update Xen version to 4.18.5-pre
Message-Id: <E1ta9rg-007dO5-2B@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:04 +0000

commit 0f4364da17b837ad7e6cee3d725adf0225b2088d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:27:05 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:27:05 2025 +0100

    update Xen version to 4.18.5-pre
---
 xen/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/Makefile b/xen/Makefile
index a4e7a2f6d1..684411fa67 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -6,7 +6,7 @@ this-makefile := $(call lastword,$(MAKEFILE_LIST))
 # All other places this is stored (eg. compile.h) should be autogenerated.
 export XEN_VERSION       = 4
 export XEN_SUBVERSION    = 18
-export XEN_EXTRAVERSION ?= .4$(XEN_VENDORVERSION)
+export XEN_EXTRAVERSION ?= .5-pre$(XEN_VENDORVERSION)
 export XEN_FULLVERSION   = $(XEN_VERSION).$(XEN_SUBVERSION)$(XEN_EXTRAVERSION)
 -include xen-version
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86emul: correct #UD check for AVX512-FP16 complex multiplications
Message-Id: <E1ta9rq-007dR5-2Y@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:14 +0000

commit 4c894c519db69c912d57a122f717ac3d6c81254c
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:27:45 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:27:45 2025 +0100

    x86emul: correct #UD check for AVX512-FP16 complex multiplications
    
    avx512_vlen_check()'s argument was inverted, while the surrounding
    conditional wrongly forced the EVEX.L'L check for the scalar forms when
    embedded rounding was in effect.
    
    Fixes: d14c52cba0f5 ("x86emul: handle AVX512-FP16 complex multiplication insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: a30d438ce58b70c5955f5d37f776086ab8f88623
    master date: 2024-08-19 15:32:31 +0200
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 2c6bc8df2c..85d8ea7172 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7948,8 +7948,8 @@ x86_emulate(
         generate_exception_if(modrm_reg == src1 ||
                               (ea.type != OP_MEM && modrm_reg == modrm_rm),
                               X86_EXC_UD);
-        if ( ea.type != OP_REG || (b & 1) || !evex.brs )
-            avx512_vlen_check(!(b & 1));
+        if ( ea.type != OP_REG || !evex.brs )
+            avx512_vlen_check(b & 1);
         goto simd_zmm;
     }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
Message-Id: <E1ta9s0-007dRs-2t@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:24 +0000

commit d7f45ead66a3fc6b7e2150bf10d34f1665488b3d
Author:     Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
AuthorDate: Tue Jan 21 09:28:13 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:13 2025 +0100

    tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
    
    Linux 6.12-rc2 fails to decompress with the current 128MiB, contrary to
    the code comment. It results in a failure like this:
    
        domainbuilder: detail: xc_dom_kernel_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/vmlinuz"
        domainbuilder: detail: xc_dom_malloc_filemap    : 12104 kB
        domainbuilder: detail: xc_dom_module_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/initramfs"
        domainbuilder: detail: xc_dom_malloc_filemap    : 7711 kB
        domainbuilder: detail: xc_dom_boot_xen_init: ver 4.19, caps xen-3.0-x86_64 hvm-3.0-x86_32 hvm-3.0-x86_32p hvm-3.0-x86_64
        domainbuilder: detail: xc_dom_parse_image: called
        domainbuilder: detail: xc_dom_find_loader: trying multiboot-binary loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying HVM-generic loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying Linux bzImage loader ...
        domainbuilder: detail: _xc_try_lzma_decode: XZ decompression error: Memory usage limit reached
        xc: error: panic: xg_dom_bzimageloader.c:761: xc_dom_probe_bzimage_kernel unable to XZ decompress kernel: Invalid kernel
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying ELF-generic loader ...
        domainbuilder: detail: loader probe failed
        xc: error: panic: xg_dom_core.c:689: xc_dom_find_loader: no loader found: Invalid kernel
        libxl: error: libxl_dom.c:566:libxl__build_dom: xc_dom_parse_image failed
    
    The important part: XZ decompression error: Memory usage limit reached
    
    This looks to be related to the following change in Linux:
    8653c909922743bceb4800e5cc26087208c9e0e6 ("xz: use 128 MiB dictionary and force single-threaded mode")
    
    Fix this by increasing the block size to 256MiB. And remove the
    misleading comment (from lack of better ideas).
    
    Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: e6472d46680ccd2b804ad73c19042a5811d036f0
    master date: 2024-12-19 17:33:54 +0000
---
 tools/libs/guest/xg_dom_bzimageloader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/libs/guest/xg_dom_bzimageloader.c b/tools/libs/guest/xg_dom_bzimageloader.c
index c6ee6d83e7..1fb4e5a1f7 100644
--- a/tools/libs/guest/xg_dom_bzimageloader.c
+++ b/tools/libs/guest/xg_dom_bzimageloader.c
@@ -272,8 +272,7 @@ static int _xc_try_lzma_decode(
     return retval;
 }
 
-/* 128 Mb is the minimum size (half-way) documented to work for all inputs. */
-#define LZMA_BLOCK_SIZE (128*1024*1024)
+#define LZMA_BLOCK_SIZE (256*1024*1024)
 
 static int xc_try_xz_decode(
     struct xc_dom_image *dom, void **blob, size_t *size)
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] xen/arch/x86: make objdump output user locale agnostic
Message-Id: <E1ta9sB-007dSv-00@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:35 +0000

commit b474783f1cfd36ee5e495bc6d70273820ce94883
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Tue Jan 21 09:28:28 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:28 2025 +0100

    xen/arch/x86: make objdump output user locale agnostic
    
    The objdump output is fed to grep, so make sure it doesn't change with
    different user locales and break the grep parsing.
    This problem was identified while updating xen in Debian and the fix is
    needed for generating reproducible builds in varying environments.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 0d729221ab74c5d2571e71501dc63838acbf752a
    master date: 2024-12-30 21:40:37 +0000
---
 xen/arch/x86/arch.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk
index aa55f54f69..28217c9ace 100644
--- a/xen/arch/x86/arch.mk
+++ b/xen/arch/x86/arch.mk
@@ -110,7 +110,7 @@ endif
 ifeq ($(XEN_BUILD_PE),y)
 
 # Check if the linker produces fixups in PE by default
-efi-nr-fixups := $(shell $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
+efi-nr-fixups := $(shell LC_ALL=C $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
 
 ifeq ($(efi-nr-fixups),2)
 MKRELOC := :
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1ta9sL-007dTN-0N@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:45 +0000

commit 8bced9a15c8cae0395713bc1ae06469c1b0f28a5
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:28:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:42 2025 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    master commit: a1746cd4434dd27ca2da8430dfb10edc76264bb3
    master date: 2025-01-02 18:44:49 +0000
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index d857bd0f89..03346aeba5 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2376,7 +2376,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2525,6 +2525,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 89faef05ef..7745d5d2d5 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -650,6 +651,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index ab92333673..c448997be5 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index b1d4dfd261..3c11d1f43c 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102c
 #define MSR_AMD64_BP_CFG		0xc001102e
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 12c19b7eca..51a66a144e 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -143,6 +144,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -363,6 +365,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -505,7 +509,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -529,10 +533,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -551,7 +556,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1120,7 +1126,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1145,22 +1151,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 2dd8018f24..603a448cb3 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -293,7 +293,9 @@ XEN_CPUFEATURE(AUTO_IBRS,          11*32+ 8) /*S  Automatic IBRS */
 XEN_CPUFEATURE(CPUID_USER_DIS,     11*32+17) /*   CPUID disable for CPL > 0 software */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1ta9sV-007dVh-0l@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:44:55 +0000

commit 02e0528060c4e2430e219a8e92775cd0a4b21dc2
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:29:34 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:29:34 2025 +0100

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 555866cb56002849014a1409ecdfa3f436c0c2c4
    master date: 2025-01-06 12:24:05 +0000
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index d702ffd38c..ea8026634a 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -115,7 +115,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2126,56 +2126,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2235,6 +2189,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2260,6 +2250,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1ta9sf-007dWf-1F@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:45:05 +0000

commit 399a9b0642b6c63463bce5766eacdc961e0b7956
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:29:49 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:29:49 2025 +0100

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    master commit: f29cc14de1d195bcd8312dcab2b5f8e634b57288
    master date: 2025-01-06 18:01:32 +0000
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index cfce4cc040..bf796e4688 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1429,6 +1429,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index dc735ee480..7c459b86c6 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 18266b9521..b765dd2d38 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -567,6 +567,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1ta9sp-007dXC-1c@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:45:15 +0000

commit 35489e3aaa05862bd8c3f37f7ca74b800a2deda0
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:30:04 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:04 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: d3709d1324aa140f064b9c68da37547f459f8e8d
    master date: 2025-01-08 11:01:17 +0100
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 85d8ea7172..f109c335a7 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3592,12 +3592,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4815,7 +4818,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1ta9sz-007dZl-1v@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:45:25 +0000

commit 04ae3260d95c1cb33361f8150713769b10bd9388
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:30:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:25 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
    master date: 2025-01-08 11:02:16 +0100
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index f109c335a7..f2436473b9 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1ta9t9-007daK-2J@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:45:35 +0000

commit 4dce231463459a82c3d7365136aa9c4d227dc471
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:30:49 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:49 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
    master date: 2025-01-08 13:05:38 +0100
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 278ad38c2a..35237a00c4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -829,6 +829,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1ta9tJ-007dbH-2c@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 08:45:45 +0000

commit 77d95386a783273ded28e92fc32a603c2ccbaa60
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue Jan 21 09:30:59 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:59 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
    master date: 2025-01-09 17:34:01 +0100
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index e6ec556603..3caf74ae77 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -974,6 +974,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -987,14 +988,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
Message-Id: <E1taAnh-007m0j-2h@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:01 +0000

commit 0a14438052e65507041cf205c517ab0b4c786813
Author:     Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
AuthorDate: Tue Jan 21 09:17:44 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:17:44 2025 +0100

    tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
    
    Linux 6.12-rc2 fails to decompress with the current 128MiB, contrary to
    the code comment. It results in a failure like this:
    
        domainbuilder: detail: xc_dom_kernel_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/vmlinuz"
        domainbuilder: detail: xc_dom_malloc_filemap    : 12104 kB
        domainbuilder: detail: xc_dom_module_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/initramfs"
        domainbuilder: detail: xc_dom_malloc_filemap    : 7711 kB
        domainbuilder: detail: xc_dom_boot_xen_init: ver 4.19, caps xen-3.0-x86_64 hvm-3.0-x86_32 hvm-3.0-x86_32p hvm-3.0-x86_64
        domainbuilder: detail: xc_dom_parse_image: called
        domainbuilder: detail: xc_dom_find_loader: trying multiboot-binary loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying HVM-generic loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying Linux bzImage loader ...
        domainbuilder: detail: _xc_try_lzma_decode: XZ decompression error: Memory usage limit reached
        xc: error: panic: xg_dom_bzimageloader.c:761: xc_dom_probe_bzimage_kernel unable to XZ decompress kernel: Invalid kernel
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying ELF-generic loader ...
        domainbuilder: detail: loader probe failed
        xc: error: panic: xg_dom_core.c:689: xc_dom_find_loader: no loader found: Invalid kernel
        libxl: error: libxl_dom.c:566:libxl__build_dom: xc_dom_parse_image failed
    
    The important part: XZ decompression error: Memory usage limit reached
    
    This looks to be related to the following change in Linux:
    8653c909922743bceb4800e5cc26087208c9e0e6 ("xz: use 128 MiB dictionary and force single-threaded mode")
    
    Fix this by increasing the block size to 256MiB. And remove the
    misleading comment (from lack of better ideas).
    
    Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: e6472d46680ccd2b804ad73c19042a5811d036f0
    master date: 2024-12-19 17:33:54 +0000
---
 tools/libs/guest/xg_dom_bzimageloader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/libs/guest/xg_dom_bzimageloader.c b/tools/libs/guest/xg_dom_bzimageloader.c
index c6ee6d83e7..1fb4e5a1f7 100644
--- a/tools/libs/guest/xg_dom_bzimageloader.c
+++ b/tools/libs/guest/xg_dom_bzimageloader.c
@@ -272,8 +272,7 @@ static int _xc_try_lzma_decode(
     return retval;
 }
 
-/* 128 Mb is the minimum size (half-way) documented to work for all inputs. */
-#define LZMA_BLOCK_SIZE (128*1024*1024)
+#define LZMA_BLOCK_SIZE (256*1024*1024)
 
 static int xc_try_xz_decode(
     struct xc_dom_image *dom, void **blob, size_t *size)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] xen/arch/x86: make objdump output user locale agnostic
Message-Id: <E1taAnr-007m1x-3D@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:11 +0000

commit d260f797843417e65c4d035198f7a171b0dfa1f1
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Tue Jan 21 09:17:58 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:17:58 2025 +0100

    xen/arch/x86: make objdump output user locale agnostic
    
    The objdump output is fed to grep, so make sure it doesn't change with
    different user locales and break the grep parsing.
    This problem was identified while updating xen in Debian and the fix is
    needed for generating reproducible builds in varying environments.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 0d729221ab74c5d2571e71501dc63838acbf752a
    master date: 2024-12-30 21:40:37 +0000
---
 xen/arch/x86/arch.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk
index a683d4bedc..b88d097a84 100644
--- a/xen/arch/x86/arch.mk
+++ b/xen/arch/x86/arch.mk
@@ -111,7 +111,7 @@ endif
 ifeq ($(XEN_BUILD_PE),y)
 
 # Check if the linker produces fixups in PE by default
-efi-nr-fixups := $(shell $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
+efi-nr-fixups := $(shell LC_ALL=C $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
 
 ifeq ($(efi-nr-fixups),2)
 MKRELOC := :
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1taAo2-007m2f-0U@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:22 +0000

commit 816235e311e1dca0b2e37b1036e8e7e7f5f22433
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:18:08 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:18:08 2025 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    master commit: a1746cd4434dd27ca2da8430dfb10edc76264bb3
    master date: 2025-01-02 18:44:49 +0000
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 98a4521155..a398891bc0 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2392,7 +2392,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2541,6 +2541,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index fd8a20afa1..52caad5162 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -622,6 +623,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index ab92333673..c448997be5 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 9cdb5b2625..22d9e76e55 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102cU
 #define MSR_AMD64_BP_CFG		0xc001102eU
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3U
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027U
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 40f6ae0170..35351044f9 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -143,6 +144,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -363,6 +365,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -505,7 +509,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -529,10 +533,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -551,7 +556,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1120,7 +1126,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1145,22 +1151,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index d9eba5e9a7..9c98e49928 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -312,7 +312,9 @@ XEN_CPUFEATURE(FSRSC,              11*32+19) /*A  Fast Short REP SCASB */
 XEN_CPUFEATURE(AMD_PREFETCHI,      11*32+20) /*A  PREFETCHIT{0,1} Instructions */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1taAoC-007m3N-0s@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:32 +0000

commit 1b88dc9afcac6c33db309ac12969c1e60fce71fb
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:18:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:18:42 2025 +0100

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 555866cb56002849014a1409ecdfa3f436c0c2c4
    master date: 2025-01-06 12:24:05 +0000
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ccb5a37a72..ae573ee4c0 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -114,7 +114,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2093,56 +2093,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2202,6 +2156,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2227,6 +2217,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1taAoM-007m6O-1L@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:42 +0000

commit 71d626f2f7da6003f5dccbd479a6818147ce66fd
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:19:14 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:14 2025 +0100

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    master commit: f29cc14de1d195bcd8312dcab2b5f8e634b57288
    master date: 2025-01-06 18:01:32 +0000
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 57ac984790..52808f9809 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1429,6 +1429,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index 9fe6e29751..31fbd326e5 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 97e6315bd9..d31e5db5b1 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -567,6 +567,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1taAoW-007m7F-1h@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:44:52 +0000

commit 4abf7f1d6174b74640c219e1cc7cb768e8d7ea32
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:19:39 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:39 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: d3709d1324aa140f064b9c68da37547f459f8e8d
    master date: 2025-01-08 11:01:17 +0100
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 09ab75d035..4ef868de3d 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3592,12 +3592,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4815,7 +4818,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1taAog-007m8K-23@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:45:02 +0000

commit 4df28706ad8756b36de23b5173e8f4ce4c086c57
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:19:56 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:19:56 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
    master date: 2025-01-08 11:02:16 +0100
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 4ef868de3d..31475208d1 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1taAoq-007m8l-2N@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:45:12 +0000

commit 30a8d910ca97ba460236bce53fb8e3c3035ea8fe
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:20:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:20:42 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
    master date: 2025-01-08 13:05:38 +0100
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 278ad38c2a..35237a00c4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -829,6 +829,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] xen/flask: Wire up XEN_DOMCTL_dt_overlay
Message-Id: <E1taAp0-007m9a-2p@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:45:22 +0000

commit e7f96aa3f3d8b1ad2f0475a627f62763261df743
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:20:51 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:20:51 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_dt_overlay
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only dt overlay operation is attaching that can
    happen only after the domain is created. Dom0 can attach overlay to itself
    as well.
    
    Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 7fa1411676150634b1d6ca030e53b94c26a949dd
    master date: 2025-01-08 13:05:50 +0100
---
 tools/flask/policy/modules/dom0.te  | 2 +-
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index 16b8c9646d..f148bfbf27 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -40,7 +40,7 @@ allow dom0_t dom0_t:domain {
 };
 allow dom0_t dom0_t:domain2 {
 	set_cpu_policy gettsc settsc setscheduler set_vnumainfo
-	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy
+	get_vnumainfo psr_cmt_op psr_alloc get_cpu_policy dt_overlay
 };
 allow dom0_t dom0_t:resource { add remove };
 
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index ba9e91d302..def60da883 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -94,7 +94,7 @@ define(`manage_domain', `
 			getaddrsize pause unpause trigger shutdown destroy
 			setaffinity setdomainmaxmem getscheduler resume
 			setpodtarget getpodtarget getpagingmempool setpagingmempool };
-    allow $1 $2:domain2 set_vnumainfo;
+    allow $1 $2:domain2 { set_vnumainfo dt_overlay };
 ')
 
 # migrate_domain_out(priv, target)
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 35237a00c4..415edee251 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -841,6 +841,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_set_paging_mempool_size:
         return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__SETPAGINGMEMPOOL);
 
+    case XEN_DOMCTL_dt_overlay:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__DT_OVERLAY);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 7cbdb7ea64..78fe37583b 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -253,6 +253,8 @@ class domain2
     get_cpu_policy
 # XEN_DOMCTL_vuart_op
     vuart_op
+# XEN_DOMCTL_dt_overlay
+    dt_overlay
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.19] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1taApA-007mAY-3C@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:45:32 +0000

commit 4803a3c5b5f1f131bd87386c33b285a67126c851
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue Jan 21 09:21:01 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:21:01 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
    master date: 2025-01-09 17:34:01 +0100
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index aac7d4b93f..cc93c52849 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -977,6 +977,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -990,14 +991,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] update Xen version to 4.18.5-pre
Message-Id: <E1taAyM-007nNe-1T@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:02 +0000

commit 0f4364da17b837ad7e6cee3d725adf0225b2088d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:27:05 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:27:05 2025 +0100

    update Xen version to 4.18.5-pre
---
 xen/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/Makefile b/xen/Makefile
index a4e7a2f6d1..684411fa67 100644
--- a/xen/Makefile
+++ b/xen/Makefile
@@ -6,7 +6,7 @@ this-makefile := $(call lastword,$(MAKEFILE_LIST))
 # All other places this is stored (eg. compile.h) should be autogenerated.
 export XEN_VERSION       = 4
 export XEN_SUBVERSION    = 18
-export XEN_EXTRAVERSION ?= .4$(XEN_VENDORVERSION)
+export XEN_EXTRAVERSION ?= .5-pre$(XEN_VENDORVERSION)
 export XEN_FULLVERSION   = $(XEN_VERSION).$(XEN_SUBVERSION)$(XEN_EXTRAVERSION)
 -include xen-version
 
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86emul: correct #UD check for AVX512-FP16 complex multiplications
Message-Id: <E1taAyW-007nOM-1t@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:12 +0000

commit 4c894c519db69c912d57a122f717ac3d6c81254c
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:27:45 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:27:45 2025 +0100

    x86emul: correct #UD check for AVX512-FP16 complex multiplications
    
    avx512_vlen_check()'s argument was inverted, while the surrounding
    conditional wrongly forced the EVEX.L'L check for the scalar forms when
    embedded rounding was in effect.
    
    Fixes: d14c52cba0f5 ("x86emul: handle AVX512-FP16 complex multiplication insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: a30d438ce58b70c5955f5d37f776086ab8f88623
    master date: 2024-08-19 15:32:31 +0200
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 2c6bc8df2c..85d8ea7172 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7948,8 +7948,8 @@ x86_emulate(
         generate_exception_if(modrm_reg == src1 ||
                               (ea.type != OP_MEM && modrm_reg == modrm_rm),
                               X86_EXC_UD);
-        if ( ea.type != OP_REG || (b & 1) || !evex.brs )
-            avx512_vlen_check(!(b & 1));
+        if ( ea.type != OP_REG || !evex.brs )
+            avx512_vlen_check(b & 1);
         goto simd_zmm;
     }
 
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
Message-Id: <E1taAyg-007nPX-2B@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:22 +0000

commit d7f45ead66a3fc6b7e2150bf10d34f1665488b3d
Author:     Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
AuthorDate: Tue Jan 21 09:28:13 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:13 2025 +0100

    tools/xg: increase LZMA_BLOCK_SIZE for uncompressing the kernel
    
    Linux 6.12-rc2 fails to decompress with the current 128MiB, contrary to
    the code comment. It results in a failure like this:
    
        domainbuilder: detail: xc_dom_kernel_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/vmlinuz"
        domainbuilder: detail: xc_dom_malloc_filemap    : 12104 kB
        domainbuilder: detail: xc_dom_module_file: filename="/var/lib/qubes/vm-kernels/6.12-rc2-1.1.fc37/initramfs"
        domainbuilder: detail: xc_dom_malloc_filemap    : 7711 kB
        domainbuilder: detail: xc_dom_boot_xen_init: ver 4.19, caps xen-3.0-x86_64 hvm-3.0-x86_32 hvm-3.0-x86_32p hvm-3.0-x86_64
        domainbuilder: detail: xc_dom_parse_image: called
        domainbuilder: detail: xc_dom_find_loader: trying multiboot-binary loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying HVM-generic loader ...
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying Linux bzImage loader ...
        domainbuilder: detail: _xc_try_lzma_decode: XZ decompression error: Memory usage limit reached
        xc: error: panic: xg_dom_bzimageloader.c:761: xc_dom_probe_bzimage_kernel unable to XZ decompress kernel: Invalid kernel
        domainbuilder: detail: loader probe failed
        domainbuilder: detail: xc_dom_find_loader: trying ELF-generic loader ...
        domainbuilder: detail: loader probe failed
        xc: error: panic: xg_dom_core.c:689: xc_dom_find_loader: no loader found: Invalid kernel
        libxl: error: libxl_dom.c:566:libxl__build_dom: xc_dom_parse_image failed
    
    The important part: XZ decompression error: Memory usage limit reached
    
    This looks to be related to the following change in Linux:
    8653c909922743bceb4800e5cc26087208c9e0e6 ("xz: use 128 MiB dictionary and force single-threaded mode")
    
    Fix this by increasing the block size to 256MiB. And remove the
    misleading comment (from lack of better ideas).
    
    Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: e6472d46680ccd2b804ad73c19042a5811d036f0
    master date: 2024-12-19 17:33:54 +0000
---
 tools/libs/guest/xg_dom_bzimageloader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/libs/guest/xg_dom_bzimageloader.c b/tools/libs/guest/xg_dom_bzimageloader.c
index c6ee6d83e7..1fb4e5a1f7 100644
--- a/tools/libs/guest/xg_dom_bzimageloader.c
+++ b/tools/libs/guest/xg_dom_bzimageloader.c
@@ -272,8 +272,7 @@ static int _xc_try_lzma_decode(
     return retval;
 }
 
-/* 128 Mb is the minimum size (half-way) documented to work for all inputs. */
-#define LZMA_BLOCK_SIZE (128*1024*1024)
+#define LZMA_BLOCK_SIZE (256*1024*1024)
 
 static int xc_try_xz_decode(
     struct xc_dom_image *dom, void **blob, size_t *size)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] xen/arch/x86: make objdump output user locale agnostic
Message-Id: <E1taAyq-007nQM-2Z@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:32 +0000

commit b474783f1cfd36ee5e495bc6d70273820ce94883
Author:     Maximilian Engelhardt <maxi@daemonizer.de>
AuthorDate: Tue Jan 21 09:28:28 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:28 2025 +0100

    xen/arch/x86: make objdump output user locale agnostic
    
    The objdump output is fed to grep, so make sure it doesn't change with
    different user locales and break the grep parsing.
    This problem was identified while updating xen in Debian and the fix is
    needed for generating reproducible builds in varying environments.
    
    Signed-off-by: Maximilian Engelhardt <maxi@daemonizer.de>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 0d729221ab74c5d2571e71501dc63838acbf752a
    master date: 2024-12-30 21:40:37 +0000
---
 xen/arch/x86/arch.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk
index aa55f54f69..28217c9ace 100644
--- a/xen/arch/x86/arch.mk
+++ b/xen/arch/x86/arch.mk
@@ -110,7 +110,7 @@ endif
 ifeq ($(XEN_BUILD_PE),y)
 
 # Check if the linker produces fixups in PE by default
-efi-nr-fixups := $(shell $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
+efi-nr-fixups := $(shell LC_ALL=C $(OBJDUMP) -p $(efi-check).efi | grep '^[[:blank:]]*reloc[[:blank:]]*[0-9][[:blank:]].*DIR64$$' | wc -l)
 
 ifeq ($(efi-nr-fixups),2)
 MKRELOC := :
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1taAz0-007nRC-34@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:42 +0000

commit 8bced9a15c8cae0395713bc1ae06469c1b0f28a5
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:28:42 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:28:42 2025 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    master commit: a1746cd4434dd27ca2da8430dfb10edc76264bb3
    master date: 2025-01-02 18:44:49 +0000
---
 docs/misc/xen-command-line.pandoc           |  9 ++++-
 xen/arch/x86/cpu-policy.c                   | 21 ++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 51 ++++++++++++++++++++++-------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 96 insertions(+), 20 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index d857bd0f89..03346aeba5 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2376,7 +2376,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2525,6 +2525,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 89faef05ef..7745d5d2d5 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __read_mostly       raw_cpu_policy;
@@ -650,6 +651,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index ab92333673..c448997be5 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1009,16 +1009,33 @@ static void cf_check fam17_disable_c6(void *arg)
 	wrmsrl(MSR_AMD_CSTATE_CFG, val & mask);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1027,7 +1044,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1297,7 +1314,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index b1d4dfd261..3c11d1f43c 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -412,6 +412,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102c
 #define MSR_AMD64_BP_CFG		0xc001102e
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 72347ef2b9..0772254189 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -90,6 +90,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 12c19b7eca..51a66a144e 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -83,6 +83,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -143,6 +144,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -363,6 +365,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -505,7 +509,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -529,10 +533,11 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_BTC_NO))         ? " BTC_NO"         : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -551,7 +556,8 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_FB_CLEAR_CTRL)                  ? " FB_CLEAR_CTRL"  : "",
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
-           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "");
+           (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "");
 
     /* Compiled-in support which pertains to mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ||
@@ -1120,7 +1126,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1145,22 +1151,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 2dd8018f24..603a448cb3 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -293,7 +293,9 @@ XEN_CPUFEATURE(AUTO_IBRS,          11*32+ 8) /*S  Automatic IBRS */
 XEN_CPUFEATURE(CPUID_USER_DIS,     11*32+17) /*   CPUID disable for CPL > 0 software */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
Message-Id: <E1taAzB-007nSY-0A@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:55:53 +0000

commit 02e0528060c4e2430e219a8e92775cd0a4b21dc2
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:29:34 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:29:34 2025 +0100

    x86/traps: Rework LER initialisation and support Zen5/Diamond Rapids
    
    AMD have always used the architectural MSRs for LER.  As the first processor
    to support LER was the K7 (which was 32bit), we can assume it's presence
    unconditionally in 64bit mode.
    
    Intel are about to run out of space in Family 6 and start using 19.  It is
    only the Pentium 4 which uses non-architectural LER MSRs.
    
    percpu_traps_init(), which runs on every CPU, contains a lot of code which
    should be init-only, and is the only reason why opt_ler can't be in initdata.
    
    Write a brand new init_ler() which expects all future Intel and AMD CPUs to
    continue using the architectural MSRs, and does all setup together.  Call it
    from trap_init(), and remove the setup logic percpu_traps_init() except for
    the single path configuring MSR_IA32_DEBUGCTLMSR.
    
    Leave behind a warning if the user asked for LER and Xen couldn't enable it.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 555866cb56002849014a1409ecdfa3f436c0c2c4
    master date: 2025-01-06 12:24:05 +0000
---
 xen/arch/x86/traps.c | 86 ++++++++++++++++++++++++----------------------------
 1 file changed, 39 insertions(+), 47 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index d702ffd38c..ea8026634a 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -115,7 +115,7 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page);
 static int debug_stack_lines = 20;
 integer_param("debug_stack_lines", debug_stack_lines);
 
-static bool __ro_after_init opt_ler;
+static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 /* LastExceptionFromIP on this hardware.  Zero if LER is not in use. */
@@ -2126,56 +2126,10 @@ static void __init set_intr_gate(unsigned int n, void *addr)
     __set_intr_gate(n, 0, addr);
 }
 
-static unsigned int noinline __init calc_ler_msr(void)
-{
-    switch ( boot_cpu_data.x86_vendor )
-    {
-    case X86_VENDOR_INTEL:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-            return MSR_IA32_LASTINTFROMIP;
-
-        case 15:
-            return MSR_P4_LER_FROM_LIP;
-        }
-        break;
-
-    case X86_VENDOR_AMD:
-        switch ( boot_cpu_data.x86 )
-        {
-        case 6:
-        case 0xf ... 0x19:
-            return MSR_IA32_LASTINTFROMIP;
-        }
-        break;
-
-    case X86_VENDOR_HYGON:
-        return MSR_IA32_LASTINTFROMIP;
-    }
-
-    return 0;
-}
-
 void percpu_traps_init(void)
 {
     subarch_percpu_traps_init();
 
-    if ( !opt_ler )
-        return;
-
-    if ( !ler_msr )
-    {
-        ler_msr = calc_ler_msr();
-        if ( !ler_msr )
-        {
-            opt_ler = false;
-            return;
-        }
-
-        setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
-    }
-
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
@@ -2235,6 +2189,42 @@ void __init init_idt_traps(void)
         this_cpu(compat_gdt) = boot_compat_gdt;
 }
 
+static void __init init_ler(void)
+{
+    unsigned int msr = 0;
+
+    if ( !opt_ler )
+        return;
+
+    /*
+     * Intel Pentium 4 is the only known CPU to not use the architectural MSR
+     * indicies.
+     */
+    switch ( boot_cpu_data.x86_vendor )
+    {
+    case X86_VENDOR_INTEL:
+        if ( boot_cpu_data.x86 == 0xf )
+        {
+            msr = MSR_P4_LER_FROM_LIP;
+            break;
+        }
+        fallthrough;
+    case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
+        msr = MSR_IA32_LASTINTFROMIP;
+        break;
+    }
+
+    if ( msr == 0 )
+    {
+        printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n");
+        return;
+    }
+
+    ler_msr = msr;
+    setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
+}
+
 extern void (*const autogen_entrypoints[X86_NR_VECTORS])(void);
 void __init trap_init(void)
 {
@@ -2260,6 +2250,8 @@ void __init trap_init(void)
         }
     }
 
+    init_ler();
+
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
     this_cpu(gdt_l1e) =
         l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86/amd: Misc setup for Fam1Ah processors
Message-Id: <E1taAzL-007nTk-0W@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:56:03 +0000

commit 399a9b0642b6c63463bce5766eacdc961e0b7956
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 09:29:49 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:29:49 2025 +0100

    x86/amd: Misc setup for Fam1Ah processors
    
    Fam1Ah is similar to Fam19h in these regards.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
    master commit: f29cc14de1d195bcd8312dcab2b5f8e634b57288
    master date: 2025-01-06 18:01:32 +0000
---
 xen/arch/x86/acpi/cpu_idle.c     | 1 +
 xen/arch/x86/cpu/microcode/amd.c | 4 ++++
 xen/arch/x86/cpu/vpmu_amd.c      | 1 +
 3 files changed, 6 insertions(+)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index cfce4cc040..bf796e4688 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1429,6 +1429,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     switch ( c->x86 )
     {
+    case 0x1a:
     case 0x19:
     case 0x18:
         if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index dc735ee480..7c459b86c6 100644
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size)
 #define F16H_MPB_MAX_SIZE 3458
 #define F17H_MPB_MAX_SIZE 3200
 #define F19H_MPB_MAX_SIZE 5568
+#define F1AH_MPB_MAX_SIZE 15296
 
     switch ( boot_cpu_data.x86 )
     {
@@ -132,6 +133,9 @@ static bool verify_patch_size(uint32_t patch_size)
     case 0x19:
         max_size = F19H_MPB_MAX_SIZE;
         break;
+    case 0x1a:
+        max_size = F1AH_MPB_MAX_SIZE;
+        break;
     default:
         max_size = F1XH_MPB_MAX_SIZE;
         break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 18266b9521..b765dd2d38 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -567,6 +567,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
     case 0x15:
     case 0x17:
     case 0x19:
+    case 0x1a:
         num_counters = F15H_NUM_COUNTERS;
         counters = AMD_F15H_COUNTERS;
         ctrls = AMD_F15H_CTRLS;
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86emul: VCVT{,U}DQ2PD ignores embedded rounding
Message-Id: <E1taAzV-007nUO-0p@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:56:13 +0000

commit 35489e3aaa05862bd8c3f37f7ca74b800a2deda0
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:30:04 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:04 2025 +0100

    x86emul: VCVT{,U}DQ2PD ignores embedded rounding
    
    IOW we shouldn't raise #UD in that case. Be on the safe side though and
    only encode fully legitimate forms into the stub to be executed.
    
    Things weren't quite right for VCVT{,U}SI2SD either, in the attempt to
    be on the safe side: Clearing EVEX.L'L isn't useful; it's EVEX.b which
    primarily needs clearing. Also reflect the somewhat improved doc
    situation in the comment there.
    
    Fixes: ed806f373730 ("x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns")
    Fixes: baf4a376f550 ("x86emul: support AVX512F legacy-equivalent scalar int/FP conversion insns")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: d3709d1324aa140f064b9c68da37547f459f8e8d
    master date: 2025-01-08 11:01:17 +0100
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 85d8ea7172..f109c335a7 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3592,12 +3592,15 @@ x86_emulate(
         if ( !mode_64bit() )
             evex.w = 0;
         /*
-         * SDM version 067 claims that exception type E10NF implies #UD when
-         * EVEX.L'L is non-zero for 32-bit VCVT{,U}SI2SD. Experimentally this
-         * cannot be confirmed, but be on the safe side for the stub.
+         * While SDM version 085 has explicit wording towards embedded rounding
+         * being ignored, it's still not entirely unambiguous with the exception
+         * type referred to. Be on the safe side for the stub.
          */
         if ( !evex.w && evex.pfx == vex_f2 )
+        {
+            evex.brs = 0;
             evex.lr = 0;
+        }
         opc[1] = (modrm & 0x38) | 0xc0;
         insn_bytes = EVEX_PFX_BYTES + 2;
         opc[2] = 0xc3;
@@ -4815,7 +4818,16 @@ x86_emulate(
         else
         {
             host_and_vcpu_must_have(avx512f);
-            generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+            /*
+             * While SDM version 085 has explicit wording towards embedded
+             * rounding being ignored, it's still not entirely unambiguous with
+             * the exception type referred to. Be on the safe side for the stub.
+             */
+            if ( ea.type != OP_MEM && evex.brs )
+            {
+                evex.brs = 0;
+                evex.lr = 2;
+            }
         }
         if ( ea.type != OP_REG || !evex.brs )
             avx512_vlen_check(false);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] x86emul: correct put_fpu()'s segment selector handling
Message-Id: <E1taAzf-007nVH-18@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:56:23 +0000

commit 04ae3260d95c1cb33361f8150713769b10bd9388
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue Jan 21 09:30:25 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:25 2025 +0100

    x86emul: correct put_fpu()'s segment selector handling
    
    All selector fields under ctxt->regs are (normally) poisoned in the HVM
    case, and the four ones besides CS and SS are potentially stale for PV.
    Avoid using them in the hypervisor incarnation of the emulator, when
    trying to cover for a missing ->read_segment() hook.
    
    To make sure there's always a valid ->read_segment() handler for all HVM
    cases, add a respective function to shadow code, even if it is not
    expected for FPU insns to be used to update page tables.
    
    Fixes: 0711b59b858a ("x86emul: correct FPU code/data pointers and opcode handling")
    Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
    master commit: 645b8d48c78f5b6ffd6230873f9e3ced4e840acd
    master date: 2025-01-08 11:02:16 +0100
---
 xen/arch/x86/mm/shadow/hvm.c           | 18 ++++++++++++++++++
 xen/arch/x86/x86_emulate/x86_emulate.c | 32 ++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index c16f3b3adf..114957a3e1 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -287,11 +287,29 @@ hvm_emulate_cmpxchg(enum x86_segment seg,
     return rc;
 }
 
+static int cf_check
+hvm_emulate_read_segment(enum x86_segment seg,
+                         struct segment_register *reg,
+                         struct x86_emulate_ctxt *ctxt)
+{
+    struct sh_emulate_ctxt *sh_ctxt =
+        container_of(ctxt, struct sh_emulate_ctxt, ctxt);
+    const struct segment_register *sreg = hvm_get_seg_reg(seg, sh_ctxt);
+
+    if ( IS_ERR(sreg) )
+        return -PTR_ERR(sreg);
+
+    *reg = *sreg;
+
+    return X86EMUL_OKAY;
+}
+
 static const struct x86_emulate_ops hvm_shadow_emulator_ops = {
     .read       = hvm_emulate_read,
     .insn_fetch = hvm_emulate_insn_fetch,
     .write      = hvm_emulate_write,
     .cmpxchg    = hvm_emulate_cmpxchg,
+    .read_segment = hvm_emulate_read_segment,
 };
 
 const struct x86_emulate_ops *shadow_init_emulation(
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index f109c335a7..f2436473b9 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -447,14 +447,37 @@ static void put_fpu(
         if ( state->ea.type == OP_MEM )
         {
             aux.dp = state->ea.mem.off;
-            if ( ops->read_segment &&
-                 ops->read_segment(state->ea.mem.seg, &sreg,
-                                   ctxt) == X86EMUL_OKAY )
+            if ( state->ea.mem.seg == x86_seg_cs )
+                aux.ds = aux.cs;
+            else if ( ops->read_segment &&
+                      ops->read_segment(state->ea.mem.seg, &sreg,
+                                        ctxt) == X86EMUL_OKAY )
                 aux.ds = sreg.sel;
+#ifdef __XEN__
+            /*
+             * While generally the expectation is that input structures are
+             * fully populated, the selector fields under ctxt->regs normally
+             * aren't set, with the exception of CS and SS for PV domains.
+             * Read the real selector registers for PV, and assert that HVM
+             * invocations always set a properly functioning ->read_segment()
+             * hook.
+             */
+            else if ( is_pv_vcpu(current) )
+                switch ( state->ea.mem.seg )
+                {
+                case x86_seg_ds: aux.ds = read_sreg(ds);  break;
+                case x86_seg_es: aux.ds = read_sreg(es);  break;
+                case x86_seg_fs: aux.ds = read_sreg(fs);  break;
+                case x86_seg_gs: aux.ds = read_sreg(gs);  break;
+                case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
+                default:         ASSERT_UNREACHABLE();    break;
+                }
+            else
+                ASSERT_UNREACHABLE();
+#else
             else
                 switch ( state->ea.mem.seg )
                 {
-                case x86_seg_cs: aux.ds = ctxt->regs->cs; break;
                 case x86_seg_ds: aux.ds = ctxt->regs->ds; break;
                 case x86_seg_es: aux.ds = ctxt->regs->es; break;
                 case x86_seg_fs: aux.ds = ctxt->regs->fs; break;
@@ -462,6 +485,7 @@ static void put_fpu(
                 case x86_seg_ss: aux.ds = ctxt->regs->ss; break;
                 default:         ASSERT_UNREACHABLE();    break;
                 }
+#endif
             aux.dval = true;
         }
         ops->put_fpu(ctxt, X86EMUL_FPU_none, &aux);
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] xen/flask: Wire up XEN_DOMCTL_vuart_op
Message-Id: <E1taAzp-007nW5-1T@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:56:33 +0000

commit 4dce231463459a82c3d7365136aa9c4d227dc471
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 21 09:30:49 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:49 2025 +0100

    xen/flask: Wire up XEN_DOMCTL_vuart_op
    
    Addition of FLASK permission for this hypercall was overlooked in the
    original patch. Fix it. The only VUART operation is initialization that
    can occur only during domain creation.
    
    Fixes: 86039f2e8c20 ("xen/arm: vpl011: Add a new domctl API to initialize vpl011")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
    master commit: 29daa72e4019aae92f857cf6e7e0c3ca8fb1483e
    master date: 2025-01-08 13:05:38 +0100
---
 tools/flask/policy/modules/xen.if   | 2 +-
 xen/xsm/flask/hooks.c               | 3 +++
 xen/xsm/flask/policy/access_vectors | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 11c1562aa5..ba9e91d302 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -54,7 +54,7 @@ define(`create_domain_common', `
 	allow $1 $2:domain2 { set_cpu_policy settsc setscheduler setclaim
 			set_vnumainfo get_vnumainfo cacheflush
 			psr_cmt_op psr_alloc soft_reset
-			resource_map get_cpu_policy };
+			resource_map get_cpu_policy vuart_op };
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
 	allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 278ad38c2a..35237a00c4 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -829,6 +829,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_soft_reset:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
 
+    case XEN_DOMCTL_vuart_op:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__VUART_OP);
+
     case XEN_DOMCTL_get_cpu_policy:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__GET_CPU_POLICY);
 
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index a35e3d4c51..7cbdb7ea64 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -251,6 +251,8 @@ class domain2
     resource_map
 # XEN_DOMCTL_get_cpu_policy
     get_cpu_policy
+# XEN_DOMCTL_vuart_op
+    vuart_op
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.18] xen/events: fix race with set_global_virq_handler()
Message-Id: <E1taAzz-007nXK-1i@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 09:56:43 +0000

commit 77d95386a783273ded28e92fc32a603c2ccbaa60
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue Jan 21 09:30:59 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue Jan 21 09:30:59 2025 +0100

    xen/events: fix race with set_global_virq_handler()
    
    There is a possible race scenario between set_global_virq_handler()
    and clear_global_virq_handlers() targeting the same domain, which
    might result in that domain ending as a zombie domain.
    
    In case set_global_virq_handler() is being called for a domain which
    is just dying, it might happen that clear_global_virq_handlers() is
    running first, resulting in set_global_virq_handler() taking a new
    reference for that domain and entering in the global_virq_handlers[]
    array afterwards. The reference will never be dropped, thus the domain
    will never be freed completely.
    
    This can be fixed by checking the is_dying state of the domain inside
    the region guarded by global_virq_handlers_lock. In case the domain is
    dying, handle it as if the domain wouldn't exist, which will be the
    case in near future anyway.
    
    Fixes: 87521589aa6a ("xen: allow global VIRQ handlers to be delegated to other domains")
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    master commit: 4d8acc9c1cf14233dda21dd3a7791b5a84b0f6c3
    master date: 2025-01-09 17:34:01 +0100
---
 xen/common/event_channel.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index e6ec556603..3caf74ae77 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -974,6 +974,7 @@ void send_global_virq(uint32_t virq)
 int set_global_virq_handler(struct domain *d, uint32_t virq)
 {
     struct domain *old;
+    int rc = 0;
 
     if (virq >= NR_VIRQS)
         return -EINVAL;
@@ -987,14 +988,32 @@ int set_global_virq_handler(struct domain *d, uint32_t virq)
         return -EINVAL;
 
     spin_lock(&global_virq_handlers_lock);
-    old = global_virq_handlers[virq];
-    global_virq_handlers[virq] = d;
+
+    /*
+     * Note that this check won't guarantee that a domain just going down can't
+     * be set as the handling domain of a virq, as the is_dying indicator might
+     * change just after testing it.
+     * This isn't going to be a major problem, as clear_global_virq_handlers()
+     * is guaranteed to run afterwards and it will reset the handling domain
+     * for the virq to the hardware domain.
+     */
+    if ( d->is_dying != DOMDYING_alive )
+    {
+        old = d;
+        rc = -EINVAL;
+    }
+    else
+    {
+        old = global_virq_handlers[virq];
+        global_virq_handlers[virq] = d;
+    }
+
     spin_unlock(&global_virq_handlers_lock);
 
     if (old != NULL)
         put_domain(old);
 
-    return 0;
+    return rc;
 }
 
 static void clear_global_virq_handlers(struct domain *d)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] docs: fusa: Fix OFT tags for the design requirements
Message-Id: <E1taFei-009DkH-2Z@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 14:55:04 +0000

commit fcde5e0de826a8a888b48da077149a799998724c
Author:     Ayan Kumar Halder <ayan.kumar.halder@amd.com>
AuthorDate: Tue Jan 14 18:57:07 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Tue Jan 21 15:49:52 2025 +0100

    docs: fusa: Fix OFT tags for the design requirements
    
    The OFT tags for the design requirements are updated.
    
    Fixes: b9f9b396452 ("docs: fusa: Add dom0less domain configuration requirements")
    Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/fusa/reqs/design-reqs/arm64/generic-timer.rst | 16 ++++++------
 docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst     | 30 +++++++++++-----------
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
index 9d2a5a8085..745e755638 100644
--- a/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
+++ b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
@@ -21,7 +21,7 @@ Comments:
 Domains can detect the presence of the Generic Timer device tree node.
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Read system counter frequency
 -----------------------------
@@ -37,7 +37,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access CNTKCTL_EL1 system register from a domain
 ------------------------------------------------
@@ -53,7 +53,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access virtual timer from a domain
 ----------------------------------
@@ -69,7 +69,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access physical timer from a domain
 -----------------------------------
@@ -85,7 +85,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Trigger the virtual timer interrupt from a domain
 -------------------------------------------------
@@ -101,7 +101,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Trigger the physical timer interrupt from a domain
 --------------------------------------------------
@@ -117,7 +117,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Assumption of Use on the Platform
 =================================
@@ -139,7 +139,7 @@ While there is a provision to get this value by reading the "clock-frequency"
 dt property [2], the use of this property is strongly discouraged.
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 [1] Arm Architecture Reference Manual for A-profile architecture, Chapter 11
 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
diff --git a/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst b/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
index 89598fa8a5..9aaf081f16 100644
--- a/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
+++ b/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
@@ -21,7 +21,7 @@ Comments:
 Domains can detect the presence of the SBSA UART device tree node.
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Transmit data in software polling mode
 --------------------------------------
@@ -36,7 +36,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Transmit data in interrupt driven mode
 --------------------------------------
@@ -51,7 +51,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive data in software polling mode
 -------------------------------------
@@ -66,7 +66,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive data in interrupt driven mode
 -------------------------------------
@@ -81,7 +81,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART data register
 -------------------------
@@ -96,7 +96,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART receive status register
 -----------------------------------
@@ -111,7 +111,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART flag register
 -------------------------
@@ -126,7 +126,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART mask set/clear register
 -----------------------------------
@@ -141,7 +141,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART raw interrupt status register
 -----------------------------------------
@@ -156,7 +156,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART masked interrupt status register
 --------------------------------------------
@@ -171,7 +171,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART interrupt clear register
 ------------------------------------
@@ -186,7 +186,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive UART TX interrupt
 -------------------------
@@ -202,7 +202,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive UART RX interrupt reception
 -----------------------------------
@@ -218,7 +218,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 [1] Arm Base System Architecture, chapter B
-[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
\ No newline at end of file
+[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
--
generated by git-patchbot for /home/xen/git/xen.git#staging


From xen-changelog-bounces@lists.xenproject.org Tue Jan 21 20:44:12 2025
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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] docs: fusa: Fix OFT tags for the design requirements
Message-Id: <E1taL6Q-00BO1S-03@xenbits.xenproject.org>
Date: Tue, 21 Jan 2025 20:44:02 +0000

commit fcde5e0de826a8a888b48da077149a799998724c
Author:     Ayan Kumar Halder <ayan.kumar.halder@amd.com>
AuthorDate: Tue Jan 14 18:57:07 2025 +0000
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Tue Jan 21 15:49:52 2025 +0100

    docs: fusa: Fix OFT tags for the design requirements
    
    The OFT tags for the design requirements are updated.
    
    Fixes: b9f9b396452 ("docs: fusa: Add dom0less domain configuration requirements")
    Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 docs/fusa/reqs/design-reqs/arm64/generic-timer.rst | 16 ++++++------
 docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst     | 30 +++++++++++-----------
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
index 9d2a5a8085..745e755638 100644
--- a/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
+++ b/docs/fusa/reqs/design-reqs/arm64/generic-timer.rst
@@ -21,7 +21,7 @@ Comments:
 Domains can detect the presence of the Generic Timer device tree node.
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Read system counter frequency
 -----------------------------
@@ -37,7 +37,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access CNTKCTL_EL1 system register from a domain
 ------------------------------------------------
@@ -53,7 +53,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access virtual timer from a domain
 ----------------------------------
@@ -69,7 +69,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Access physical timer from a domain
 -----------------------------------
@@ -85,7 +85,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Trigger the virtual timer interrupt from a domain
 -------------------------------------------------
@@ -101,7 +101,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Trigger the physical timer interrupt from a domain
 --------------------------------------------------
@@ -117,7 +117,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 Assumption of Use on the Platform
 =================================
@@ -139,7 +139,7 @@ While there is a provision to get this value by reading the "clock-frequency"
 dt property [2], the use of this property is strongly discouraged.
 
 Covers:
- - `XenProd~emulated_timer~1`
+ - `XenProd~arm64_emulated_timer~1`
 
 [1] Arm Architecture Reference Manual for A-profile architecture, Chapter 11
 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
diff --git a/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst b/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
index 89598fa8a5..9aaf081f16 100644
--- a/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
+++ b/docs/fusa/reqs/design-reqs/arm64/sbsa-uart.rst
@@ -21,7 +21,7 @@ Comments:
 Domains can detect the presence of the SBSA UART device tree node.
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Transmit data in software polling mode
 --------------------------------------
@@ -36,7 +36,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Transmit data in interrupt driven mode
 --------------------------------------
@@ -51,7 +51,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive data in software polling mode
 -------------------------------------
@@ -66,7 +66,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive data in interrupt driven mode
 -------------------------------------
@@ -81,7 +81,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART data register
 -------------------------
@@ -96,7 +96,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART receive status register
 -----------------------------------
@@ -111,7 +111,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART flag register
 -------------------------
@@ -126,7 +126,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART mask set/clear register
 -----------------------------------
@@ -141,7 +141,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART raw interrupt status register
 -----------------------------------------
@@ -156,7 +156,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART masked interrupt status register
 --------------------------------------------
@@ -171,7 +171,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Access UART interrupt clear register
 ------------------------------------
@@ -186,7 +186,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive UART TX interrupt
 -------------------------
@@ -202,7 +202,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 Receive UART RX interrupt reception
 -----------------------------------
@@ -218,7 +218,7 @@ Rationale:
 Comments:
 
 Covers:
- - `XenProd~emulated_uart~1`
+ - `XenProd~arm64_emulated_uart~1`
 
 [1] Arm Base System Architecture, chapter B
-[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
\ No newline at end of file
+[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/HVM: correct MMIO emulation cache bounds check
Message-Id: <E1tauLd-006wqy-0S@xenbits.xenproject.org>
Date: Thu, 23 Jan 2025 10:22:05 +0000

commit e5339bb689dfa79a914c6c96e1d82d61e1ae3161
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu Jan 23 11:14:48 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 23 11:14:48 2025 +0100

    x86/HVM: correct MMIO emulation cache bounds check
    
    To avoid overrunning the internal buffer we need to take the offset into
    the buffer into account.
    
    Fixes: d95da91fb497 ("x86/HVM: grow MMIO cache data size to 64 bytes")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/hvm/emulate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index a1935a1748..f3b5800d81 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -935,7 +935,7 @@ static int hvmemul_phys_mmio_access(
     }
 
     /* Accesses must not overflow the cache's buffer. */
-    if ( size > sizeof(cache->buffer) )
+    if ( offset + size > sizeof(cache->buffer) )
     {
         ASSERT_UNREACHABLE();
         return X86EMUL_UNHANDLEABLE;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/HVM: correct MMIO emulation cache bounds check
Message-Id: <E1tav6z-0073dN-1H@xenbits.xenproject.org>
Date: Thu, 23 Jan 2025 11:11:01 +0000

commit e5339bb689dfa79a914c6c96e1d82d61e1ae3161
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu Jan 23 11:14:48 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Jan 23 11:14:48 2025 +0100

    x86/HVM: correct MMIO emulation cache bounds check
    
    To avoid overrunning the internal buffer we need to take the offset into
    the buffer into account.
    
    Fixes: d95da91fb497 ("x86/HVM: grow MMIO cache data size to 64 bytes")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/hvm/emulate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index a1935a1748..f3b5800d81 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -935,7 +935,7 @@ static int hvmemul_phys_mmio_access(
     }
 
     /* Accesses must not overflow the cache's buffer. */
-    if ( size > sizeof(cache->buffer) )
+    if ( offset + size > sizeof(cache->buffer) )
     {
         ASSERT_UNREACHABLE();
         return X86EMUL_UNHANDLEABLE;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/HVM: allocate emulation cache entries dynamically
Message-Id: <E1tbFt7-009E8r-07@xenbits.xenproject.org>
Date: Fri, 24 Jan 2025 09:22:05 +0000

commit 23d60dbb0493b2f9ec1d89be5341eec2ee9dab32
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 24 10:15:29 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 24 10:15:29 2025 +0100

    x86/HVM: allocate emulation cache entries dynamically
    
    Both caches may need higher capacity, and the upper bound will need to
    be determined dynamically based on CPUID policy (for AMX'es TILELOAD /
    TILESTORE at least).
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/hvm/emulate.c             | 51 ++++++++++++++++++++++++++--------
 xen/arch/x86/include/asm/hvm/emulate.h |  7 ++++-
 xen/arch/x86/include/asm/hvm/vcpu.h    | 13 +--------
 3 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index f3b5800d81..427ac811a7 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -26,6 +26,18 @@
 #include <asm/iocap.h>
 #include <asm/vm_event.h>
 
+/*
+ * We may read or write up to m512 or up to a tile row as a number of
+ * device-model transactions.
+ */
+struct hvm_mmio_cache {
+    unsigned long gla;
+    unsigned int size;     /* Amount of buffer[] actually used. */
+    unsigned int space:31; /* Allocated size of buffer[]. */
+    unsigned int dir:1;
+    uint8_t buffer[] __aligned(sizeof(long));
+};
+
 struct hvmemul_cache
 {
     /* The cache is disabled as long as num_ents > max_ents. */
@@ -935,7 +947,7 @@ static int hvmemul_phys_mmio_access(
     }
 
     /* Accesses must not overflow the cache's buffer. */
-    if ( offset + size > sizeof(cache->buffer) )
+    if ( offset + size > cache->space )
     {
         ASSERT_UNREACHABLE();
         return X86EMUL_UNHANDLEABLE;
@@ -1011,7 +1023,7 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
 
     for ( i = 0; i < hvio->mmio_cache_count; i ++ )
     {
-        cache = &hvio->mmio_cache[i];
+        cache = hvio->mmio_cache[i];
 
         if ( gla == cache->gla &&
              dir == cache->dir )
@@ -1027,10 +1039,11 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
 
     ++hvio->mmio_cache_count;
 
-    cache = &hvio->mmio_cache[i];
-    memset(cache, 0, sizeof (*cache));
+    cache = hvio->mmio_cache[i];
+    memset(cache->buffer, 0, cache->space);
 
     cache->gla = gla;
+    cache->size = 0;
     cache->dir = dir;
 
     return cache;
@@ -2980,16 +2993,21 @@ void hvm_dump_emulation_state(const char *loglvl, const char *prefix,
 int hvmemul_cache_init(struct vcpu *v)
 {
     /*
-     * No insn can access more than 16 independent linear addresses (AVX512F
-     * scatters/gathers being the worst). Each such linear range can span a
-     * page boundary, i.e. may require two page walks. Account for each insn
-     * byte individually, for simplicity.
+     * AVX512F scatter/gather insns can access up to 16 independent linear
+     * addresses, up to 8 bytes size. Each such linear range can span a page
+     * boundary, i.e. may require two page walks.
+     */
+    unsigned int nents = 16 * 2 * (CONFIG_PAGING_LEVELS + 1);
+    unsigned int i, max_bytes = 64;
+    struct hvmemul_cache *cache;
+
+    /*
+     * Account for each insn byte individually, both for simplicity and to
+     * leave some slack space.
      */
-    const unsigned int nents = (CONFIG_PAGING_LEVELS + 1) *
-                               (MAX_INST_LEN + 16 * 2);
-    struct hvmemul_cache *cache = xmalloc_flex_struct(struct hvmemul_cache,
-                                                      ents, nents);
+    nents += MAX_INST_LEN * (CONFIG_PAGING_LEVELS + 1);
 
+    cache = xvmalloc_flex_struct(struct hvmemul_cache, ents, nents);
     if ( !cache )
         return -ENOMEM;
 
@@ -2999,6 +3017,15 @@ int hvmemul_cache_init(struct vcpu *v)
 
     v->arch.hvm.hvm_io.cache = cache;
 
+    for ( i = 0; i < ARRAY_SIZE(v->arch.hvm.hvm_io.mmio_cache); ++i )
+    {
+        v->arch.hvm.hvm_io.mmio_cache[i] =
+            xvmalloc_flex_struct(struct hvm_mmio_cache, buffer, max_bytes);
+        if ( !v->arch.hvm.hvm_io.mmio_cache[i] )
+            return -ENOMEM;
+        v->arch.hvm.hvm_io.mmio_cache[i]->space = max_bytes;
+    }
+
     return 0;
 }
 
diff --git a/xen/arch/x86/include/asm/hvm/emulate.h b/xen/arch/x86/include/asm/hvm/emulate.h
index 29d679442e..760ce5e77c 100644
--- a/xen/arch/x86/include/asm/hvm/emulate.h
+++ b/xen/arch/x86/include/asm/hvm/emulate.h
@@ -15,6 +15,7 @@
 #include <xen/err.h>
 #include <xen/mm.h>
 #include <xen/sched.h>
+#include <xen/xvmalloc.h>
 #include <asm/hvm/hvm.h>
 #include <asm/x86_emulate.h>
 
@@ -119,7 +120,11 @@ int hvmemul_do_pio_buffer(uint16_t port,
 int __must_check hvmemul_cache_init(struct vcpu *v);
 static inline void hvmemul_cache_destroy(struct vcpu *v)
 {
-    XFREE(v->arch.hvm.hvm_io.cache);
+    unsigned int i;
+
+    for ( i = 0; i < ARRAY_SIZE(v->arch.hvm.hvm_io.mmio_cache); ++i )
+        XFREE(v->arch.hvm.hvm_io.mmio_cache[i]);
+    XVFREE(v->arch.hvm.hvm_io.cache);
 }
 bool hvmemul_read_cache(const struct vcpu *v, paddr_t gpa,
                         void *buffer, unsigned int size);
diff --git a/xen/arch/x86/include/asm/hvm/vcpu.h b/xen/arch/x86/include/asm/hvm/vcpu.h
index 6d5845780d..196fed6d5d 100644
--- a/xen/arch/x86/include/asm/hvm/vcpu.h
+++ b/xen/arch/x86/include/asm/hvm/vcpu.h
@@ -22,17 +22,6 @@ struct hvm_vcpu_asid {
     uint32_t asid;
 };
 
-/*
- * We may read or write up to m512 as a number of device-model
- * transactions.
- */
-struct hvm_mmio_cache {
-    unsigned long gla;
-    unsigned int size;
-    uint8_t dir;
-    uint8_t buffer[64] __aligned(sizeof(long));
-};
-
 struct hvm_vcpu_io {
     /*
      * HVM emulation:
@@ -48,7 +37,7 @@ struct hvm_vcpu_io {
      * We may need to handle up to 3 distinct memory accesses per
      * instruction.
      */
-    struct hvm_mmio_cache mmio_cache[3];
+    struct hvm_mmio_cache *mmio_cache[3];
     unsigned int mmio_cache_count;
 
     /* For retries we shouldn't re-fetch the instruction. */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/HVM: correct read/write split at page boundaries
Message-Id: <E1tbFtH-009E9F-0Y@xenbits.xenproject.org>
Date: Fri, 24 Jan 2025 09:22:15 +0000

commit 672894a11fe06e664a0ebfb600baf5dbb897b9e4
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 24 10:15:56 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 24 10:15:56 2025 +0100

    x86/HVM: correct read/write split at page boundaries
    
    The MMIO cache is intended to have one entry used per independent memory
    access that an insn does. This, in particular, is supposed to be
    ignoring any page boundary crossing. Therefore when looking up a cache
    entry, the access'es starting (linear) address is relevant, not the one
    possibly advanced past a page boundary.
    
    In order for the same offset-into-buffer variable to be usable in
    hvmemul_phys_mmio_access() for both the caller's buffer and the cache
    entry's it is further necessary to have the un-adjusted caller buffer
    passed into there.
    
    Fixes: 2d527ba310dc ("x86/hvm: split all linear reads and writes at page boundary")
    Reported-by: Manuel Andreas <manuel.andreas@tum.de>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/hvm/emulate.c | 92 ++++++++++++++++++++++++++++++----------------
 1 file changed, 61 insertions(+), 31 deletions(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index 427ac811a7..0d90cc4598 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -31,8 +31,9 @@
  * device-model transactions.
  */
 struct hvm_mmio_cache {
-    unsigned long gla;
-    unsigned int size;     /* Amount of buffer[] actually used. */
+    unsigned long gla;     /* Start of original access (e.g. insn operand). */
+    unsigned int skip;     /* Offset to start of MMIO */
+    unsigned int size;     /* Amount of buffer[] actually used, incl @skip. */
     unsigned int space:31; /* Allocated size of buffer[]. */
     unsigned int dir:1;
     uint8_t buffer[] __aligned(sizeof(long));
@@ -953,6 +954,13 @@ static int hvmemul_phys_mmio_access(
         return X86EMUL_UNHANDLEABLE;
     }
 
+    /* Accesses must not be to the unused leading space. */
+    if ( offset < cache->skip )
+    {
+        ASSERT_UNREACHABLE();
+        return X86EMUL_UNHANDLEABLE;
+    }
+
     /*
      * hvmemul_do_io() cannot handle non-power-of-2 accesses or
      * accesses larger than sizeof(long), so choose the highest power
@@ -1010,13 +1018,15 @@ static int hvmemul_phys_mmio_access(
 
 /*
  * Multi-cycle MMIO handling is based upon the assumption that emulation
- * of the same instruction will not access the same MMIO region more
- * than once. Hence we can deal with re-emulation (for secondary or
- * subsequent cycles) by looking up the result or previous I/O in a
- * cache indexed by linear MMIO address.
+ * of the same instruction will not access the exact same MMIO region
+ * more than once in exactly the same way (if it does, the accesses will
+ * be "folded"). Hence we can deal with re-emulation (for secondary or
+ * subsequent cycles) by looking up the result of previous I/O in a cache
+ * indexed by linear address and access type.
  */
 static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
-    struct hvm_vcpu_io *hvio, unsigned long gla, uint8_t dir, bool create)
+    struct hvm_vcpu_io *hvio, unsigned long gla, uint8_t dir,
+    unsigned int skip)
 {
     unsigned int i;
     struct hvm_mmio_cache *cache;
@@ -1030,7 +1040,11 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
             return cache;
     }
 
-    if ( !create )
+    /*
+     * Bail if a new entry shouldn't be allocated, relying on ->space having
+     * the same value for all entries.
+     */
+    if ( skip >= hvio->mmio_cache[0]->space )
         return NULL;
 
     i = hvio->mmio_cache_count;
@@ -1043,7 +1057,8 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
     memset(cache->buffer, 0, cache->space);
 
     cache->gla = gla;
-    cache->size = 0;
+    cache->skip = skip;
+    cache->size = skip;
     cache->dir = dir;
 
     return cache;
@@ -1064,12 +1079,14 @@ static void latch_linear_to_phys(struct hvm_vcpu_io *hvio, unsigned long gla,
 
 static int hvmemul_linear_mmio_access(
     unsigned long gla, unsigned int size, uint8_t dir, void *buffer,
-    uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt, bool known_gpfn)
+    uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
+    unsigned long start_gla, bool known_gpfn)
 {
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
     unsigned long offset = gla & ~PAGE_MASK;
-    struct hvm_mmio_cache *cache = hvmemul_find_mmio_cache(hvio, gla, dir, true);
-    unsigned int chunk, buffer_offset = 0;
+    unsigned int chunk, buffer_offset = gla - start_gla;
+    struct hvm_mmio_cache *cache = hvmemul_find_mmio_cache(hvio, start_gla,
+                                                           dir, buffer_offset);
     paddr_t gpa;
     unsigned long one_rep = 1;
     int rc;
@@ -1117,19 +1134,19 @@ static int hvmemul_linear_mmio_access(
 static inline int hvmemul_linear_mmio_read(
     unsigned long gla, unsigned int size, void *buffer,
     uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
-    bool translate)
+    unsigned long start_gla, bool translate)
 {
-    return hvmemul_linear_mmio_access(gla, size, IOREQ_READ, buffer,
-                                      pfec, hvmemul_ctxt, translate);
+    return hvmemul_linear_mmio_access(gla, size, IOREQ_READ, buffer, pfec,
+                                      hvmemul_ctxt, start_gla, translate);
 }
 
 static inline int hvmemul_linear_mmio_write(
     unsigned long gla, unsigned int size, void *buffer,
     uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
-    bool translate)
+    unsigned long start_gla, bool translate)
 {
-    return hvmemul_linear_mmio_access(gla, size, IOREQ_WRITE, buffer,
-                                      pfec, hvmemul_ctxt, translate);
+    return hvmemul_linear_mmio_access(gla, size, IOREQ_WRITE, buffer, pfec,
+                                      hvmemul_ctxt, start_gla, translate);
 }
 
 static bool known_gla(unsigned long addr, unsigned int bytes, uint32_t pfec)
@@ -1158,7 +1175,10 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
 {
     pagefault_info_t pfinfo;
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
+    void *buffer = p_data;
+    unsigned long start = addr;
     unsigned int offset = addr & ~PAGE_MASK;
+    const struct hvm_mmio_cache *cache;
     int rc;
 
     if ( offset + bytes > PAGE_SIZE )
@@ -1182,8 +1202,17 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
      * an access that was previously handled as MMIO. Thus it is imperative that
      * we handle this access in the same way to guarantee completion and hence
      * clean up any interim state.
+     *
+     * Care must be taken, however, to correctly deal with crossing RAM/MMIO or
+     * MMIO/RAM boundaries. While we want to use a single cache entry (tagged
+     * by the starting linear address), we need to continue issuing (i.e. also
+     * upon replay) the RAM access for anything that's ahead of or past MMIO,
+     * i.e. in RAM.
      */
-    if ( !hvmemul_find_mmio_cache(hvio, addr, IOREQ_READ, false) )
+    cache = hvmemul_find_mmio_cache(hvio, start, IOREQ_READ, ~0);
+    if ( !cache ||
+         addr + bytes <= start + cache->skip ||
+         addr >= start + cache->size )
         rc = hvm_copy_from_guest_linear(p_data, addr, bytes, pfec, &pfinfo);
 
     switch ( rc )
@@ -1199,8 +1228,8 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
         if ( pfec & PFEC_insn_fetch )
             return X86EMUL_UNHANDLEABLE;
 
-        return hvmemul_linear_mmio_read(addr, bytes, p_data, pfec,
-                                        hvmemul_ctxt,
+        return hvmemul_linear_mmio_read(addr, bytes, buffer, pfec,
+                                        hvmemul_ctxt, start,
                                         known_gla(addr, bytes, pfec));
 
     case HVMTRANS_gfn_paged_out:
@@ -1217,7 +1246,10 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
 {
     pagefault_info_t pfinfo;
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
+    void *buffer = p_data;
+    unsigned long start = addr;
     unsigned int offset = addr & ~PAGE_MASK;
+    const struct hvm_mmio_cache *cache;
     int rc;
 
     if ( offset + bytes > PAGE_SIZE )
@@ -1236,13 +1268,11 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
 
     rc = HVMTRANS_bad_gfn_to_mfn;
 
-    /*
-     * If there is an MMIO cache entry for the access then we must be re-issuing
-     * an access that was previously handled as MMIO. Thus it is imperative that
-     * we handle this access in the same way to guarantee completion and hence
-     * clean up any interim state.
-     */
-    if ( !hvmemul_find_mmio_cache(hvio, addr, IOREQ_WRITE, false) )
+    /* See commentary in linear_read(). */
+    cache = hvmemul_find_mmio_cache(hvio, start, IOREQ_WRITE, ~0);
+    if ( !cache ||
+         addr + bytes <= start + cache->skip ||
+         addr >= start + cache->size )
         rc = hvm_copy_to_guest_linear(addr, p_data, bytes, pfec, &pfinfo);
 
     switch ( rc )
@@ -1255,8 +1285,8 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
         return X86EMUL_EXCEPTION;
 
     case HVMTRANS_bad_gfn_to_mfn:
-        return hvmemul_linear_mmio_write(addr, bytes, p_data, pfec,
-                                         hvmemul_ctxt,
+        return hvmemul_linear_mmio_write(addr, bytes, buffer, pfec,
+                                         hvmemul_ctxt, start,
                                          known_gla(addr, bytes, pfec));
 
     case HVMTRANS_gfn_paged_out:
@@ -1643,7 +1673,7 @@ static int cf_check hvmemul_cmpxchg(
     {
         /* Fix this in case the guest is really relying on r-m-w atomicity. */
         return hvmemul_linear_mmio_write(addr, bytes, p_new, pfec,
-                                         hvmemul_ctxt,
+                                         hvmemul_ctxt, addr,
                                          hvio->mmio_access.write_access &&
                                          hvio->mmio_gla == (addr & PAGE_MASK));
     }
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/HVM: allocate emulation cache entries dynamically
Message-Id: <E1tbIrt-009Suo-35@xenbits.xenproject.org>
Date: Fri, 24 Jan 2025 12:33:01 +0000

commit 23d60dbb0493b2f9ec1d89be5341eec2ee9dab32
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 24 10:15:29 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 24 10:15:29 2025 +0100

    x86/HVM: allocate emulation cache entries dynamically
    
    Both caches may need higher capacity, and the upper bound will need to
    be determined dynamically based on CPUID policy (for AMX'es TILELOAD /
    TILESTORE at least).
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/hvm/emulate.c             | 51 ++++++++++++++++++++++++++--------
 xen/arch/x86/include/asm/hvm/emulate.h |  7 ++++-
 xen/arch/x86/include/asm/hvm/vcpu.h    | 13 +--------
 3 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index f3b5800d81..427ac811a7 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -26,6 +26,18 @@
 #include <asm/iocap.h>
 #include <asm/vm_event.h>
 
+/*
+ * We may read or write up to m512 or up to a tile row as a number of
+ * device-model transactions.
+ */
+struct hvm_mmio_cache {
+    unsigned long gla;
+    unsigned int size;     /* Amount of buffer[] actually used. */
+    unsigned int space:31; /* Allocated size of buffer[]. */
+    unsigned int dir:1;
+    uint8_t buffer[] __aligned(sizeof(long));
+};
+
 struct hvmemul_cache
 {
     /* The cache is disabled as long as num_ents > max_ents. */
@@ -935,7 +947,7 @@ static int hvmemul_phys_mmio_access(
     }
 
     /* Accesses must not overflow the cache's buffer. */
-    if ( offset + size > sizeof(cache->buffer) )
+    if ( offset + size > cache->space )
     {
         ASSERT_UNREACHABLE();
         return X86EMUL_UNHANDLEABLE;
@@ -1011,7 +1023,7 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
 
     for ( i = 0; i < hvio->mmio_cache_count; i ++ )
     {
-        cache = &hvio->mmio_cache[i];
+        cache = hvio->mmio_cache[i];
 
         if ( gla == cache->gla &&
              dir == cache->dir )
@@ -1027,10 +1039,11 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
 
     ++hvio->mmio_cache_count;
 
-    cache = &hvio->mmio_cache[i];
-    memset(cache, 0, sizeof (*cache));
+    cache = hvio->mmio_cache[i];
+    memset(cache->buffer, 0, cache->space);
 
     cache->gla = gla;
+    cache->size = 0;
     cache->dir = dir;
 
     return cache;
@@ -2980,16 +2993,21 @@ void hvm_dump_emulation_state(const char *loglvl, const char *prefix,
 int hvmemul_cache_init(struct vcpu *v)
 {
     /*
-     * No insn can access more than 16 independent linear addresses (AVX512F
-     * scatters/gathers being the worst). Each such linear range can span a
-     * page boundary, i.e. may require two page walks. Account for each insn
-     * byte individually, for simplicity.
+     * AVX512F scatter/gather insns can access up to 16 independent linear
+     * addresses, up to 8 bytes size. Each such linear range can span a page
+     * boundary, i.e. may require two page walks.
+     */
+    unsigned int nents = 16 * 2 * (CONFIG_PAGING_LEVELS + 1);
+    unsigned int i, max_bytes = 64;
+    struct hvmemul_cache *cache;
+
+    /*
+     * Account for each insn byte individually, both for simplicity and to
+     * leave some slack space.
      */
-    const unsigned int nents = (CONFIG_PAGING_LEVELS + 1) *
-                               (MAX_INST_LEN + 16 * 2);
-    struct hvmemul_cache *cache = xmalloc_flex_struct(struct hvmemul_cache,
-                                                      ents, nents);
+    nents += MAX_INST_LEN * (CONFIG_PAGING_LEVELS + 1);
 
+    cache = xvmalloc_flex_struct(struct hvmemul_cache, ents, nents);
     if ( !cache )
         return -ENOMEM;
 
@@ -2999,6 +3017,15 @@ int hvmemul_cache_init(struct vcpu *v)
 
     v->arch.hvm.hvm_io.cache = cache;
 
+    for ( i = 0; i < ARRAY_SIZE(v->arch.hvm.hvm_io.mmio_cache); ++i )
+    {
+        v->arch.hvm.hvm_io.mmio_cache[i] =
+            xvmalloc_flex_struct(struct hvm_mmio_cache, buffer, max_bytes);
+        if ( !v->arch.hvm.hvm_io.mmio_cache[i] )
+            return -ENOMEM;
+        v->arch.hvm.hvm_io.mmio_cache[i]->space = max_bytes;
+    }
+
     return 0;
 }
 
diff --git a/xen/arch/x86/include/asm/hvm/emulate.h b/xen/arch/x86/include/asm/hvm/emulate.h
index 29d679442e..760ce5e77c 100644
--- a/xen/arch/x86/include/asm/hvm/emulate.h
+++ b/xen/arch/x86/include/asm/hvm/emulate.h
@@ -15,6 +15,7 @@
 #include <xen/err.h>
 #include <xen/mm.h>
 #include <xen/sched.h>
+#include <xen/xvmalloc.h>
 #include <asm/hvm/hvm.h>
 #include <asm/x86_emulate.h>
 
@@ -119,7 +120,11 @@ int hvmemul_do_pio_buffer(uint16_t port,
 int __must_check hvmemul_cache_init(struct vcpu *v);
 static inline void hvmemul_cache_destroy(struct vcpu *v)
 {
-    XFREE(v->arch.hvm.hvm_io.cache);
+    unsigned int i;
+
+    for ( i = 0; i < ARRAY_SIZE(v->arch.hvm.hvm_io.mmio_cache); ++i )
+        XFREE(v->arch.hvm.hvm_io.mmio_cache[i]);
+    XVFREE(v->arch.hvm.hvm_io.cache);
 }
 bool hvmemul_read_cache(const struct vcpu *v, paddr_t gpa,
                         void *buffer, unsigned int size);
diff --git a/xen/arch/x86/include/asm/hvm/vcpu.h b/xen/arch/x86/include/asm/hvm/vcpu.h
index 6d5845780d..196fed6d5d 100644
--- a/xen/arch/x86/include/asm/hvm/vcpu.h
+++ b/xen/arch/x86/include/asm/hvm/vcpu.h
@@ -22,17 +22,6 @@ struct hvm_vcpu_asid {
     uint32_t asid;
 };
 
-/*
- * We may read or write up to m512 as a number of device-model
- * transactions.
- */
-struct hvm_mmio_cache {
-    unsigned long gla;
-    unsigned int size;
-    uint8_t dir;
-    uint8_t buffer[64] __aligned(sizeof(long));
-};
-
 struct hvm_vcpu_io {
     /*
      * HVM emulation:
@@ -48,7 +37,7 @@ struct hvm_vcpu_io {
      * We may need to handle up to 3 distinct memory accesses per
      * instruction.
      */
-    struct hvm_mmio_cache mmio_cache[3];
+    struct hvm_mmio_cache *mmio_cache[3];
     unsigned int mmio_cache_count;
 
     /* For retries we shouldn't re-fetch the instruction. */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/HVM: correct read/write split at page boundaries
Message-Id: <E1tbIs4-009T1O-0P@xenbits.xenproject.org>
Date: Fri, 24 Jan 2025 12:33:12 +0000

commit 672894a11fe06e664a0ebfb600baf5dbb897b9e4
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Jan 24 10:15:56 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Jan 24 10:15:56 2025 +0100

    x86/HVM: correct read/write split at page boundaries
    
    The MMIO cache is intended to have one entry used per independent memory
    access that an insn does. This, in particular, is supposed to be
    ignoring any page boundary crossing. Therefore when looking up a cache
    entry, the access'es starting (linear) address is relevant, not the one
    possibly advanced past a page boundary.
    
    In order for the same offset-into-buffer variable to be usable in
    hvmemul_phys_mmio_access() for both the caller's buffer and the cache
    entry's it is further necessary to have the un-adjusted caller buffer
    passed into there.
    
    Fixes: 2d527ba310dc ("x86/hvm: split all linear reads and writes at page boundary")
    Reported-by: Manuel Andreas <manuel.andreas@tum.de>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/hvm/emulate.c | 92 ++++++++++++++++++++++++++++++----------------
 1 file changed, 61 insertions(+), 31 deletions(-)

diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index 427ac811a7..0d90cc4598 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -31,8 +31,9 @@
  * device-model transactions.
  */
 struct hvm_mmio_cache {
-    unsigned long gla;
-    unsigned int size;     /* Amount of buffer[] actually used. */
+    unsigned long gla;     /* Start of original access (e.g. insn operand). */
+    unsigned int skip;     /* Offset to start of MMIO */
+    unsigned int size;     /* Amount of buffer[] actually used, incl @skip. */
     unsigned int space:31; /* Allocated size of buffer[]. */
     unsigned int dir:1;
     uint8_t buffer[] __aligned(sizeof(long));
@@ -953,6 +954,13 @@ static int hvmemul_phys_mmio_access(
         return X86EMUL_UNHANDLEABLE;
     }
 
+    /* Accesses must not be to the unused leading space. */
+    if ( offset < cache->skip )
+    {
+        ASSERT_UNREACHABLE();
+        return X86EMUL_UNHANDLEABLE;
+    }
+
     /*
      * hvmemul_do_io() cannot handle non-power-of-2 accesses or
      * accesses larger than sizeof(long), so choose the highest power
@@ -1010,13 +1018,15 @@ static int hvmemul_phys_mmio_access(
 
 /*
  * Multi-cycle MMIO handling is based upon the assumption that emulation
- * of the same instruction will not access the same MMIO region more
- * than once. Hence we can deal with re-emulation (for secondary or
- * subsequent cycles) by looking up the result or previous I/O in a
- * cache indexed by linear MMIO address.
+ * of the same instruction will not access the exact same MMIO region
+ * more than once in exactly the same way (if it does, the accesses will
+ * be "folded"). Hence we can deal with re-emulation (for secondary or
+ * subsequent cycles) by looking up the result of previous I/O in a cache
+ * indexed by linear address and access type.
  */
 static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
-    struct hvm_vcpu_io *hvio, unsigned long gla, uint8_t dir, bool create)
+    struct hvm_vcpu_io *hvio, unsigned long gla, uint8_t dir,
+    unsigned int skip)
 {
     unsigned int i;
     struct hvm_mmio_cache *cache;
@@ -1030,7 +1040,11 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
             return cache;
     }
 
-    if ( !create )
+    /*
+     * Bail if a new entry shouldn't be allocated, relying on ->space having
+     * the same value for all entries.
+     */
+    if ( skip >= hvio->mmio_cache[0]->space )
         return NULL;
 
     i = hvio->mmio_cache_count;
@@ -1043,7 +1057,8 @@ static struct hvm_mmio_cache *hvmemul_find_mmio_cache(
     memset(cache->buffer, 0, cache->space);
 
     cache->gla = gla;
-    cache->size = 0;
+    cache->skip = skip;
+    cache->size = skip;
     cache->dir = dir;
 
     return cache;
@@ -1064,12 +1079,14 @@ static void latch_linear_to_phys(struct hvm_vcpu_io *hvio, unsigned long gla,
 
 static int hvmemul_linear_mmio_access(
     unsigned long gla, unsigned int size, uint8_t dir, void *buffer,
-    uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt, bool known_gpfn)
+    uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
+    unsigned long start_gla, bool known_gpfn)
 {
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
     unsigned long offset = gla & ~PAGE_MASK;
-    struct hvm_mmio_cache *cache = hvmemul_find_mmio_cache(hvio, gla, dir, true);
-    unsigned int chunk, buffer_offset = 0;
+    unsigned int chunk, buffer_offset = gla - start_gla;
+    struct hvm_mmio_cache *cache = hvmemul_find_mmio_cache(hvio, start_gla,
+                                                           dir, buffer_offset);
     paddr_t gpa;
     unsigned long one_rep = 1;
     int rc;
@@ -1117,19 +1134,19 @@ static int hvmemul_linear_mmio_access(
 static inline int hvmemul_linear_mmio_read(
     unsigned long gla, unsigned int size, void *buffer,
     uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
-    bool translate)
+    unsigned long start_gla, bool translate)
 {
-    return hvmemul_linear_mmio_access(gla, size, IOREQ_READ, buffer,
-                                      pfec, hvmemul_ctxt, translate);
+    return hvmemul_linear_mmio_access(gla, size, IOREQ_READ, buffer, pfec,
+                                      hvmemul_ctxt, start_gla, translate);
 }
 
 static inline int hvmemul_linear_mmio_write(
     unsigned long gla, unsigned int size, void *buffer,
     uint32_t pfec, struct hvm_emulate_ctxt *hvmemul_ctxt,
-    bool translate)
+    unsigned long start_gla, bool translate)
 {
-    return hvmemul_linear_mmio_access(gla, size, IOREQ_WRITE, buffer,
-                                      pfec, hvmemul_ctxt, translate);
+    return hvmemul_linear_mmio_access(gla, size, IOREQ_WRITE, buffer, pfec,
+                                      hvmemul_ctxt, start_gla, translate);
 }
 
 static bool known_gla(unsigned long addr, unsigned int bytes, uint32_t pfec)
@@ -1158,7 +1175,10 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
 {
     pagefault_info_t pfinfo;
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
+    void *buffer = p_data;
+    unsigned long start = addr;
     unsigned int offset = addr & ~PAGE_MASK;
+    const struct hvm_mmio_cache *cache;
     int rc;
 
     if ( offset + bytes > PAGE_SIZE )
@@ -1182,8 +1202,17 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
      * an access that was previously handled as MMIO. Thus it is imperative that
      * we handle this access in the same way to guarantee completion and hence
      * clean up any interim state.
+     *
+     * Care must be taken, however, to correctly deal with crossing RAM/MMIO or
+     * MMIO/RAM boundaries. While we want to use a single cache entry (tagged
+     * by the starting linear address), we need to continue issuing (i.e. also
+     * upon replay) the RAM access for anything that's ahead of or past MMIO,
+     * i.e. in RAM.
      */
-    if ( !hvmemul_find_mmio_cache(hvio, addr, IOREQ_READ, false) )
+    cache = hvmemul_find_mmio_cache(hvio, start, IOREQ_READ, ~0);
+    if ( !cache ||
+         addr + bytes <= start + cache->skip ||
+         addr >= start + cache->size )
         rc = hvm_copy_from_guest_linear(p_data, addr, bytes, pfec, &pfinfo);
 
     switch ( rc )
@@ -1199,8 +1228,8 @@ static int linear_read(unsigned long addr, unsigned int bytes, void *p_data,
         if ( pfec & PFEC_insn_fetch )
             return X86EMUL_UNHANDLEABLE;
 
-        return hvmemul_linear_mmio_read(addr, bytes, p_data, pfec,
-                                        hvmemul_ctxt,
+        return hvmemul_linear_mmio_read(addr, bytes, buffer, pfec,
+                                        hvmemul_ctxt, start,
                                         known_gla(addr, bytes, pfec));
 
     case HVMTRANS_gfn_paged_out:
@@ -1217,7 +1246,10 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
 {
     pagefault_info_t pfinfo;
     struct hvm_vcpu_io *hvio = &current->arch.hvm.hvm_io;
+    void *buffer = p_data;
+    unsigned long start = addr;
     unsigned int offset = addr & ~PAGE_MASK;
+    const struct hvm_mmio_cache *cache;
     int rc;
 
     if ( offset + bytes > PAGE_SIZE )
@@ -1236,13 +1268,11 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
 
     rc = HVMTRANS_bad_gfn_to_mfn;
 
-    /*
-     * If there is an MMIO cache entry for the access then we must be re-issuing
-     * an access that was previously handled as MMIO. Thus it is imperative that
-     * we handle this access in the same way to guarantee completion and hence
-     * clean up any interim state.
-     */
-    if ( !hvmemul_find_mmio_cache(hvio, addr, IOREQ_WRITE, false) )
+    /* See commentary in linear_read(). */
+    cache = hvmemul_find_mmio_cache(hvio, start, IOREQ_WRITE, ~0);
+    if ( !cache ||
+         addr + bytes <= start + cache->skip ||
+         addr >= start + cache->size )
         rc = hvm_copy_to_guest_linear(addr, p_data, bytes, pfec, &pfinfo);
 
     switch ( rc )
@@ -1255,8 +1285,8 @@ static int linear_write(unsigned long addr, unsigned int bytes, void *p_data,
         return X86EMUL_EXCEPTION;
 
     case HVMTRANS_bad_gfn_to_mfn:
-        return hvmemul_linear_mmio_write(addr, bytes, p_data, pfec,
-                                         hvmemul_ctxt,
+        return hvmemul_linear_mmio_write(addr, bytes, buffer, pfec,
+                                         hvmemul_ctxt, start,
                                          known_gla(addr, bytes, pfec));
 
     case HVMTRANS_gfn_paged_out:
@@ -1643,7 +1673,7 @@ static int cf_check hvmemul_cmpxchg(
     {
         /* Fix this in case the guest is really relying on r-m-w atomicity. */
         return hvmemul_linear_mmio_write(addr, bytes, p_new, pfec,
-                                         hvmemul_ctxt,
+                                         hvmemul_ctxt, addr,
                                          hvio->mmio_access.write_access &&
                                          hvio->mmio_gla == (addr & PAGE_MASK));
     }
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/iommu: check for CMPXCHG16B when enabling IOMMU
Message-Id: <E1tcOIb-005n6n-0Z@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 12:33:05 +0000

commit 2636fcdc15c707d5e097770133f0afb69e8d70c9
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Fri Jan 24 12:31:15 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    x86/iommu: check for CMPXCHG16B when enabling IOMMU
    
    All hardware with VT-d/AMD-Vi has CMPXCHG16B support. Check this at
    initialisation time, and otherwise refuse to use the IOMMU.
    
    If the local APICs support x2APIC mode the IOMMU support for interrupt
    remapping will be checked earlier using a specific helper.  If no support
    for CX16 is detected by that earlier hook disable the IOMMU at that point
    and prevent further poking for CX16 later in the boot process, which would
    also fail.
    
    There's a possible corner case when running virtualized, and the underlying
    hypervisor exposing an IOMMU but no CMPXCHG16B support.  In which case
    ignoring the IOMMU is fine, albeit the most natural would be for the
    underlying hypervisor to also expose CMPXCHG16B support if an IOMMU is
    available to the VM.
    
    Note this change only introduces the checks, but doesn't remove the now
    stale checks for CX16 support sprinkled in the IOMMU code.  Further changes
    will take care of that.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_intr.c    | 13 +++++++++++++
 xen/drivers/passthrough/amd/pci_amd_iommu.c |  6 ++++++
 xen/drivers/passthrough/vtd/intremap.c      | 13 +++++++++++++
 xen/drivers/passthrough/vtd/iommu.c         |  7 +++++++
 4 files changed, 39 insertions(+)

diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c
index 7fc796dec2..f07fd9e3d9 100644
--- a/xen/drivers/passthrough/amd/iommu_intr.c
+++ b/xen/drivers/passthrough/amd/iommu_intr.c
@@ -649,6 +649,19 @@ bool __init cf_check iov_supports_xt(void)
     if ( !iommu_enable || !iommu_intremap )
         return false;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        AMD_IOMMU_ERROR("no CMPXCHG16B support, disabling IOMMU\n");
+        /*
+         * Disable IOMMU support at once: there's no reason to check for CX16
+         * yet again when attempting to initialize IOMMU DMA remapping
+         * functionality or interrupt remapping without x2APIC support.
+         */
+        iommu_enable = false;
+        iommu_intremap = iommu_intremap_off;
+        return false;
+    }
+
     if ( amd_iommu_prepare(true) )
         return false;
 
diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c
index 73dcc4a2dd..f96f59440b 100644
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c
@@ -309,6 +309,12 @@ static int __init cf_check iov_detect(void)
     if ( !iommu_enable && !iommu_intremap )
         return 0;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        AMD_IOMMU_ERROR("no CMPXCHG16B support, disabling IOMMU\n");
+        return -ENODEV;
+    }
+
     if ( (init_done ? amd_iommu_init_late()
                     : amd_iommu_init(false)) != 0 )
     {
diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c
index c504852eb8..233db5cb64 100644
--- a/xen/drivers/passthrough/vtd/intremap.c
+++ b/xen/drivers/passthrough/vtd/intremap.c
@@ -150,6 +150,19 @@ bool __init cf_check intel_iommu_supports_eim(void)
     if ( !iommu_qinval || !iommu_intremap || list_empty(&acpi_drhd_units) )
         return false;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        printk(XENLOG_ERR VTDPREFIX "no CMPXCHG16B support, disabling IOMMU\n");
+        /*
+         * Disable IOMMU support at once: there's no reason to check for CX16
+         * yet again when attempting to initialize IOMMU DMA remapping
+         * functionality or interrupt remapping without x2APIC support.
+         */
+        iommu_enable = false;
+        iommu_intremap = iommu_intremap_off;
+        return false;
+    }
+
     /* We MUST have a DRHD unit for each IOAPIC. */
     for ( apic = 0; apic < nr_ioapics; apic++ )
         if ( !ioapic_to_drhd(IO_APIC_ID(apic)) )
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index 27a4d16401..3daedc4f55 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -2633,6 +2633,13 @@ static int __init cf_check vtd_setup(void)
     int ret;
     bool reg_inval_supported = true;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        printk(XENLOG_ERR VTDPREFIX "no CMPXCHG16B support, disabling IOMMU\n");
+        ret = -ENODEV;
+        goto error;
+    }
+
     if ( list_empty(&acpi_drhd_units) )
     {
         ret = -ENODEV;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] iommu/vtd: remove non-CX16 logic from interrupt remapping
Message-Id: <E1tcOIl-005nAA-10@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 12:33:15 +0000

commit 848b6bc8c9f37edaf6992c4716a06816ccb0b19e
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:21 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/vtd: remove non-CX16 logic from interrupt remapping
    
    As CX16 support is now mandatory for IOMMU usage, the checks for CX16 in
    the interrupt remapping code are stale.  Remove them together with the
    associated code introduced in case CX16 was not available.
    
    Note that AMD-Vi support for atomically updating a 128bit IRTE entry is
    still not implemented, it will be done by further changes.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/vtd/intremap.c | 75 +++++++---------------------------
 1 file changed, 14 insertions(+), 61 deletions(-)

diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c
index 233db5cb64..820616a8de 100644
--- a/xen/drivers/passthrough/vtd/intremap.c
+++ b/xen/drivers/passthrough/vtd/intremap.c
@@ -184,49 +184,26 @@ bool __init cf_check intel_iommu_supports_eim(void)
 
 /*
  * Assume iremap_lock has been acquired. It is to make sure software will not
- * change the same IRTE behind us. With this assumption, if only high qword or
- * low qword in IRTE is to be updated, this function's atomic variant can
- * present an atomic update to VT-d hardware even when cmpxchg16b
- * instruction is not supported.
+ * change the same IRTE behind us.
  */
 static void update_irte(struct vtd_iommu *iommu, struct iremap_entry *entry,
                         const struct iremap_entry *new_ire, bool atomic)
 {
-    ASSERT(spin_is_locked(&iommu->intremap.lock));
+    __uint128_t ret;
+    struct iremap_entry old_ire;
 
-    if ( cpu_has_cx16 )
-    {
-        __uint128_t ret;
-        struct iremap_entry old_ire;
+    ASSERT(spin_is_locked(&iommu->intremap.lock));
 
-        old_ire = *entry;
-        ret = cmpxchg16b(entry, &old_ire, new_ire);
+    old_ire = *entry;
+    ret = cmpxchg16b(entry, &old_ire, new_ire);
 
-        /*
-         * In the above, we use cmpxchg16 to atomically update the 128-bit
-         * IRTE, and the hardware cannot update the IRTE behind us, so
-         * the return value of cmpxchg16 should be the same as old_ire.
-         * This ASSERT validate it.
-         */
-        ASSERT(ret == old_ire.val);
-    }
-    else
-    {
-        /*
-         * VT-d hardware doesn't update IRTEs behind us, nor the software
-         * since we hold iremap_lock. If the caller wants VT-d hardware to
-         * always see a consistent entry, but we can't meet it, a bug will
-         * be raised.
-         */
-        if ( entry->lo == new_ire->lo )
-            write_atomic(&entry->hi, new_ire->hi);
-        else if ( entry->hi == new_ire->hi )
-            write_atomic(&entry->lo, new_ire->lo);
-        else if ( !atomic )
-            *entry = *new_ire;
-        else
-            BUG();
-    }
+    /*
+     * In the above, we use cmpxchg16 to atomically update the 128-bit
+     * IRTE, and the hardware cannot update the IRTE behind us, so
+     * the return value of cmpxchg16 should be the same as old_ire.
+     * This ASSERT validate it.
+     */
+    ASSERT(ret == old_ire.val);
 }
 
 /* Mark specified intr remap entry as free */
@@ -408,7 +385,6 @@ static int ioapic_rte_to_remap_entry(struct vtd_iommu *iommu,
     /* Indicate remap format. */
     remap_rte->format = 1;
 
-    /* If cmpxchg16b is not available the caller must mask the IO-APIC pin. */
     update_irte(iommu, iremap_entry, &new_ire, !init && !masked);
     iommu_sync_cache(iremap_entry, sizeof(*iremap_entry));
     iommu_flush_iec_index(iommu, 0, index);
@@ -447,38 +423,15 @@ void cf_check io_apic_write_remap_rte(
 {
     struct IO_xAPIC_route_entry old_rte = {}, new_rte;
     struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic));
-    bool masked = true;
     int rc;
 
-    if ( !cpu_has_cx16 )
-    {
-       /*
-        * Cannot atomically update the IRTE entry: mask the IO-APIC pin to
-        * avoid interrupts seeing an inconsistent IRTE entry.
-        */
-        old_rte = __ioapic_read_entry(apic, pin, true);
-        if ( !old_rte.mask )
-        {
-            masked = false;
-            old_rte.mask = 1;
-            __ioapic_write_entry(apic, pin, true, old_rte);
-        }
-    }
-
     /* Not the initializer, for old gcc to cope. */
     new_rte.raw = rte;
 
     rc = ioapic_rte_to_remap_entry(iommu, apic, pin, &old_rte, new_rte);
     if ( rc )
-    {
-        if ( !masked )
-        {
-            /* Recover the original value of 'mask' bit */
-            old_rte.mask = 0;
-            __ioapic_write_entry(apic, pin, true, old_rte);
-        }
         return;
-    }
+
     /* old_rte will contain the updated IO-APIC RTE on success. */
     __ioapic_write_entry(apic, pin, true, old_rte);
 }
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/iommu: remove non-CX16 logic from DMA remapping
Message-Id: <E1tcOIv-005nH1-1P@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 12:33:25 +0000

commit 3fc44151d83d3d63320036bcf06634dfbebe1ff3
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:20 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    x86/iommu: remove non-CX16 logic from DMA remapping
    
    As CX16 support is now mandatory for IOMMU usage, the checks for CX16 in
    the DMA remapping code are stale.  Remove them together with the associated
    code introduced in case CX16 was not available.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_map.c | 42 +++++++------------
 xen/drivers/passthrough/vtd/iommu.c     | 71 ++++++++-------------------------
 2 files changed, 31 insertions(+), 82 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthrough/amd/iommu_map.c
index 1f0e416756..dde393645a 100644
--- a/xen/drivers/passthrough/amd/iommu_map.c
+++ b/xen/drivers/passthrough/amd/iommu_map.c
@@ -167,15 +167,14 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte,
 {
     bool valid = flags & SET_ROOT_VALID;
 
-    if ( dte->v && dte->tv &&
-         (cpu_has_cx16 || (flags & SET_ROOT_WITH_UNITY_MAP)) )
+    if ( dte->v && dte->tv )
     {
         union {
             struct amd_iommu_dte dte;
             uint64_t raw64[4];
             __uint128_t raw128[2];
         } ldte = { .dte = *dte };
-        __uint128_t old = ldte.raw128[0];
+        __uint128_t res, old = ldte.raw128[0];
         int ret = 0;
 
         ldte.dte.domain_id = domain_id;
@@ -185,33 +184,20 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte,
         ldte.dte.paging_mode = paging_mode;
         ldte.dte.v = valid;
 
-        if ( cpu_has_cx16 )
-        {
-            __uint128_t res = cmpxchg16b(dte, &old, &ldte.raw128[0]);
+        res = cmpxchg16b(dte, &old, &ldte.raw128[0]);
 
-            /*
-             * Hardware does not update the DTE behind our backs, so the
-             * return value should match "old".
-             */
-            if ( res != old )
-            {
-                printk(XENLOG_ERR
-                       "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n",
-                       domain_id,
-                       (uint64_t)(res >> 64), (uint64_t)res,
-                       (uint64_t)(old >> 64), (uint64_t)old);
-                ret = -EILSEQ;
-            }
-        }
-        else /* Best effort, updating domain_id last. */
+        /*
+         * Hardware does not update the DTE behind our backs, so the
+         * return value should match "old".
+         */
+        if ( res != old )
         {
-            uint64_t *ptr = (void *)dte;
-
-            write_atomic(ptr + 0, ldte.raw64[0]);
-            /* No barrier should be needed between these two. */
-            write_atomic(ptr + 1, ldte.raw64[1]);
-
-            ret = 1;
+            printk(XENLOG_ERR
+                   "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n",
+                   domain_id,
+                   (uint64_t)(res >> 64), (uint64_t)res,
+                   (uint64_t)(old >> 64), (uint64_t)old);
+            ret = -EILSEQ;
         }
 
         return ret;
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index 3daedc4f55..b0963bfcf7 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1485,7 +1485,7 @@ int domain_context_mapping_one(
 {
     struct domain_iommu *hd = dom_iommu(domain);
     struct context_entry *context, *context_entries, lctxt;
-    __uint128_t old;
+    __uint128_t res, old;
     uint64_t maddr;
     uint16_t seg = iommu->drhd->segment, prev_did = 0;
     struct domain *prev_dom = NULL;
@@ -1583,55 +1583,23 @@ int domain_context_mapping_one(
         ASSERT(!context_fault_disable(lctxt));
     }
 
-    if ( cpu_has_cx16 )
-    {
-        __uint128_t res = cmpxchg16b(context, &old, &lctxt.full);
-
-        /*
-         * Hardware does not update the context entry behind our backs,
-         * so the return value should match "old".
-         */
-        if ( res != old )
-        {
-            if ( pdev )
-                check_cleanup_domid_map(domain, pdev, iommu);
-            printk(XENLOG_ERR
-                   "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n",
-                   &PCI_SBDF(seg, bus, devfn),
-                   (uint64_t)(res >> 64), (uint64_t)res,
-                   (uint64_t)(old >> 64), (uint64_t)old);
-            rc = -EILSEQ;
-            goto unlock;
-        }
-    }
-    else if ( !prev_dom || !(mode & MAP_WITH_RMRR) )
-    {
-        context_clear_present(*context);
-        iommu_sync_cache(context, sizeof(*context));
+    res = cmpxchg16b(context, &old, &lctxt.full);
 
-        write_atomic(&context->hi, lctxt.hi);
-        /* No barrier should be needed between these two. */
-        write_atomic(&context->lo, lctxt.lo);
-    }
-    else /* Best effort, updating DID last. */
+    /*
+     * Hardware does not update the context entry behind our backs,
+     * so the return value should match "old".
+     */
+    if ( res != old )
     {
-         /*
-          * By non-atomically updating the context entry's DID field last,
-          * during a short window in time TLB entries with the old domain ID
-          * but the new page tables may be inserted.  This could affect I/O
-          * of other devices using this same (old) domain ID.  Such updating
-          * therefore is not a problem if this was the only device associated
-          * with the old domain ID.  Diverting I/O of any of a dying domain's
-          * devices to the quarantine page tables is intended anyway.
-          */
-        if ( !(mode & (MAP_OWNER_DYING | MAP_SINGLE_DEVICE)) )
-            printk(XENLOG_WARNING VTDPREFIX
-                   " %pp: reassignment may cause %pd data corruption\n",
-                   &PCI_SBDF(seg, bus, devfn), prev_dom);
-
-        write_atomic(&context->lo, lctxt.lo);
-        /* No barrier should be needed between these two. */
-        write_atomic(&context->hi, lctxt.hi);
+        if ( pdev )
+            check_cleanup_domid_map(domain, pdev, iommu);
+        printk(XENLOG_ERR
+                "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n",
+                &PCI_SBDF(seg, bus, devfn),
+                (uint64_t)(res >> 64), (uint64_t)res,
+                (uint64_t)(old >> 64), (uint64_t)old);
+        rc = -EILSEQ;
+        goto unlock;
     }
 
     iommu_sync_cache(context, sizeof(struct context_entry));
@@ -2702,12 +2670,7 @@ static int __init cf_check vtd_setup(void)
             iommu_intremap = iommu_intremap_off;
 
 #ifndef iommu_intpost
-        /*
-         * We cannot use posted interrupt if X86_FEATURE_CX16 is
-         * not supported, since we count on this feature to
-         * atomically update 16-byte IRTE in posted format.
-         */
-        if ( !cap_intr_post(iommu->cap) || !iommu_intremap || !cpu_has_cx16 )
+        if ( !cap_intr_post(iommu->cap) || !iommu_intremap )
             iommu_intpost = false;
 #endif
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] iommu/vtd: cleanup MAP_SINGLE_DEVICE and related code
Message-Id: <E1tcOJ5-005nQ4-1m@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 12:33:35 +0000

commit a2bbb140be9d176226495cb991af59721c34b3f1
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:21 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/vtd: cleanup MAP_SINGLE_DEVICE and related code
    
    This flag was only used in case cx16 is not available, as those code paths no
    longer exist, this flag now does basically nothing.
    
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/vtd/iommu.c | 12 +++---------
 xen/drivers/passthrough/vtd/vtd.h   |  5 ++---
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index b0963bfcf7..9d7a9977a6 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1695,15 +1695,9 @@ static int domain_context_mapping(struct domain *domain, u8 devfn,
         break;
     }
 
-    if ( domain != pdev->domain && pdev->domain != dom_io )
-    {
-        if ( pdev->domain->is_dying )
-            mode |= MAP_OWNER_DYING;
-        else if ( drhd &&
-                  !any_pdev_behind_iommu(pdev->domain, pdev, drhd->iommu) &&
-                  !pdev->phantom_stride )
-            mode |= MAP_SINGLE_DEVICE;
-    }
+    if ( domain != pdev->domain && pdev->domain != dom_io &&
+         pdev->domain->is_dying )
+        mode |= MAP_OWNER_DYING;
 
     switch ( pdev->type )
     {
diff --git a/xen/drivers/passthrough/vtd/vtd.h b/xen/drivers/passthrough/vtd/vtd.h
index 8aeff8c1f2..b95124517b 100644
--- a/xen/drivers/passthrough/vtd/vtd.h
+++ b/xen/drivers/passthrough/vtd/vtd.h
@@ -28,9 +28,8 @@
  */
 #define MAP_WITH_RMRR         (1u << 0)
 #define MAP_OWNER_DYING       (1u << 1)
-#define MAP_SINGLE_DEVICE     (1u << 2)
-#define MAP_ERROR_RECOVERY    (1u << 3)
-#define UNMAP_ME_PHANTOM_FUNC (1u << 4)
+#define MAP_ERROR_RECOVERY    (1u << 2)
+#define UNMAP_ME_PHANTOM_FUNC (1u << 3)
 
 /* Allow for both IOAPIC and IOSAPIC. */
 #define IO_xAPIC_route_entry IO_APIC_route_entry
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] iommu/amd: atomically update IRTE
Message-Id: <E1tcOJF-005nT4-26@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 12:33:45 +0000

commit b953a99da98d63a7c827248abc450d4e8e015ab6
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Jan 20 15:48:21 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/amd: atomically update IRTE
    
    Either when using a 32bit Interrupt Remapping Entry or a 128bit one update
    the entry atomically, by using cmpxchg unconditionally as IOMMU depends on
    it.  No longer disable the entry by setting RemapEn = 0 ahead of updating
    it.  As a consequence of not toggling RemapEn ahead of the update the
    Interrupt Remapping Table needs to be flushed after the entry update.
    
    This avoids a window where the IRTE has RemapEn = 0, which can lead to
    IO_PAGE_FAULT if the underlying interrupt source is not masked.
    
    There's no guidance in AMD-Vi specification about how IRTE update should be
    performed as opposed to DTE updating which has specific guidance.  However
    DTE updating claims that reads will always be at least 128bits in size, and
    hence for the purposes here assume that reads and caching of the IRTE
    entries in either 32 or 128 bit format will be done atomically from
    the IOMMU.
    
    Note that as part of introducing a new raw128 field in the IRTE struct, the
    current raw field is renamed to raw64 to explicitly contain the size in the
    field name.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_intr.c | 75 ++++++++++++++------------------
 1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c
index f07fd9e3d9..c0273059cb 100644
--- a/xen/drivers/passthrough/amd/iommu_intr.c
+++ b/xen/drivers/passthrough/amd/iommu_intr.c
@@ -39,7 +39,8 @@ union irte32 {
 };
 
 union irte128 {
-    uint64_t raw[2];
+    uint64_t raw64[2];
+    __uint128_t raw128;
     struct {
         bool remap_en:1;
         bool sup_io_pf:1;
@@ -187,7 +188,7 @@ static void free_intremap_entry(const struct amd_iommu *iommu,
 
     if ( iommu->ctrl.ga_en )
     {
-        ACCESS_ONCE(entry.ptr128->raw[0]) = 0;
+        ACCESS_ONCE(entry.ptr128->raw64[0]) = 0;
         /*
          * Low half (containing RemapEn) needs to be cleared first.  Note that
          * strictly speaking smp_wmb() isn't enough, as conceptually it expands
@@ -197,7 +198,7 @@ static void free_intremap_entry(const struct amd_iommu *iommu,
          * variant will do.
          */
         smp_wmb();
-        entry.ptr128->raw[1] = 0;
+        entry.ptr128->raw64[1] = 0;
     }
     else
         ACCESS_ONCE(entry.ptr32->raw) = 0;
@@ -212,7 +213,7 @@ static void update_intremap_entry(const struct amd_iommu *iommu,
 {
     if ( iommu->ctrl.ga_en )
     {
-        union irte128 irte = {
+        const union irte128 irte = {
             .full = {
                 .remap_en = true,
                 .int_type = int_type,
@@ -222,19 +223,26 @@ static void update_intremap_entry(const struct amd_iommu *iommu,
                 .vector = vector,
             },
         };
+        __uint128_t old = entry.ptr128->raw128;
+        __uint128_t res = cmpxchg16b(&entry.ptr128->raw128, &old,
+                                     &irte.raw128);
 
-        ASSERT(!entry.ptr128->full.remap_en);
-        entry.ptr128->raw[1] = irte.raw[1];
         /*
-         * High half needs to be set before low one (containing RemapEn).  See
-         * comment in free_intremap_entry() regarding the choice of barrier.
+         * Hardware does not update the IRTE behind our backs, so the return
+         * value should match "old".
          */
-        smp_wmb();
-        ACCESS_ONCE(entry.ptr128->raw[0]) = irte.raw[0];
+        if ( res != old )
+        {
+            printk(XENLOG_ERR
+                   "unexpected IRTE %016lx_%016lx (expected %016lx_%016lx)\n",
+                   (uint64_t)(res >> 64), (uint64_t)res,
+                   (uint64_t)(old >> 64), (uint64_t)old);
+            ASSERT_UNREACHABLE();
+        }
     }
     else
     {
-        union irte32 irte = {
+        const union irte32 irte = {
             .flds = {
                 .remap_en = true,
                 .int_type = int_type,
@@ -299,21 +307,13 @@ static int update_intremap_entry_from_ioapic(
 
     entry = get_intremap_entry(iommu, req_id, offset);
 
-    /* The RemapEn fields match for all formats. */
-    while ( iommu->enabled && entry.ptr32->flds.remap_en )
-    {
-        entry.ptr32->flds.remap_en = false;
-        spin_unlock(lock);
-
-        amd_iommu_flush_intremap(iommu, req_id);
-
-        spin_lock(lock);
-    }
-
     update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
 
     spin_unlock_irqrestore(lock, flags);
 
+    if ( !fresh )
+        amd_iommu_flush_intremap(iommu, req_id);
+
     set_rte_index(rte, offset);
 
     return 0;
@@ -322,7 +322,7 @@ static int update_intremap_entry_from_ioapic(
 void cf_check amd_iommu_ioapic_update_ire(
     unsigned int apic, unsigned int pin, uint64_t rte)
 {
-    struct IO_APIC_route_entry old_rte, new_rte;
+    struct IO_APIC_route_entry new_rte;
     int seg, bdf, rc;
     struct amd_iommu *iommu;
     unsigned int idx;
@@ -346,14 +346,6 @@ void cf_check amd_iommu_ioapic_update_ire(
         return;
     }
 
-    old_rte = __ioapic_read_entry(apic, pin, true);
-    /* mask the interrupt while we change the intremap table */
-    if ( !old_rte.mask )
-    {
-        old_rte.mask = 1;
-        __ioapic_write_entry(apic, pin, true, old_rte);
-    }
-
     /* Update interrupt remapping entry */
     rc = update_intremap_entry_from_ioapic(
              bdf, iommu, &new_rte,
@@ -425,6 +417,7 @@ static int update_intremap_entry_from_msi_msg(
     uint8_t delivery_mode, vector, dest_mode;
     spinlock_t *lock;
     unsigned int dest, offset, i;
+    bool fresh = false;
 
     req_id = get_dma_requestor_id(iommu->seg, bdf);
     alias_id = get_intremap_requestor_id(iommu->seg, bdf);
@@ -468,26 +461,21 @@ static int update_intremap_entry_from_msi_msg(
             return -ENOSPC;
         }
         *remap_index = offset;
+        fresh = true;
     }
 
     entry = get_intremap_entry(iommu, req_id, offset);
 
-    /* The RemapEn fields match for all formats. */
-    while ( iommu->enabled && entry.ptr32->flds.remap_en )
-    {
-        entry.ptr32->flds.remap_en = false;
-        spin_unlock(lock);
+    update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
+    spin_unlock_irqrestore(lock, flags);
 
+    if ( !fresh )
+    {
         amd_iommu_flush_intremap(iommu, req_id);
         if ( alias_id != req_id )
             amd_iommu_flush_intremap(iommu, alias_id);
-
-        spin_lock(lock);
     }
 
-    update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
-    spin_unlock_irqrestore(lock, flags);
-
     *data = (msg->data & ~(INTREMAP_MAX_ENTRIES - 1)) | offset;
 
     /*
@@ -735,7 +723,7 @@ static void dump_intremap_table(const struct amd_iommu *iommu,
     for ( count = 0; count < nr; count++ )
     {
         if ( iommu->ctrl.ga_en
-             ? !tbl.ptr128[count].raw[0] && !tbl.ptr128[count].raw[1]
+             ? !tbl.ptr128[count].raw64[0] && !tbl.ptr128[count].raw64[1]
              : !tbl.ptr32[count].raw )
                 continue;
 
@@ -748,7 +736,8 @@ static void dump_intremap_table(const struct amd_iommu *iommu,
 
         if ( iommu->ctrl.ga_en )
             printk("    IRTE[%03x] %016lx_%016lx\n",
-                   count, tbl.ptr128[count].raw[1], tbl.ptr128[count].raw[0]);
+                   count, tbl.ptr128[count].raw64[1],
+                   tbl.ptr128[count].raw64[0]);
         else
             printk("    IRTE[%03x] %08x\n", count, tbl.ptr32[count].raw);
     }
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/iommu: check for CMPXCHG16B when enabling IOMMU
Message-Id: <E1tcOtJ-005v68-38@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 13:11:01 +0000

commit 2636fcdc15c707d5e097770133f0afb69e8d70c9
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Fri Jan 24 12:31:15 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    x86/iommu: check for CMPXCHG16B when enabling IOMMU
    
    All hardware with VT-d/AMD-Vi has CMPXCHG16B support. Check this at
    initialisation time, and otherwise refuse to use the IOMMU.
    
    If the local APICs support x2APIC mode the IOMMU support for interrupt
    remapping will be checked earlier using a specific helper.  If no support
    for CX16 is detected by that earlier hook disable the IOMMU at that point
    and prevent further poking for CX16 later in the boot process, which would
    also fail.
    
    There's a possible corner case when running virtualized, and the underlying
    hypervisor exposing an IOMMU but no CMPXCHG16B support.  In which case
    ignoring the IOMMU is fine, albeit the most natural would be for the
    underlying hypervisor to also expose CMPXCHG16B support if an IOMMU is
    available to the VM.
    
    Note this change only introduces the checks, but doesn't remove the now
    stale checks for CX16 support sprinkled in the IOMMU code.  Further changes
    will take care of that.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_intr.c    | 13 +++++++++++++
 xen/drivers/passthrough/amd/pci_amd_iommu.c |  6 ++++++
 xen/drivers/passthrough/vtd/intremap.c      | 13 +++++++++++++
 xen/drivers/passthrough/vtd/iommu.c         |  7 +++++++
 4 files changed, 39 insertions(+)

diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c
index 7fc796dec2..f07fd9e3d9 100644
--- a/xen/drivers/passthrough/amd/iommu_intr.c
+++ b/xen/drivers/passthrough/amd/iommu_intr.c
@@ -649,6 +649,19 @@ bool __init cf_check iov_supports_xt(void)
     if ( !iommu_enable || !iommu_intremap )
         return false;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        AMD_IOMMU_ERROR("no CMPXCHG16B support, disabling IOMMU\n");
+        /*
+         * Disable IOMMU support at once: there's no reason to check for CX16
+         * yet again when attempting to initialize IOMMU DMA remapping
+         * functionality or interrupt remapping without x2APIC support.
+         */
+        iommu_enable = false;
+        iommu_intremap = iommu_intremap_off;
+        return false;
+    }
+
     if ( amd_iommu_prepare(true) )
         return false;
 
diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c
index 73dcc4a2dd..f96f59440b 100644
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c
@@ -309,6 +309,12 @@ static int __init cf_check iov_detect(void)
     if ( !iommu_enable && !iommu_intremap )
         return 0;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        AMD_IOMMU_ERROR("no CMPXCHG16B support, disabling IOMMU\n");
+        return -ENODEV;
+    }
+
     if ( (init_done ? amd_iommu_init_late()
                     : amd_iommu_init(false)) != 0 )
     {
diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c
index c504852eb8..233db5cb64 100644
--- a/xen/drivers/passthrough/vtd/intremap.c
+++ b/xen/drivers/passthrough/vtd/intremap.c
@@ -150,6 +150,19 @@ bool __init cf_check intel_iommu_supports_eim(void)
     if ( !iommu_qinval || !iommu_intremap || list_empty(&acpi_drhd_units) )
         return false;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        printk(XENLOG_ERR VTDPREFIX "no CMPXCHG16B support, disabling IOMMU\n");
+        /*
+         * Disable IOMMU support at once: there's no reason to check for CX16
+         * yet again when attempting to initialize IOMMU DMA remapping
+         * functionality or interrupt remapping without x2APIC support.
+         */
+        iommu_enable = false;
+        iommu_intremap = iommu_intremap_off;
+        return false;
+    }
+
     /* We MUST have a DRHD unit for each IOAPIC. */
     for ( apic = 0; apic < nr_ioapics; apic++ )
         if ( !ioapic_to_drhd(IO_APIC_ID(apic)) )
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index 27a4d16401..3daedc4f55 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -2633,6 +2633,13 @@ static int __init cf_check vtd_setup(void)
     int ret;
     bool reg_inval_supported = true;
 
+    if ( unlikely(!cpu_has_cx16) )
+    {
+        printk(XENLOG_ERR VTDPREFIX "no CMPXCHG16B support, disabling IOMMU\n");
+        ret = -ENODEV;
+        goto error;
+    }
+
     if ( list_empty(&acpi_drhd_units) )
     {
         ret = -ENODEV;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] iommu/vtd: remove non-CX16 logic from interrupt remapping
Message-Id: <E1tcOtU-005v6y-0G@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 13:11:12 +0000

commit 848b6bc8c9f37edaf6992c4716a06816ccb0b19e
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:21 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/vtd: remove non-CX16 logic from interrupt remapping
    
    As CX16 support is now mandatory for IOMMU usage, the checks for CX16 in
    the interrupt remapping code are stale.  Remove them together with the
    associated code introduced in case CX16 was not available.
    
    Note that AMD-Vi support for atomically updating a 128bit IRTE entry is
    still not implemented, it will be done by further changes.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/vtd/intremap.c | 75 +++++++---------------------------
 1 file changed, 14 insertions(+), 61 deletions(-)

diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c
index 233db5cb64..820616a8de 100644
--- a/xen/drivers/passthrough/vtd/intremap.c
+++ b/xen/drivers/passthrough/vtd/intremap.c
@@ -184,49 +184,26 @@ bool __init cf_check intel_iommu_supports_eim(void)
 
 /*
  * Assume iremap_lock has been acquired. It is to make sure software will not
- * change the same IRTE behind us. With this assumption, if only high qword or
- * low qword in IRTE is to be updated, this function's atomic variant can
- * present an atomic update to VT-d hardware even when cmpxchg16b
- * instruction is not supported.
+ * change the same IRTE behind us.
  */
 static void update_irte(struct vtd_iommu *iommu, struct iremap_entry *entry,
                         const struct iremap_entry *new_ire, bool atomic)
 {
-    ASSERT(spin_is_locked(&iommu->intremap.lock));
+    __uint128_t ret;
+    struct iremap_entry old_ire;
 
-    if ( cpu_has_cx16 )
-    {
-        __uint128_t ret;
-        struct iremap_entry old_ire;
+    ASSERT(spin_is_locked(&iommu->intremap.lock));
 
-        old_ire = *entry;
-        ret = cmpxchg16b(entry, &old_ire, new_ire);
+    old_ire = *entry;
+    ret = cmpxchg16b(entry, &old_ire, new_ire);
 
-        /*
-         * In the above, we use cmpxchg16 to atomically update the 128-bit
-         * IRTE, and the hardware cannot update the IRTE behind us, so
-         * the return value of cmpxchg16 should be the same as old_ire.
-         * This ASSERT validate it.
-         */
-        ASSERT(ret == old_ire.val);
-    }
-    else
-    {
-        /*
-         * VT-d hardware doesn't update IRTEs behind us, nor the software
-         * since we hold iremap_lock. If the caller wants VT-d hardware to
-         * always see a consistent entry, but we can't meet it, a bug will
-         * be raised.
-         */
-        if ( entry->lo == new_ire->lo )
-            write_atomic(&entry->hi, new_ire->hi);
-        else if ( entry->hi == new_ire->hi )
-            write_atomic(&entry->lo, new_ire->lo);
-        else if ( !atomic )
-            *entry = *new_ire;
-        else
-            BUG();
-    }
+    /*
+     * In the above, we use cmpxchg16 to atomically update the 128-bit
+     * IRTE, and the hardware cannot update the IRTE behind us, so
+     * the return value of cmpxchg16 should be the same as old_ire.
+     * This ASSERT validate it.
+     */
+    ASSERT(ret == old_ire.val);
 }
 
 /* Mark specified intr remap entry as free */
@@ -408,7 +385,6 @@ static int ioapic_rte_to_remap_entry(struct vtd_iommu *iommu,
     /* Indicate remap format. */
     remap_rte->format = 1;
 
-    /* If cmpxchg16b is not available the caller must mask the IO-APIC pin. */
     update_irte(iommu, iremap_entry, &new_ire, !init && !masked);
     iommu_sync_cache(iremap_entry, sizeof(*iremap_entry));
     iommu_flush_iec_index(iommu, 0, index);
@@ -447,38 +423,15 @@ void cf_check io_apic_write_remap_rte(
 {
     struct IO_xAPIC_route_entry old_rte = {}, new_rte;
     struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic));
-    bool masked = true;
     int rc;
 
-    if ( !cpu_has_cx16 )
-    {
-       /*
-        * Cannot atomically update the IRTE entry: mask the IO-APIC pin to
-        * avoid interrupts seeing an inconsistent IRTE entry.
-        */
-        old_rte = __ioapic_read_entry(apic, pin, true);
-        if ( !old_rte.mask )
-        {
-            masked = false;
-            old_rte.mask = 1;
-            __ioapic_write_entry(apic, pin, true, old_rte);
-        }
-    }
-
     /* Not the initializer, for old gcc to cope. */
     new_rte.raw = rte;
 
     rc = ioapic_rte_to_remap_entry(iommu, apic, pin, &old_rte, new_rte);
     if ( rc )
-    {
-        if ( !masked )
-        {
-            /* Recover the original value of 'mask' bit */
-            old_rte.mask = 0;
-            __ioapic_write_entry(apic, pin, true, old_rte);
-        }
         return;
-    }
+
     /* old_rte will contain the updated IO-APIC RTE on success. */
     __ioapic_write_entry(apic, pin, true, old_rte);
 }
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/iommu: remove non-CX16 logic from DMA remapping
Message-Id: <E1tcOte-005v7g-0d@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 13:11:22 +0000

commit 3fc44151d83d3d63320036bcf06634dfbebe1ff3
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:20 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    x86/iommu: remove non-CX16 logic from DMA remapping
    
    As CX16 support is now mandatory for IOMMU usage, the checks for CX16 in
    the DMA remapping code are stale.  Remove them together with the associated
    code introduced in case CX16 was not available.
    
    Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_map.c | 42 +++++++------------
 xen/drivers/passthrough/vtd/iommu.c     | 71 ++++++++-------------------------
 2 files changed, 31 insertions(+), 82 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthrough/amd/iommu_map.c
index 1f0e416756..dde393645a 100644
--- a/xen/drivers/passthrough/amd/iommu_map.c
+++ b/xen/drivers/passthrough/amd/iommu_map.c
@@ -167,15 +167,14 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte,
 {
     bool valid = flags & SET_ROOT_VALID;
 
-    if ( dte->v && dte->tv &&
-         (cpu_has_cx16 || (flags & SET_ROOT_WITH_UNITY_MAP)) )
+    if ( dte->v && dte->tv )
     {
         union {
             struct amd_iommu_dte dte;
             uint64_t raw64[4];
             __uint128_t raw128[2];
         } ldte = { .dte = *dte };
-        __uint128_t old = ldte.raw128[0];
+        __uint128_t res, old = ldte.raw128[0];
         int ret = 0;
 
         ldte.dte.domain_id = domain_id;
@@ -185,33 +184,20 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte,
         ldte.dte.paging_mode = paging_mode;
         ldte.dte.v = valid;
 
-        if ( cpu_has_cx16 )
-        {
-            __uint128_t res = cmpxchg16b(dte, &old, &ldte.raw128[0]);
+        res = cmpxchg16b(dte, &old, &ldte.raw128[0]);
 
-            /*
-             * Hardware does not update the DTE behind our backs, so the
-             * return value should match "old".
-             */
-            if ( res != old )
-            {
-                printk(XENLOG_ERR
-                       "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n",
-                       domain_id,
-                       (uint64_t)(res >> 64), (uint64_t)res,
-                       (uint64_t)(old >> 64), (uint64_t)old);
-                ret = -EILSEQ;
-            }
-        }
-        else /* Best effort, updating domain_id last. */
+        /*
+         * Hardware does not update the DTE behind our backs, so the
+         * return value should match "old".
+         */
+        if ( res != old )
         {
-            uint64_t *ptr = (void *)dte;
-
-            write_atomic(ptr + 0, ldte.raw64[0]);
-            /* No barrier should be needed between these two. */
-            write_atomic(ptr + 1, ldte.raw64[1]);
-
-            ret = 1;
+            printk(XENLOG_ERR
+                   "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n",
+                   domain_id,
+                   (uint64_t)(res >> 64), (uint64_t)res,
+                   (uint64_t)(old >> 64), (uint64_t)old);
+            ret = -EILSEQ;
         }
 
         return ret;
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index 3daedc4f55..b0963bfcf7 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1485,7 +1485,7 @@ int domain_context_mapping_one(
 {
     struct domain_iommu *hd = dom_iommu(domain);
     struct context_entry *context, *context_entries, lctxt;
-    __uint128_t old;
+    __uint128_t res, old;
     uint64_t maddr;
     uint16_t seg = iommu->drhd->segment, prev_did = 0;
     struct domain *prev_dom = NULL;
@@ -1583,55 +1583,23 @@ int domain_context_mapping_one(
         ASSERT(!context_fault_disable(lctxt));
     }
 
-    if ( cpu_has_cx16 )
-    {
-        __uint128_t res = cmpxchg16b(context, &old, &lctxt.full);
-
-        /*
-         * Hardware does not update the context entry behind our backs,
-         * so the return value should match "old".
-         */
-        if ( res != old )
-        {
-            if ( pdev )
-                check_cleanup_domid_map(domain, pdev, iommu);
-            printk(XENLOG_ERR
-                   "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n",
-                   &PCI_SBDF(seg, bus, devfn),
-                   (uint64_t)(res >> 64), (uint64_t)res,
-                   (uint64_t)(old >> 64), (uint64_t)old);
-            rc = -EILSEQ;
-            goto unlock;
-        }
-    }
-    else if ( !prev_dom || !(mode & MAP_WITH_RMRR) )
-    {
-        context_clear_present(*context);
-        iommu_sync_cache(context, sizeof(*context));
+    res = cmpxchg16b(context, &old, &lctxt.full);
 
-        write_atomic(&context->hi, lctxt.hi);
-        /* No barrier should be needed between these two. */
-        write_atomic(&context->lo, lctxt.lo);
-    }
-    else /* Best effort, updating DID last. */
+    /*
+     * Hardware does not update the context entry behind our backs,
+     * so the return value should match "old".
+     */
+    if ( res != old )
     {
-         /*
-          * By non-atomically updating the context entry's DID field last,
-          * during a short window in time TLB entries with the old domain ID
-          * but the new page tables may be inserted.  This could affect I/O
-          * of other devices using this same (old) domain ID.  Such updating
-          * therefore is not a problem if this was the only device associated
-          * with the old domain ID.  Diverting I/O of any of a dying domain's
-          * devices to the quarantine page tables is intended anyway.
-          */
-        if ( !(mode & (MAP_OWNER_DYING | MAP_SINGLE_DEVICE)) )
-            printk(XENLOG_WARNING VTDPREFIX
-                   " %pp: reassignment may cause %pd data corruption\n",
-                   &PCI_SBDF(seg, bus, devfn), prev_dom);
-
-        write_atomic(&context->lo, lctxt.lo);
-        /* No barrier should be needed between these two. */
-        write_atomic(&context->hi, lctxt.hi);
+        if ( pdev )
+            check_cleanup_domid_map(domain, pdev, iommu);
+        printk(XENLOG_ERR
+                "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n",
+                &PCI_SBDF(seg, bus, devfn),
+                (uint64_t)(res >> 64), (uint64_t)res,
+                (uint64_t)(old >> 64), (uint64_t)old);
+        rc = -EILSEQ;
+        goto unlock;
     }
 
     iommu_sync_cache(context, sizeof(struct context_entry));
@@ -2702,12 +2670,7 @@ static int __init cf_check vtd_setup(void)
             iommu_intremap = iommu_intremap_off;
 
 #ifndef iommu_intpost
-        /*
-         * We cannot use posted interrupt if X86_FEATURE_CX16 is
-         * not supported, since we count on this feature to
-         * atomically update 16-byte IRTE in posted format.
-         */
-        if ( !cap_intr_post(iommu->cap) || !iommu_intremap || !cpu_has_cx16 )
+        if ( !cap_intr_post(iommu->cap) || !iommu_intremap )
             iommu_intpost = false;
 #endif
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] iommu/vtd: cleanup MAP_SINGLE_DEVICE and related code
Message-Id: <E1tcOto-005v9z-0z@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 13:11:32 +0000

commit a2bbb140be9d176226495cb991af59721c34b3f1
Author:     Teddy Astie <teddy.astie@vates.tech>
AuthorDate: Thu Apr 18 11:57:21 2024 +0000
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/vtd: cleanup MAP_SINGLE_DEVICE and related code
    
    This flag was only used in case cx16 is not available, as those code paths no
    longer exist, this flag now does basically nothing.
    
    Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/vtd/iommu.c | 12 +++---------
 xen/drivers/passthrough/vtd/vtd.h   |  5 ++---
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index b0963bfcf7..9d7a9977a6 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1695,15 +1695,9 @@ static int domain_context_mapping(struct domain *domain, u8 devfn,
         break;
     }
 
-    if ( domain != pdev->domain && pdev->domain != dom_io )
-    {
-        if ( pdev->domain->is_dying )
-            mode |= MAP_OWNER_DYING;
-        else if ( drhd &&
-                  !any_pdev_behind_iommu(pdev->domain, pdev, drhd->iommu) &&
-                  !pdev->phantom_stride )
-            mode |= MAP_SINGLE_DEVICE;
-    }
+    if ( domain != pdev->domain && pdev->domain != dom_io &&
+         pdev->domain->is_dying )
+        mode |= MAP_OWNER_DYING;
 
     switch ( pdev->type )
     {
diff --git a/xen/drivers/passthrough/vtd/vtd.h b/xen/drivers/passthrough/vtd/vtd.h
index 8aeff8c1f2..b95124517b 100644
--- a/xen/drivers/passthrough/vtd/vtd.h
+++ b/xen/drivers/passthrough/vtd/vtd.h
@@ -28,9 +28,8 @@
  */
 #define MAP_WITH_RMRR         (1u << 0)
 #define MAP_OWNER_DYING       (1u << 1)
-#define MAP_SINGLE_DEVICE     (1u << 2)
-#define MAP_ERROR_RECOVERY    (1u << 3)
-#define UNMAP_ME_PHANTOM_FUNC (1u << 4)
+#define MAP_ERROR_RECOVERY    (1u << 2)
+#define UNMAP_ME_PHANTOM_FUNC (1u << 3)
 
 /* Allow for both IOAPIC and IOSAPIC. */
 #define IO_xAPIC_route_entry IO_APIC_route_entry
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] iommu/amd: atomically update IRTE
Message-Id: <E1tcOty-005vAX-1I@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 13:11:42 +0000

commit b953a99da98d63a7c827248abc450d4e8e015ab6
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Mon Jan 20 15:48:21 2025 +0100
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Mon Jan 27 13:05:11 2025 +0100

    iommu/amd: atomically update IRTE
    
    Either when using a 32bit Interrupt Remapping Entry or a 128bit one update
    the entry atomically, by using cmpxchg unconditionally as IOMMU depends on
    it.  No longer disable the entry by setting RemapEn = 0 ahead of updating
    it.  As a consequence of not toggling RemapEn ahead of the update the
    Interrupt Remapping Table needs to be flushed after the entry update.
    
    This avoids a window where the IRTE has RemapEn = 0, which can lead to
    IO_PAGE_FAULT if the underlying interrupt source is not masked.
    
    There's no guidance in AMD-Vi specification about how IRTE update should be
    performed as opposed to DTE updating which has specific guidance.  However
    DTE updating claims that reads will always be at least 128bits in size, and
    hence for the purposes here assume that reads and caching of the IRTE
    entries in either 32 or 128 bit format will be done atomically from
    the IOMMU.
    
    Note that as part of introducing a new raw128 field in the IRTE struct, the
    current raw field is renamed to raw64 to explicitly contain the size in the
    field name.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/drivers/passthrough/amd/iommu_intr.c | 75 ++++++++++++++------------------
 1 file changed, 32 insertions(+), 43 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c
index f07fd9e3d9..c0273059cb 100644
--- a/xen/drivers/passthrough/amd/iommu_intr.c
+++ b/xen/drivers/passthrough/amd/iommu_intr.c
@@ -39,7 +39,8 @@ union irte32 {
 };
 
 union irte128 {
-    uint64_t raw[2];
+    uint64_t raw64[2];
+    __uint128_t raw128;
     struct {
         bool remap_en:1;
         bool sup_io_pf:1;
@@ -187,7 +188,7 @@ static void free_intremap_entry(const struct amd_iommu *iommu,
 
     if ( iommu->ctrl.ga_en )
     {
-        ACCESS_ONCE(entry.ptr128->raw[0]) = 0;
+        ACCESS_ONCE(entry.ptr128->raw64[0]) = 0;
         /*
          * Low half (containing RemapEn) needs to be cleared first.  Note that
          * strictly speaking smp_wmb() isn't enough, as conceptually it expands
@@ -197,7 +198,7 @@ static void free_intremap_entry(const struct amd_iommu *iommu,
          * variant will do.
          */
         smp_wmb();
-        entry.ptr128->raw[1] = 0;
+        entry.ptr128->raw64[1] = 0;
     }
     else
         ACCESS_ONCE(entry.ptr32->raw) = 0;
@@ -212,7 +213,7 @@ static void update_intremap_entry(const struct amd_iommu *iommu,
 {
     if ( iommu->ctrl.ga_en )
     {
-        union irte128 irte = {
+        const union irte128 irte = {
             .full = {
                 .remap_en = true,
                 .int_type = int_type,
@@ -222,19 +223,26 @@ static void update_intremap_entry(const struct amd_iommu *iommu,
                 .vector = vector,
             },
         };
+        __uint128_t old = entry.ptr128->raw128;
+        __uint128_t res = cmpxchg16b(&entry.ptr128->raw128, &old,
+                                     &irte.raw128);
 
-        ASSERT(!entry.ptr128->full.remap_en);
-        entry.ptr128->raw[1] = irte.raw[1];
         /*
-         * High half needs to be set before low one (containing RemapEn).  See
-         * comment in free_intremap_entry() regarding the choice of barrier.
+         * Hardware does not update the IRTE behind our backs, so the return
+         * value should match "old".
          */
-        smp_wmb();
-        ACCESS_ONCE(entry.ptr128->raw[0]) = irte.raw[0];
+        if ( res != old )
+        {
+            printk(XENLOG_ERR
+                   "unexpected IRTE %016lx_%016lx (expected %016lx_%016lx)\n",
+                   (uint64_t)(res >> 64), (uint64_t)res,
+                   (uint64_t)(old >> 64), (uint64_t)old);
+            ASSERT_UNREACHABLE();
+        }
     }
     else
     {
-        union irte32 irte = {
+        const union irte32 irte = {
             .flds = {
                 .remap_en = true,
                 .int_type = int_type,
@@ -299,21 +307,13 @@ static int update_intremap_entry_from_ioapic(
 
     entry = get_intremap_entry(iommu, req_id, offset);
 
-    /* The RemapEn fields match for all formats. */
-    while ( iommu->enabled && entry.ptr32->flds.remap_en )
-    {
-        entry.ptr32->flds.remap_en = false;
-        spin_unlock(lock);
-
-        amd_iommu_flush_intremap(iommu, req_id);
-
-        spin_lock(lock);
-    }
-
     update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
 
     spin_unlock_irqrestore(lock, flags);
 
+    if ( !fresh )
+        amd_iommu_flush_intremap(iommu, req_id);
+
     set_rte_index(rte, offset);
 
     return 0;
@@ -322,7 +322,7 @@ static int update_intremap_entry_from_ioapic(
 void cf_check amd_iommu_ioapic_update_ire(
     unsigned int apic, unsigned int pin, uint64_t rte)
 {
-    struct IO_APIC_route_entry old_rte, new_rte;
+    struct IO_APIC_route_entry new_rte;
     int seg, bdf, rc;
     struct amd_iommu *iommu;
     unsigned int idx;
@@ -346,14 +346,6 @@ void cf_check amd_iommu_ioapic_update_ire(
         return;
     }
 
-    old_rte = __ioapic_read_entry(apic, pin, true);
-    /* mask the interrupt while we change the intremap table */
-    if ( !old_rte.mask )
-    {
-        old_rte.mask = 1;
-        __ioapic_write_entry(apic, pin, true, old_rte);
-    }
-
     /* Update interrupt remapping entry */
     rc = update_intremap_entry_from_ioapic(
              bdf, iommu, &new_rte,
@@ -425,6 +417,7 @@ static int update_intremap_entry_from_msi_msg(
     uint8_t delivery_mode, vector, dest_mode;
     spinlock_t *lock;
     unsigned int dest, offset, i;
+    bool fresh = false;
 
     req_id = get_dma_requestor_id(iommu->seg, bdf);
     alias_id = get_intremap_requestor_id(iommu->seg, bdf);
@@ -468,26 +461,21 @@ static int update_intremap_entry_from_msi_msg(
             return -ENOSPC;
         }
         *remap_index = offset;
+        fresh = true;
     }
 
     entry = get_intremap_entry(iommu, req_id, offset);
 
-    /* The RemapEn fields match for all formats. */
-    while ( iommu->enabled && entry.ptr32->flds.remap_en )
-    {
-        entry.ptr32->flds.remap_en = false;
-        spin_unlock(lock);
+    update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
+    spin_unlock_irqrestore(lock, flags);
 
+    if ( !fresh )
+    {
         amd_iommu_flush_intremap(iommu, req_id);
         if ( alias_id != req_id )
             amd_iommu_flush_intremap(iommu, alias_id);
-
-        spin_lock(lock);
     }
 
-    update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest);
-    spin_unlock_irqrestore(lock, flags);
-
     *data = (msg->data & ~(INTREMAP_MAX_ENTRIES - 1)) | offset;
 
     /*
@@ -735,7 +723,7 @@ static void dump_intremap_table(const struct amd_iommu *iommu,
     for ( count = 0; count < nr; count++ )
     {
         if ( iommu->ctrl.ga_en
-             ? !tbl.ptr128[count].raw[0] && !tbl.ptr128[count].raw[1]
+             ? !tbl.ptr128[count].raw64[0] && !tbl.ptr128[count].raw64[1]
              : !tbl.ptr32[count].raw )
                 continue;
 
@@ -748,7 +736,8 @@ static void dump_intremap_table(const struct amd_iommu *iommu,
 
         if ( iommu->ctrl.ga_en )
             printk("    IRTE[%03x] %016lx_%016lx\n",
-                   count, tbl.ptr128[count].raw[1], tbl.ptr128[count].raw[0]);
+                   count, tbl.ptr128[count].raw64[1],
+                   tbl.ptr128[count].raw64[0]);
         else
             printk("    IRTE[%03x] %08x\n", count, tbl.ptr32[count].raw);
     }
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86emul: further correct 64-bit mode zero count repeated string insn handling
Message-Id: <E1tcQAj-006DKJ-0Z@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 14:33:05 +0000

commit 5310a042c4e3135c471446c8253ad13250539957
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon Jan 27 15:23:19 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon Jan 27 15:23:19 2025 +0100

    x86emul: further correct 64-bit mode zero count repeated string insn handling
    
    In an entirely different context I came across Linux commit 428e3d08574b
    ("KVM: x86: Fix zero iterations REP-string"), which points out that
    we're still doing things wrong: For one, there's no zero-extension at
    all on AMD. And then while RCX is zero-extended from 32 bits uniformly
    for all string instructions on newer hardware, RSI/RDI are only for MOVS
    and STOS on the systems I have access to. (On an old family 0xf system
    I've further found that for REP LODS even RCX is not zero-extended.)
    
    While touching the lines anyway, replace two casts in get_rep_prefix().
    
    Fixes: 79e996a89f69 ("x86emul: correct 64-bit mode repeated string insn handling with zero count")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Released-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 7e12b19805..535d803588 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -513,7 +513,7 @@ static inline void put_loop_count(
         regs->r(cx) = ad_bytes == 4 ? (uint32_t)count : count;
 }
 
-#define get_rep_prefix(using_si, using_di) ({                           \
+#define get_rep_prefix(extend_si, extend_di) ({                         \
     unsigned long max_reps = 1;                                         \
     if ( rep_prefix() )                                                 \
         max_reps = get_loop_count(&_regs, ad_bytes);                    \
@@ -521,14 +521,14 @@ static inline void put_loop_count(
     {                                                                   \
         /*                                                              \
          * Skip the instruction if no repetitions are required, but     \
-         * zero extend involved registers first when using 32-bit       \
+         * zero extend relevant registers first when using 32-bit       \
          * addressing in 64-bit mode.                                   \
          */                                                             \
-        if ( mode_64bit() && ad_bytes == 4 )                            \
+        if ( !amd_like(ctxt) && mode_64bit() && ad_bytes == 4 )         \
         {                                                               \
             _regs.r(cx) = 0;                                            \
-            if ( using_si ) _regs.r(si) = (uint32_t)_regs.r(si);        \
-            if ( using_di ) _regs.r(di) = (uint32_t)_regs.r(di);        \
+            if ( extend_si ) _regs.r(si) = _regs.esi;                   \
+            if ( extend_di ) _regs.r(di) = _regs.edi;                   \
         }                                                               \
         goto complete_insn;                                             \
     }                                                                   \
@@ -1818,7 +1818,7 @@ x86_emulate(
         dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
         if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
             goto done;
-        nr_reps = get_rep_prefix(false, true);
+        nr_reps = get_rep_prefix(false, false /* don't extend RSI/RDI */);
         dst.mem.off = truncate_ea_and_reps(_regs.r(di), nr_reps, dst.bytes);
         dst.mem.seg = x86_seg_es;
         /* Try the presumably most efficient approach first. */
@@ -1860,7 +1860,7 @@ x86_emulate(
         dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
         if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
             goto done;
-        nr_reps = get_rep_prefix(true, false);
+        nr_reps = get_rep_prefix(false, false /* don't extend RSI/RDI */);
         ea.mem.off = truncate_ea_and_reps(_regs.r(si), nr_reps, dst.bytes);
         /* Try the presumably most efficient approach first. */
         if ( !ops->rep_outs )
@@ -2198,7 +2198,7 @@ x86_emulate(
     case 0xa6 ... 0xa7: /* cmps */ {
         unsigned long next_eip = _regs.r(ip);
 
-        get_rep_prefix(true, true);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
         if ( (rc = read_ulong(ea.mem.seg, truncate_ea(_regs.r(si)),
                               &dst.val, dst.bytes, ctxt, ops)) ||
@@ -2240,7 +2240,7 @@ x86_emulate(
     }
 
     case 0xac ... 0xad: /* lods */
-        get_rep_prefix(true, false);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         if ( (rc = read_ulong(ea.mem.seg, truncate_ea(_regs.r(si)),
                               &dst.val, dst.bytes, ctxt, ops)) != 0 )
             goto done;
@@ -2251,7 +2251,7 @@ x86_emulate(
     case 0xae ... 0xaf: /* scas */ {
         unsigned long next_eip = _regs.r(ip);
 
-        get_rep_prefix(false, true);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         if ( (rc = read_ulong(x86_seg_es, truncate_ea(_regs.r(di)),
                               &dst.val, src.bytes, ctxt, ops)) != 0 )
             goto done;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/PV: further harden guest memory accesses against speculative abuse
Message-Id: <E1tcQAt-006DMA-0z@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 14:33:15 +0000

commit 8306d773b03acec6062c0547ac05e3dd4a6960f6
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon Jan 27 15:23:59 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon Jan 27 15:23:59 2025 +0100

    x86/PV: further harden guest memory accesses against speculative abuse
    
    The original implementation has two issues: For one it doesn't preserve
    non-canonical-ness of inputs in the range 0x8000000000000000 through
    0x80007fffffffffff. Bogus guest pointers in that range would not cause a
    (#GP) fault upon access, when they should.
    
    And then there is an AMD-specific aspect, where only the low 48 bits of
    an address are used for speculative execution; the architecturally
    mandated #GP for non-canonical addresses would be raised at a later
    execution stage. Therefore to prevent Xen controlled data to make it
    into any of the caches in a guest controllable manner, we need to
    additionally ensure that for non-canonical inputs bit 47 would be clear.
    
    See the code comment for how addressing both is being achieved.
    
    Fixes: 4dc181599142 ("x86/PV: harden guest memory accesses against speculative abuse")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/include/asm/asm-defns.h | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
index d55dd3bbc3..32d6b44910 100644
--- a/xen/arch/x86/include/asm/asm-defns.h
+++ b/xen/arch/x86/include/asm/asm-defns.h
@@ -1,3 +1,5 @@
+#include <asm/page-bits.h>
+
 #ifndef HAVE_AS_CLAC_STAC
 .macro clac
     .byte 0x0f, 0x01, 0xca
@@ -65,17 +67,36 @@
 .macro guest_access_mask_ptr ptr:req, scratch1:req, scratch2:req
 #if defined(CONFIG_SPECULATIVE_HARDEN_GUEST_ACCESS)
     /*
-     * Here we want
-     *
-     * ptr &= ~0ull >> (ptr < HYPERVISOR_VIRT_END);
-     *
+     * Here we want to adjust \ptr such that
+     * - if it's within Xen range, it becomes non-canonical,
+     * - otherwise if it's (non-)canonical on input, it retains that property,
+     * - if the result is non-canonical, bit 47 is clear (to avoid
+     *   potentially populating the cache with Xen data on AMD-like hardware),
      * but guaranteed without any conditional branches (hence in assembly).
+     *
+     * To achieve this we determine which bit to forcibly clear: Either bit 47
+     * (in case the address is below HYPERVISOR_VIRT_END) or bit 63.  Further
+     * we determine whether for forcably set bit 63: In case we first cleared
+     * it, we'll merely restore the original address.  In case we ended up
+     * clearing bit 47 (i.e. the address was either non-canonical or within Xen
+     * range), setting the bit will yield a guaranteed non-canonical address.
+     * If we didn't clear a bit, we also won't set one: The address was in the
+     * low half of address space in that case with bit 47 already clear.  The
+     * address can thus be left unchanged, whether canonical or not.
      */
     mov $(HYPERVISOR_VIRT_END - 1), \scratch1
-    mov $~0, \scratch2
+    mov $(VADDR_BITS - 1), \scratch2
     cmp \ptr, \scratch1
+    /*
+     * Not needed: The value we have in \scratch1 will be truncated to 6 bits,
+     * thus yielding the value we need.
+    mov $63, \scratch1
+     */
+    cmovnb \scratch2, \scratch1
+    xor \scratch2, \scratch2
+    btr \scratch1, \ptr
     rcr $1, \scratch2
-    and \scratch2, \ptr
+    or \scratch2, \ptr
 #elif defined(CONFIG_DEBUG) && defined(CONFIG_PV)
     xor $~\@, \scratch1
     xor $~\@, \scratch2
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86emul: further correct 64-bit mode zero count repeated string insn handling
Message-Id: <E1tcT9W-006hbR-0X@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 17:44:02 +0000

commit 5310a042c4e3135c471446c8253ad13250539957
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon Jan 27 15:23:19 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon Jan 27 15:23:19 2025 +0100

    x86emul: further correct 64-bit mode zero count repeated string insn handling
    
    In an entirely different context I came across Linux commit 428e3d08574b
    ("KVM: x86: Fix zero iterations REP-string"), which points out that
    we're still doing things wrong: For one, there's no zero-extension at
    all on AMD. And then while RCX is zero-extended from 32 bits uniformly
    for all string instructions on newer hardware, RSI/RDI are only for MOVS
    and STOS on the systems I have access to. (On an old family 0xf system
    I've further found that for REP LODS even RCX is not zero-extended.)
    
    While touching the lines anyway, replace two casts in get_rep_prefix().
    
    Fixes: 79e996a89f69 ("x86emul: correct 64-bit mode repeated string insn handling with zero count")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
    Released-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 7e12b19805..535d803588 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -513,7 +513,7 @@ static inline void put_loop_count(
         regs->r(cx) = ad_bytes == 4 ? (uint32_t)count : count;
 }
 
-#define get_rep_prefix(using_si, using_di) ({                           \
+#define get_rep_prefix(extend_si, extend_di) ({                         \
     unsigned long max_reps = 1;                                         \
     if ( rep_prefix() )                                                 \
         max_reps = get_loop_count(&_regs, ad_bytes);                    \
@@ -521,14 +521,14 @@ static inline void put_loop_count(
     {                                                                   \
         /*                                                              \
          * Skip the instruction if no repetitions are required, but     \
-         * zero extend involved registers first when using 32-bit       \
+         * zero extend relevant registers first when using 32-bit       \
          * addressing in 64-bit mode.                                   \
          */                                                             \
-        if ( mode_64bit() && ad_bytes == 4 )                            \
+        if ( !amd_like(ctxt) && mode_64bit() && ad_bytes == 4 )         \
         {                                                               \
             _regs.r(cx) = 0;                                            \
-            if ( using_si ) _regs.r(si) = (uint32_t)_regs.r(si);        \
-            if ( using_di ) _regs.r(di) = (uint32_t)_regs.r(di);        \
+            if ( extend_si ) _regs.r(si) = _regs.esi;                   \
+            if ( extend_di ) _regs.r(di) = _regs.edi;                   \
         }                                                               \
         goto complete_insn;                                             \
     }                                                                   \
@@ -1818,7 +1818,7 @@ x86_emulate(
         dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
         if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
             goto done;
-        nr_reps = get_rep_prefix(false, true);
+        nr_reps = get_rep_prefix(false, false /* don't extend RSI/RDI */);
         dst.mem.off = truncate_ea_and_reps(_regs.r(di), nr_reps, dst.bytes);
         dst.mem.seg = x86_seg_es;
         /* Try the presumably most efficient approach first. */
@@ -1860,7 +1860,7 @@ x86_emulate(
         dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
         if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
             goto done;
-        nr_reps = get_rep_prefix(true, false);
+        nr_reps = get_rep_prefix(false, false /* don't extend RSI/RDI */);
         ea.mem.off = truncate_ea_and_reps(_regs.r(si), nr_reps, dst.bytes);
         /* Try the presumably most efficient approach first. */
         if ( !ops->rep_outs )
@@ -2198,7 +2198,7 @@ x86_emulate(
     case 0xa6 ... 0xa7: /* cmps */ {
         unsigned long next_eip = _regs.r(ip);
 
-        get_rep_prefix(true, true);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
         if ( (rc = read_ulong(ea.mem.seg, truncate_ea(_regs.r(si)),
                               &dst.val, dst.bytes, ctxt, ops)) ||
@@ -2240,7 +2240,7 @@ x86_emulate(
     }
 
     case 0xac ... 0xad: /* lods */
-        get_rep_prefix(true, false);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         if ( (rc = read_ulong(ea.mem.seg, truncate_ea(_regs.r(si)),
                               &dst.val, dst.bytes, ctxt, ops)) != 0 )
             goto done;
@@ -2251,7 +2251,7 @@ x86_emulate(
     case 0xae ... 0xaf: /* scas */ {
         unsigned long next_eip = _regs.r(ip);
 
-        get_rep_prefix(false, true);
+        get_rep_prefix(false, false /* don't extend RSI/RDI */);
         if ( (rc = read_ulong(x86_seg_es, truncate_ea(_regs.r(di)),
                               &dst.val, src.bytes, ctxt, ops)) != 0 )
             goto done;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/PV: further harden guest memory accesses against speculative abuse
Message-Id: <E1tcT9g-006hby-0v@xenbits.xenproject.org>
Date: Mon, 27 Jan 2025 17:44:12 +0000

commit 8306d773b03acec6062c0547ac05e3dd4a6960f6
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon Jan 27 15:23:59 2025 +0100
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon Jan 27 15:23:59 2025 +0100

    x86/PV: further harden guest memory accesses against speculative abuse
    
    The original implementation has two issues: For one it doesn't preserve
    non-canonical-ness of inputs in the range 0x8000000000000000 through
    0x80007fffffffffff. Bogus guest pointers in that range would not cause a
    (#GP) fault upon access, when they should.
    
    And then there is an AMD-specific aspect, where only the low 48 bits of
    an address are used for speculative execution; the architecturally
    mandated #GP for non-canonical addresses would be raised at a later
    execution stage. Therefore to prevent Xen controlled data to make it
    into any of the caches in a guest controllable manner, we need to
    additionally ensure that for non-canonical inputs bit 47 would be clear.
    
    See the code comment for how addressing both is being achieved.
    
    Fixes: 4dc181599142 ("x86/PV: harden guest memory accesses against speculative abuse")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/include/asm/asm-defns.h | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
index d55dd3bbc3..32d6b44910 100644
--- a/xen/arch/x86/include/asm/asm-defns.h
+++ b/xen/arch/x86/include/asm/asm-defns.h
@@ -1,3 +1,5 @@
+#include <asm/page-bits.h>
+
 #ifndef HAVE_AS_CLAC_STAC
 .macro clac
     .byte 0x0f, 0x01, 0xca
@@ -65,17 +67,36 @@
 .macro guest_access_mask_ptr ptr:req, scratch1:req, scratch2:req
 #if defined(CONFIG_SPECULATIVE_HARDEN_GUEST_ACCESS)
     /*
-     * Here we want
-     *
-     * ptr &= ~0ull >> (ptr < HYPERVISOR_VIRT_END);
-     *
+     * Here we want to adjust \ptr such that
+     * - if it's within Xen range, it becomes non-canonical,
+     * - otherwise if it's (non-)canonical on input, it retains that property,
+     * - if the result is non-canonical, bit 47 is clear (to avoid
+     *   potentially populating the cache with Xen data on AMD-like hardware),
      * but guaranteed without any conditional branches (hence in assembly).
+     *
+     * To achieve this we determine which bit to forcibly clear: Either bit 47
+     * (in case the address is below HYPERVISOR_VIRT_END) or bit 63.  Further
+     * we determine whether for forcably set bit 63: In case we first cleared
+     * it, we'll merely restore the original address.  In case we ended up
+     * clearing bit 47 (i.e. the address was either non-canonical or within Xen
+     * range), setting the bit will yield a guaranteed non-canonical address.
+     * If we didn't clear a bit, we also won't set one: The address was in the
+     * low half of address space in that case with bit 47 already clear.  The
+     * address can thus be left unchanged, whether canonical or not.
      */
     mov $(HYPERVISOR_VIRT_END - 1), \scratch1
-    mov $~0, \scratch2
+    mov $(VADDR_BITS - 1), \scratch2
     cmp \ptr, \scratch1
+    /*
+     * Not needed: The value we have in \scratch1 will be truncated to 6 bits,
+     * thus yielding the value we need.
+    mov $63, \scratch1
+     */
+    cmovnb \scratch2, \scratch1
+    xor \scratch2, \scratch2
+    btr \scratch1, \ptr
     rcr $1, \scratch2
-    and \scratch2, \ptr
+    or \scratch2, \ptr
 #elif defined(CONFIG_DEBUG) && defined(CONFIG_PV)
     xor $~\@, \scratch1
     xor $~\@, \scratch2
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/intel: Fix PERF_GLOBAL fixup when virtualised
Message-Id: <E1tcjfQ-007oGu-2u@xenbits.xenproject.org>
Date: Tue, 28 Jan 2025 11:22:04 +0000

commit dd05d265b8abda4cc7206b29cd71b77fb46658bf
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 16:56:26 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 28 11:19:45 2025 +0000

    x86/intel: Fix PERF_GLOBAL fixup when virtualised
    
    Logic using performance counters needs to look at
    MSR_MISC_ENABLE.PERF_AVAILABLE before touching any other resources.
    
    When virtualised under ESX, Xen dies with a #GP fault trying to read
    MSR_CORE_PERF_GLOBAL_CTRL.
    
    Factor this logic out into a separate function (it's already too squashed to
    the RHS), and insert a check of MSR_MISC_ENABLE.PERF_AVAILABLE.
    
    This also avoids setting X86_FEATURE_ARCH_PERFMON if MSR_MISC_ENABLE says that
    PERF is unavailable, although oprofile (the only consumer of this flag)
    cross-checks too.
    
    Fixes: 6bdb965178bb ("x86/intel: ensure Global Performance Counter Control is setup correctly")
    Reported-by: Jonathan Katz <jonathan.katz@aptar.com>
    Link: https://xcp-ng.org/forum/topic/10286/nesting-xcp-ng-on-esx-8
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Tested-by: Jonathan Katz <jonathan.katz@aptar.com>
---
 xen/arch/x86/cpu/intel.c | 64 ++++++++++++++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 27 deletions(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 6a7347968b..6a680ba38d 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -535,39 +535,49 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
     printk("%u MHz\n", (factor * max_ratio + 50) / 100);
 }
 
+static void init_intel_perf(struct cpuinfo_x86 *c)
+{
+    uint64_t val;
+    unsigned int eax, ver, nr_cnt;
+
+    if ( c->cpuid_level <= 9 ||
+         ({  rdmsrl(MSR_IA32_MISC_ENABLE, val);
+             !(val & MSR_IA32_MISC_ENABLE_PERF_AVAIL); }) )
+        return;
+
+    eax = cpuid_eax(10);
+    ver = eax & 0xff;
+    nr_cnt = (eax >> 8) & 0xff;
+
+    if ( ver && nr_cnt > 1 && nr_cnt <= 32 )
+    {
+        unsigned int cnt_mask = (1UL << nr_cnt) - 1;
+
+        /*
+         * On (some?) Sapphire/Emerald Rapids platforms each package-BSP
+         * starts with all the enable bits for the general-purpose PMCs
+         * cleared.  Adjust so counters can be enabled from EVNTSEL.
+         */
+        rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val);
+
+        if ( (val & cnt_mask) != cnt_mask )
+        {
+            printk("FIRMWARE BUG: CPU%u invalid PERF_GLOBAL_CTRL: %#"PRIx64" adjusting to %#"PRIx64"\n",
+                   smp_processor_id(), val, val | cnt_mask);
+            wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val | cnt_mask);
+        }
+
+        __set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+    }
+}
+
 static void cf_check init_intel(struct cpuinfo_x86 *c)
 {
 	/* Detect the extended topology information if available */
 	detect_extended_topology(c);
 
 	init_intel_cacheinfo(c);
-	if (c->cpuid_level > 9) {
-		unsigned eax = cpuid_eax(10);
-		unsigned int cnt = (eax >> 8) & 0xff;
-
-		/* Check for version and the number of counters */
-		if ((eax & 0xff) && (cnt > 1) && (cnt <= 32)) {
-			uint64_t global_ctrl;
-			unsigned int cnt_mask = (1UL << cnt) - 1;
-
-			/*
-			 * On (some?) Sapphire/Emerald Rapids platforms each
-			 * package-BSP starts with all the enable bits for the
-			 * general-purpose PMCs cleared.  Adjust so counters
-			 * can be enabled from EVNTSEL.
-			 */
-			rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl);
-			if ((global_ctrl & cnt_mask) != cnt_mask) {
-				printk("CPU%u: invalid PERF_GLOBAL_CTRL: %#"
-				       PRIx64 " adjusting to %#" PRIx64 "\n",
-				       smp_processor_id(), global_ctrl,
-				       global_ctrl | cnt_mask);
-				wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
-				       global_ctrl | cnt_mask);
-			}
-			__set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
-		}
-	}
+	init_intel_perf(c);
 
 	if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
 	{
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/intel: Fix PERF_GLOBAL fixup when virtualised
Message-Id: <E1tckm5-007tu8-25@xenbits.xenproject.org>
Date: Tue, 28 Jan 2025 12:33:01 +0000

commit dd05d265b8abda4cc7206b29cd71b77fb46658bf
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Jan 21 16:56:26 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue Jan 28 11:19:45 2025 +0000

    x86/intel: Fix PERF_GLOBAL fixup when virtualised
    
    Logic using performance counters needs to look at
    MSR_MISC_ENABLE.PERF_AVAILABLE before touching any other resources.
    
    When virtualised under ESX, Xen dies with a #GP fault trying to read
    MSR_CORE_PERF_GLOBAL_CTRL.
    
    Factor this logic out into a separate function (it's already too squashed to
    the RHS), and insert a check of MSR_MISC_ENABLE.PERF_AVAILABLE.
    
    This also avoids setting X86_FEATURE_ARCH_PERFMON if MSR_MISC_ENABLE says that
    PERF is unavailable, although oprofile (the only consumer of this flag)
    cross-checks too.
    
    Fixes: 6bdb965178bb ("x86/intel: ensure Global Performance Counter Control is setup correctly")
    Reported-by: Jonathan Katz <jonathan.katz@aptar.com>
    Link: https://xcp-ng.org/forum/topic/10286/nesting-xcp-ng-on-esx-8
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    Tested-by: Jonathan Katz <jonathan.katz@aptar.com>
---
 xen/arch/x86/cpu/intel.c | 64 ++++++++++++++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 27 deletions(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 6a7347968b..6a680ba38d 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -535,39 +535,49 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
     printk("%u MHz\n", (factor * max_ratio + 50) / 100);
 }
 
+static void init_intel_perf(struct cpuinfo_x86 *c)
+{
+    uint64_t val;
+    unsigned int eax, ver, nr_cnt;
+
+    if ( c->cpuid_level <= 9 ||
+         ({  rdmsrl(MSR_IA32_MISC_ENABLE, val);
+             !(val & MSR_IA32_MISC_ENABLE_PERF_AVAIL); }) )
+        return;
+
+    eax = cpuid_eax(10);
+    ver = eax & 0xff;
+    nr_cnt = (eax >> 8) & 0xff;
+
+    if ( ver && nr_cnt > 1 && nr_cnt <= 32 )
+    {
+        unsigned int cnt_mask = (1UL << nr_cnt) - 1;
+
+        /*
+         * On (some?) Sapphire/Emerald Rapids platforms each package-BSP
+         * starts with all the enable bits for the general-purpose PMCs
+         * cleared.  Adjust so counters can be enabled from EVNTSEL.
+         */
+        rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val);
+
+        if ( (val & cnt_mask) != cnt_mask )
+        {
+            printk("FIRMWARE BUG: CPU%u invalid PERF_GLOBAL_CTRL: %#"PRIx64" adjusting to %#"PRIx64"\n",
+                   smp_processor_id(), val, val | cnt_mask);
+            wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val | cnt_mask);
+        }
+
+        __set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+    }
+}
+
 static void cf_check init_intel(struct cpuinfo_x86 *c)
 {
 	/* Detect the extended topology information if available */
 	detect_extended_topology(c);
 
 	init_intel_cacheinfo(c);
-	if (c->cpuid_level > 9) {
-		unsigned eax = cpuid_eax(10);
-		unsigned int cnt = (eax >> 8) & 0xff;
-
-		/* Check for version and the number of counters */
-		if ((eax & 0xff) && (cnt > 1) && (cnt <= 32)) {
-			uint64_t global_ctrl;
-			unsigned int cnt_mask = (1UL << cnt) - 1;
-
-			/*
-			 * On (some?) Sapphire/Emerald Rapids platforms each
-			 * package-BSP starts with all the enable bits for the
-			 * general-purpose PMCs cleared.  Adjust so counters
-			 * can be enabled from EVNTSEL.
-			 */
-			rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl);
-			if ((global_ctrl & cnt_mask) != cnt_mask) {
-				printk("CPU%u: invalid PERF_GLOBAL_CTRL: %#"
-				       PRIx64 " adjusting to %#" PRIx64 "\n",
-				       smp_processor_id(), global_ctrl,
-				       global_ctrl | cnt_mask);
-				wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
-				       global_ctrl | cnt_mask);
-			}
-			__set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
-		}
-	}
+	init_intel_perf(c);
 
 	if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
 	{
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
Message-Id: <E1td2kB-009qs0-12@xenbits.xenproject.org>
Date: Wed, 29 Jan 2025 07:44:15 +0000

commit 45c65669bf34bfad9ff6de0dabae2cb201239e34
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 28 10:40:02 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 29 08:34:43 2025 +0100

    xen/arm: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
    
    On Arm32, when CONFIG_PHYS_ADDR_T_32 is set, a build failure is observed:
    arch/arm/platforms/vexpress.c: In function 'vexpress_smp_init':
    arch/arm/platforms/vexpress.c:102:12: error: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'long long unsigned int' [-Werror=format=]
      102 |     printk("Set SYS_FLAGS to %"PRIpaddr" (%p)\n",
    
    When CONFIG_PHYS_ADDR_T_32 is set, paddr_t is defined as unsigned long.
    Commit 96f35de69e59 dropped __virt_to_maddr() which used paddr_t as a
    return type. Without a cast, the expression type is unsigned long long
    which causes the issue. Fix it.
    
    Fixes: 96f35de69e59 ("x86+Arm: drop (rename) __virt_to_maddr() / __maddr_to_virt()")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/include/asm/mm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index f91ff088f6..a0d8e5afe9 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -263,7 +263,7 @@ static inline void __iomem *ioremap_wc(paddr_t start, size_t len)
 
 #define virt_to_maddr(va) ({                                        \
     vaddr_t va_ = (vaddr_t)(va);                                    \
-    (va_to_par(va_) & PADDR_MASK & PAGE_MASK) | (va_ & ~PAGE_MASK); \
+    (paddr_t)((va_to_par(va_) & PADDR_MASK & PAGE_MASK) | (va_ & ~PAGE_MASK)); \
 })
 
 #ifdef CONFIG_ARM_32
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] device-tree: bootfdt: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
Message-Id: <E1td2k1-009qrV-0U@xenbits.xenproject.org>
Date: Wed, 29 Jan 2025 07:44:05 +0000

commit d59699e63d239ffde4fb9364b2e8dd20b7acd1ac
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 28 10:40:01 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 29 08:34:33 2025 +0100

    device-tree: bootfdt: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
    
    On Arm32, when CONFIG_PHYS_ADDR_T_32 is set, a build failure is observed:
    common/device-tree/bootfdt.c: In function 'build_assertions':
    ./include/xen/macros.h:47:31: error: static assertion failed: "!(alignof(struct membanks) != 8)"
       47 | #define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); })
          |                               ^~~~~~~~~~~~~~
    common/device-tree/bootfdt.c:31:5: note: in expansion of macro 'BUILD_BUG_ON'
       31 |     BUILD_BUG_ON(alignof(struct membanks) != 8);
    
    When CONFIG_PHYS_ADDR_T_32 is set, paddr_t is defined as unsigned long,
    therefore the struct membanks alignment is 4B and not 8B. The check is
    there to ensure the struct membanks and struct membank, which is a
    member of the former, are equally aligned. Therefore modify the check to
    compare alignments obtained via alignof not to rely on hardcoded
    values.
    
    Fixes: 2209c1e35b47 ("xen/arm: Introduce a generic way to access memory bank structures")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Julien Grall <julien@xen.org>
---
 xen/common/device-tree/bootfdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/common/device-tree/bootfdt.c b/xen/common/device-tree/bootfdt.c
index 47386d4fff..529c91e603 100644
--- a/xen/common/device-tree/bootfdt.c
+++ b/xen/common/device-tree/bootfdt.c
@@ -27,8 +27,8 @@ static void __init __maybe_unused build_assertions(void)
      */
     BUILD_BUG_ON((offsetof(struct membanks, bank) !=
                  offsetof(struct meminfo, bank)));
-    /* Ensure "struct membanks" is 8-byte aligned */
-    BUILD_BUG_ON(alignof(struct membanks) != 8);
+    /* Ensure "struct membanks" and "struct membank" are equally aligned */
+    BUILD_BUG_ON(alignof(struct membanks) != alignof(struct membank));
 }
 
 static bool __init device_tree_node_is_available(const void *fdt, int node)
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] device-tree: bootfdt: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
Message-Id: <E1td3Kk-009xoz-0R@xenbits.xenproject.org>
Date: Wed, 29 Jan 2025 08:22:02 +0000

commit d59699e63d239ffde4fb9364b2e8dd20b7acd1ac
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 28 10:40:01 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 29 08:34:33 2025 +0100

    device-tree: bootfdt: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
    
    On Arm32, when CONFIG_PHYS_ADDR_T_32 is set, a build failure is observed:
    common/device-tree/bootfdt.c: In function 'build_assertions':
    ./include/xen/macros.h:47:31: error: static assertion failed: "!(alignof(struct membanks) != 8)"
       47 | #define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); })
          |                               ^~~~~~~~~~~~~~
    common/device-tree/bootfdt.c:31:5: note: in expansion of macro 'BUILD_BUG_ON'
       31 |     BUILD_BUG_ON(alignof(struct membanks) != 8);
    
    When CONFIG_PHYS_ADDR_T_32 is set, paddr_t is defined as unsigned long,
    therefore the struct membanks alignment is 4B and not 8B. The check is
    there to ensure the struct membanks and struct membank, which is a
    member of the former, are equally aligned. Therefore modify the check to
    compare alignments obtained via alignof not to rely on hardcoded
    values.
    
    Fixes: 2209c1e35b47 ("xen/arm: Introduce a generic way to access memory bank structures")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Julien Grall <julien@xen.org>
---
 xen/common/device-tree/bootfdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/common/device-tree/bootfdt.c b/xen/common/device-tree/bootfdt.c
index 47386d4fff..529c91e603 100644
--- a/xen/common/device-tree/bootfdt.c
+++ b/xen/common/device-tree/bootfdt.c
@@ -27,8 +27,8 @@ static void __init __maybe_unused build_assertions(void)
      */
     BUILD_BUG_ON((offsetof(struct membanks, bank) !=
                  offsetof(struct meminfo, bank)));
-    /* Ensure "struct membanks" is 8-byte aligned */
-    BUILD_BUG_ON(alignof(struct membanks) != 8);
+    /* Ensure "struct membanks" and "struct membank" are equally aligned */
+    BUILD_BUG_ON(alignof(struct membanks) != alignof(struct membank));
 }
 
 static bool __init device_tree_node_is_available(const void *fdt, int node)
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
Message-Id: <E1td3Ku-009xpf-0o@xenbits.xenproject.org>
Date: Wed, 29 Jan 2025 08:22:12 +0000

commit 45c65669bf34bfad9ff6de0dabae2cb201239e34
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue Jan 28 10:40:02 2025 +0100
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Wed Jan 29 08:34:43 2025 +0100

    xen/arm: Fix build issue when CONFIG_PHYS_ADDR_T_32=y
    
    On Arm32, when CONFIG_PHYS_ADDR_T_32 is set, a build failure is observed:
    arch/arm/platforms/vexpress.c: In function 'vexpress_smp_init':
    arch/arm/platforms/vexpress.c:102:12: error: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'long long unsigned int' [-Werror=format=]
      102 |     printk("Set SYS_FLAGS to %"PRIpaddr" (%p)\n",
    
    When CONFIG_PHYS_ADDR_T_32 is set, paddr_t is defined as unsigned long.
    Commit 96f35de69e59 dropped __virt_to_maddr() which used paddr_t as a
    return type. Without a cast, the expression type is unsigned long long
    which causes the issue. Fix it.
    
    Fixes: 96f35de69e59 ("x86+Arm: drop (rename) __virt_to_maddr() / __maddr_to_virt()")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/include/asm/mm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index f91ff088f6..a0d8e5afe9 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -263,7 +263,7 @@ static inline void __iomem *ioremap_wc(paddr_t start, size_t len)
 
 #define virt_to_maddr(va) ({                                        \
     vaddr_t va_ = (vaddr_t)(va);                                    \
-    (va_to_par(va_) & PADDR_MASK & PAGE_MASK) | (va_ & ~PAGE_MASK); \
+    (paddr_t)((va_to_par(va_) & PADDR_MASK & PAGE_MASK) | (va_ & ~PAGE_MASK)); \
 })
 
 #ifdef CONFIG_ARM_32
--
generated by git-patchbot for /home/xen/git/xen.git#master


