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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/pdx: Undef the correct macro
Message-Id: <E1wImhy-00AUln-0C@xenbits.xenproject.org>
Date: Fri, 01 May 2026 12:11:02 +0000

commit 9e13c0ca186c073f17f0f055658c7d33b3ea6877
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 09:37:30 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    x86/pdx: Undef the correct macro
    
    This was caused by a rename during review.
    
    No functional change.
    
    Reported-by: Luca Fancellu <luca.fancellu@arm.com>
    Fixes: bd0b3a876d80 ("pdx: allow per-arch optimization of PDX conversion helpers")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
---
 xen/arch/x86/include/asm/pdx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/pdx.h b/xen/arch/x86/include/asm/pdx.h
index 6be7e1185e..6c10234ecf 100644
--- a/xen/arch/x86/include/asm/pdx.h
+++ b/xen/arch/x86/include/asm/pdx.h
@@ -57,7 +57,7 @@ static inline paddr_t directmapoff_to_maddr(unsigned long offset)
     return offset;
 }
 
-#undef PDX_ASM_GOTO_SKIP
+#undef PDX_ASM_GOTO
 
 #endif /* X86_PDX_H */
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/cpu: identify uninitialized CPU data using BAD_APICID
Message-Id: <E1wImi8-00AUmo-0j@xenbits.xenproject.org>
Date: Fri, 01 May 2026 12:11:12 +0000

commit cd0413bfacf262b258029cbccbeadf99a7fef2b4
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Apr 30 13:46:47 2026 +0200
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    x86/cpu: identify uninitialized CPU data using BAD_APICID
    
    Uninitialized cpu_data[] entries have the apicid field set to BAD_APICID,
    not boot_cpu_data.apicid.  Fix the check in cpu_smpboot_free() to use the
    correct condition.
    
    Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]")
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/smpboot.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 491cbbba33..ff05955bae 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -961,8 +961,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool remove)
      * In that case the socket number cannot be relied upon, but the respective
      * socket_cpumask[] slot also wouldn't have been set.
      */
-    if ( c[cpu].apicid != boot_cpu_data.apicid &&
-         cpumask_empty(socket_cpumask[socket]) )
+    if ( c[cpu].apicid != BAD_APICID && cpumask_empty(socket_cpumask[socket]) )
     {
         xfree(socket_cpumask[socket]);
         socket_cpumask[socket] = NULL;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: use --platform on `docker build` and `push`
Message-Id: <E1wImiI-00AUoW-13@xenbits.xenproject.org>
Date: Fri, 01 May 2026 12:11:22 +0000

commit 61f957d48c78df6c5254b6f54d6170d3bd3d717e
Author:     Anthony PERARD <anthony.perard@vates.tech>
AuthorDate: Wed Apr 29 14:48:01 2026 +0200
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    CI: use --platform on `docker build` and `push`
    
    Without --platform, it seems recent versions of docker ignores the
    platform of the image when pushing, and it's pushed as the platform of
    the runner.
    
    If we happen to build an arm64 image on x86, with recent version of
    docker, the image will be push as if it was an x86 image, then
    `docker run --platform=linux/arm64 ...` fails. Even if it would
    work without --platform, gitlab-runner will not be able to use the
    image.
    
    To go back to the previous behavior, we will extract --platform from
    the dockerfiles, and use it on the command line.
    
    --platform= is needed on both docker-build and docker-push. The first
    one so that the image is tagged with the right platform, and the
    second one so that we can push a "generic" image without been tagged
    to a particular platform. --platform on docker-push allow to easly use
    the container on any arch, without having to use --platform on
    docker-pull or docker-run.
    
    `docker push --platform` seem to have been added to 1.46, according to
    the [doc], and doesn't exist on Podman. So we need to check that we
    are using `docker` and that the API version is new enough.
    
    [doc] https://docs.docker.com/reference/cli/docker/image/push/
    
    Also, introduce the $img variable, to make the lines a bit shorter.
    
    Signed-off-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 automation/build/Makefile | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/automation/build/Makefile b/automation/build/Makefile
index fedf7524da..d578cd3476 100644
--- a/automation/build/Makefile
+++ b/automation/build/Makefile
@@ -15,10 +15,28 @@ help:
 
 include yocto/yocto.inc
 
+# Find out if we are running Podman, if not is likely docker.
+is-docker = $(if $(filter Podman,$(shell $(DOCKER_CMD) version)),,1)
+
+# Find out the docker API version is at least 1.46. We exploit `sort -V` to
+# compare the versions at it can sort by version.
+docker-api-version = $(shell $(DOCKER_CMD) version -f '{{.Client.APIVersion}}')
+docker-min-version = $(firstword $(shell printf "1.46\n$(docker-api-version)" | sort -V))
+docker-have-push-platform = $(if $(filter 1.46,$(docker-min-version)),1)
+
+# check if we can use `X push --platform`.
+# `podman push` doesn't support --platform.
+# `docker` only have it on recent version.
+builder-have-push-platform = $(and $(is-docker),$(docker-have-push-platform))
+
 %: %.dockerfile ## Builds containers
-	$(DOCKER_CMD) build --pull -t $(REGISTRY)/$(@D):$(@F) -f $< $(<D)
-	@if [ ! -z $${PUSH+x} ]; then \
-		$(DOCKER_CMD) push $(REGISTRY)/$(@D):$(@F); \
+	set -xe; \
+	$(if $(builder-have-push-platform), \
+	    platform=$$(sed -n '/^FROM/{s/.*\(--platform=[^ ]*\) .*/\1/p;q}' $<); ) \
+	img="$(REGISTRY)/$(@D):$(@F)"; \
+	$(DOCKER_CMD) build --pull $$platform -t $$img -f $< $(<D); \
+	if [ ! -z $${PUSH+x} ]; then \
+		$(DOCKER_CMD) push $$platform $$img; \
 	fi
 
 .PHONY: all clean
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/cpu: identify uninitialized CPU data using BAD_APICID
Message-Id: <E1wJOLM-00CsSk-0u@xenbits.xenproject.org>
Date: Sun, 03 May 2026 04:22:12 +0000

commit cd0413bfacf262b258029cbccbeadf99a7fef2b4
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Apr 30 13:46:47 2026 +0200
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    x86/cpu: identify uninitialized CPU data using BAD_APICID
    
    Uninitialized cpu_data[] entries have the apicid field set to BAD_APICID,
    not boot_cpu_data.apicid.  Fix the check in cpu_smpboot_free() to use the
    correct condition.
    
    Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]")
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/smpboot.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 491cbbba33..ff05955bae 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -961,8 +961,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool remove)
      * In that case the socket number cannot be relied upon, but the respective
      * socket_cpumask[] slot also wouldn't have been set.
      */
-    if ( c[cpu].apicid != boot_cpu_data.apicid &&
-         cpumask_empty(socket_cpumask[socket]) )
+    if ( c[cpu].apicid != BAD_APICID && cpumask_empty(socket_cpumask[socket]) )
     {
         xfree(socket_cpumask[socket]);
         socket_cpumask[socket] = NULL;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/pdx: Undef the correct macro
Message-Id: <E1wJOLC-00CsR1-0L@xenbits.xenproject.org>
Date: Sun, 03 May 2026 04:22:02 +0000

commit 9e13c0ca186c073f17f0f055658c7d33b3ea6877
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 09:37:30 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    x86/pdx: Undef the correct macro
    
    This was caused by a rename during review.
    
    No functional change.
    
    Reported-by: Luca Fancellu <luca.fancellu@arm.com>
    Fixes: bd0b3a876d80 ("pdx: allow per-arch optimization of PDX conversion helpers")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
---
 xen/arch/x86/include/asm/pdx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/pdx.h b/xen/arch/x86/include/asm/pdx.h
index 6be7e1185e..6c10234ecf 100644
--- a/xen/arch/x86/include/asm/pdx.h
+++ b/xen/arch/x86/include/asm/pdx.h
@@ -57,7 +57,7 @@ static inline paddr_t directmapoff_to_maddr(unsigned long offset)
     return offset;
 }
 
-#undef PDX_ASM_GOTO_SKIP
+#undef PDX_ASM_GOTO
 
 #endif /* X86_PDX_H */
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: use --platform on `docker build` and `push`
Message-Id: <E1wJOLW-00CsVM-1V@xenbits.xenproject.org>
Date: Sun, 03 May 2026 04:22:22 +0000

commit 61f957d48c78df6c5254b6f54d6170d3bd3d717e
Author:     Anthony PERARD <anthony.perard@vates.tech>
AuthorDate: Wed Apr 29 14:48:01 2026 +0200
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Fri May 1 10:51:19 2026 +0100

    CI: use --platform on `docker build` and `push`
    
    Without --platform, it seems recent versions of docker ignores the
    platform of the image when pushing, and it's pushed as the platform of
    the runner.
    
    If we happen to build an arm64 image on x86, with recent version of
    docker, the image will be push as if it was an x86 image, then
    `docker run --platform=linux/arm64 ...` fails. Even if it would
    work without --platform, gitlab-runner will not be able to use the
    image.
    
    To go back to the previous behavior, we will extract --platform from
    the dockerfiles, and use it on the command line.
    
    --platform= is needed on both docker-build and docker-push. The first
    one so that the image is tagged with the right platform, and the
    second one so that we can push a "generic" image without been tagged
    to a particular platform. --platform on docker-push allow to easly use
    the container on any arch, without having to use --platform on
    docker-pull or docker-run.
    
    `docker push --platform` seem to have been added to 1.46, according to
    the [doc], and doesn't exist on Podman. So we need to check that we
    are using `docker` and that the API version is new enough.
    
    [doc] https://docs.docker.com/reference/cli/docker/image/push/
    
    Also, introduce the $img variable, to make the lines a bit shorter.
    
    Signed-off-by: Anthony PERARD <anthony.perard@vates.tech>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 automation/build/Makefile | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/automation/build/Makefile b/automation/build/Makefile
index fedf7524da..d578cd3476 100644
--- a/automation/build/Makefile
+++ b/automation/build/Makefile
@@ -15,10 +15,28 @@ help:
 
 include yocto/yocto.inc
 
+# Find out if we are running Podman, if not is likely docker.
+is-docker = $(if $(filter Podman,$(shell $(DOCKER_CMD) version)),,1)
+
+# Find out the docker API version is at least 1.46. We exploit `sort -V` to
+# compare the versions at it can sort by version.
+docker-api-version = $(shell $(DOCKER_CMD) version -f '{{.Client.APIVersion}}')
+docker-min-version = $(firstword $(shell printf "1.46\n$(docker-api-version)" | sort -V))
+docker-have-push-platform = $(if $(filter 1.46,$(docker-min-version)),1)
+
+# check if we can use `X push --platform`.
+# `podman push` doesn't support --platform.
+# `docker` only have it on recent version.
+builder-have-push-platform = $(and $(is-docker),$(docker-have-push-platform))
+
 %: %.dockerfile ## Builds containers
-	$(DOCKER_CMD) build --pull -t $(REGISTRY)/$(@D):$(@F) -f $< $(<D)
-	@if [ ! -z $${PUSH+x} ]; then \
-		$(DOCKER_CMD) push $(REGISTRY)/$(@D):$(@F); \
+	set -xe; \
+	$(if $(builder-have-push-platform), \
+	    platform=$$(sed -n '/^FROM/{s/.*\(--platform=[^ ]*\) .*/\1/p;q}' $<); ) \
+	img="$(REGISTRY)/$(@D):$(@F)"; \
+	$(DOCKER_CMD) build --pull $$platform -t $$img -f $< $(<D); \
+	if [ ! -z $${PUSH+x} ]; then \
+		$(DOCKER_CMD) push $$platform $$img; \
 	fi
 
 .PHONY: all clean
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown
Message-Id: <E1wJojd-00ELWb-30@xenbits.xenproject.org>
Date: Mon, 04 May 2026 08:33:01 +0000

commit 6f00fd9d6c1d6f08ab21f16c0406b3bb2c1e3b01
Author:     Mykola Kvach <mykola_kvach@epam.com>
AuthorDate: Tue Apr 28 14:57:55 2026 +0300
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Mon May 4 10:20:00 2026 +0200

    xen/arm: gic-v2: disable interrupt bypass on CPU shutdown
    
    The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR.
    
    Per IHI0048B.b section 2.3.1, clearing the architected bypass-disable
    bits selects bypass rather than deasserted interrupt outputs when the
    CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed
    GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully
    disabling the interface.
    
    Fix this by reading GICC_CTLR, then setting the bypass-disable bits and
    clearing the group-enable bits that are architecturally defined for the
    current GICC_CTLR view before writing the value back. When Security
    Extensions are implemented Xen accesses the Non-secure copy of
    GICC_CTLR, where IRQBypDisGrp1 and FIQBypDisGrp1 are at bits [6:5] and
    bits [8:7] are reserved.
    
    Without Security Extensions (GICD_CTLR.DS=1), GICD_IGROUPR is RAZ/WI
    and all interrupts are Group 0, so clearing EnableGrp0 alone is
    sufficient to stop interrupt delivery through the CPU interface.
    
    Section 2.3.2 also states that wakeup event signals remain available
    even when both GIC interrupt signaling and interrupt bypass are
    disabled, so disabling bypass does not break the power-management use
    case, i.e. suspend modes.
    
    Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown")
    Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
---
 xen/arch/arm/gic-v2.c          | 12 +++++++++++-
 xen/arch/arm/include/asm/gic.h | 25 +++++++++++++++++++++++--
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 014f955967..43a379fdda 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -408,7 +408,17 @@ static void gicv2_cpu_init(void)
 
 static void gicv2_cpu_disable(void)
 {
-    writel_gicc(0x0, GICC_CTLR);
+    uint32_t ctlr = readl_gicc(GICC_CTLR);
+
+    if ( readl_gicd(GICD_TYPER) & GICD_TYPE_SEC )
+        ctlr |= GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK;
+    else
+        ctlr |= GICC_CTLR_BYPASS_DISABLE_GRP0_MASK |
+                GICC_CTLR_BYPASS_DISABLE_GRP1_MASK;
+
+    ctlr &= ~GICC_CTL_ENABLE;
+
+    writel_gicc(ctlr, GICC_CTLR);
 }
 
 static void gicv2_hyp_init(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
index 8e713aa477..ff22dea40d 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -102,8 +102,29 @@
 #define GICD_TYPE_SEC   0x400
 #define GICD_TYPER_DVIS (1U << 18)
 
-#define GICC_CTL_ENABLE 0x1
-#define GICC_CTL_EOI    (0x1 << 9)
+/*
+ * Xen runs in the Non-secure world. When Security Extensions are present,
+ * Xen accesses the Non-secure GICC_CTLR view, where bit[0] is EnableGrp1
+ * and bits[6:5] are the Group 1 bypass-disable bits. Otherwise Xen sees the
+ * common GICC_CTLR layout, where bit[0] is EnableGrp0, bit[1] is EnableGrp1,
+ * bits[6:5] are the Group 0 bypass-disable bits, and bits[8:7] are the
+ * Group 1 bypass-disable bits.
+ */
+#define GICC_CTL_ENABLE        (0x1 << 0)
+#define GICC_CTL_ENABLE_GRP1   (0x1 << 1)
+#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5)
+#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6)
+#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7)
+#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8)
+
+#define GICC_CTLR_BYPASS_DISABLE_GRP0_MASK              \
+    (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0)
+#define GICC_CTLR_BYPASS_DISABLE_GRP1_MASK              \
+    (GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1)
+#define GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK           \
+    GICC_CTLR_BYPASS_DISABLE_GRP0_MASK
+
+#define GICC_CTL_EOI           (0x1 << 9)
 
 #define GICC_IA_IRQ       0x03ff
 #define GICC_IA_CPU_MASK  0x1c00
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments
Message-Id: <E1wJojo-00ELXC-09@xenbits.xenproject.org>
Date: Mon, 04 May 2026 08:33:12 +0000

commit f4af571dd70bea97d8de82d7aa39c62c530db897
Author:     Mykola Kvach <mykola_kvach@epam.com>
AuthorDate: Tue Mar 31 21:31:29 2026 +0300
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Mon May 4 10:20:00 2026 +0200

    xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments
    
    SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls
    using Wn, only the least significant 32 bits are significant and the
    upper 32 bits must be ignored by the implementation.
    
    So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the
    argument registers as an error. Instead, they should be discarded when
    decoding the arguments.
    
    Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be
    implementation defined when entering from AArch32. Xen zeros them on
    entry, but that guarantee is only relevant for 32-bit domains.
    
    Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND
    to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64
    handling unchanged.
    
    No functional change is intended for PSCI 0.1.
    
    Suggested-by: Julien Grall <julien@xen.org>
    Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/vpsci.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index bd87ec430d..ac6af6118f 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -305,13 +305,16 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 #define PSCI_ARG32(reg, n) PSCI_ARG(reg, n)
 #endif
 
+#define PSCI_ARG_CONV(reg, n, conv_64) \
+    ((conv_64) ? PSCI_ARG(reg, n) : PSCI_ARG32(reg, n))
+
 /*
  * PSCI 0.1 calls. It will return false if the function ID is not
  * handled.
  */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid)
 {
-    switch ( (uint32_t)get_user_reg(regs, 0) )
+    switch ( fid )
     {
     case PSCI_cpu_off:
     {
@@ -346,6 +349,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
      * adding/removing a function. SSSC_SMCCC_*_REVISION should be
      * updated once per release.
      */
+    bool is_conv_64 = smccc_is_conv_64(fid);
+
     switch ( fid )
     {
     case PSCI_0_2_FN32_PSCI_VERSION:
@@ -378,9 +383,9 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN32_CPU_ON:
     case PSCI_0_2_FN64_CPU_ON:
     {
-        register_t vcpuid = PSCI_ARG(regs, 1);
-        register_t epoint = PSCI_ARG(regs, 2);
-        register_t cid = PSCI_ARG(regs, 3);
+        register_t vcpuid = PSCI_ARG_CONV(regs, 1, is_conv_64);
+        register_t epoint = PSCI_ARG_CONV(regs, 2, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 3, is_conv_64);
 
         perfc_incr(vpsci_cpu_on);
         PSCI_SET_RESULT(regs, do_psci_0_2_cpu_on(vcpuid, epoint, cid));
@@ -391,8 +396,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN64_CPU_SUSPEND:
     {
         uint32_t pstate = PSCI_ARG32(regs, 1);
-        register_t epoint = PSCI_ARG(regs, 2);
-        register_t cid = PSCI_ARG(regs, 3);
+        register_t epoint = PSCI_ARG_CONV(regs, 2, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 3, is_conv_64);
 
         perfc_incr(vpsci_cpu_suspend);
         PSCI_SET_RESULT(regs, do_psci_0_2_cpu_suspend(pstate, epoint, cid));
@@ -402,7 +407,7 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN32_AFFINITY_INFO:
     case PSCI_0_2_FN64_AFFINITY_INFO:
     {
-        register_t taff = PSCI_ARG(regs, 1);
+        register_t taff = PSCI_ARG_CONV(regs, 1, is_conv_64);
         uint32_t laff = PSCI_ARG32(regs, 2);
 
         perfc_incr(vpsci_cpu_affinity_info);
@@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_1_0_FN32_SYSTEM_SUSPEND:
     case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     {
-        register_t epoint = PSCI_ARG(regs, 1);
-        register_t cid = PSCI_ARG(regs, 2);
-
-        if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
-        {
-            epoint &= GENMASK(31, 0);
-            cid &= GENMASK(31, 0);
-        }
+        register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64);
 
         perfc_incr(vpsci_system_suspend);
         PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown
Message-Id: <E1wJpfh-00EOd6-1s@xenbits.xenproject.org>
Date: Mon, 04 May 2026 09:33:01 +0000

commit 6f00fd9d6c1d6f08ab21f16c0406b3bb2c1e3b01
Author:     Mykola Kvach <mykola_kvach@epam.com>
AuthorDate: Tue Apr 28 14:57:55 2026 +0300
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Mon May 4 10:20:00 2026 +0200

    xen/arm: gic-v2: disable interrupt bypass on CPU shutdown
    
    The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR.
    
    Per IHI0048B.b section 2.3.1, clearing the architected bypass-disable
    bits selects bypass rather than deasserted interrupt outputs when the
    CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed
    GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully
    disabling the interface.
    
    Fix this by reading GICC_CTLR, then setting the bypass-disable bits and
    clearing the group-enable bits that are architecturally defined for the
    current GICC_CTLR view before writing the value back. When Security
    Extensions are implemented Xen accesses the Non-secure copy of
    GICC_CTLR, where IRQBypDisGrp1 and FIQBypDisGrp1 are at bits [6:5] and
    bits [8:7] are reserved.
    
    Without Security Extensions (GICD_CTLR.DS=1), GICD_IGROUPR is RAZ/WI
    and all interrupts are Group 0, so clearing EnableGrp0 alone is
    sufficient to stop interrupt delivery through the CPU interface.
    
    Section 2.3.2 also states that wakeup event signals remain available
    even when both GIC interrupt signaling and interrupt bypass are
    disabled, so disabling bypass does not break the power-management use
    case, i.e. suspend modes.
    
    Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown")
    Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
---
 xen/arch/arm/gic-v2.c          | 12 +++++++++++-
 xen/arch/arm/include/asm/gic.h | 25 +++++++++++++++++++++++--
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 014f955967..43a379fdda 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -408,7 +408,17 @@ static void gicv2_cpu_init(void)
 
 static void gicv2_cpu_disable(void)
 {
-    writel_gicc(0x0, GICC_CTLR);
+    uint32_t ctlr = readl_gicc(GICC_CTLR);
+
+    if ( readl_gicd(GICD_TYPER) & GICD_TYPE_SEC )
+        ctlr |= GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK;
+    else
+        ctlr |= GICC_CTLR_BYPASS_DISABLE_GRP0_MASK |
+                GICC_CTLR_BYPASS_DISABLE_GRP1_MASK;
+
+    ctlr &= ~GICC_CTL_ENABLE;
+
+    writel_gicc(ctlr, GICC_CTLR);
 }
 
 static void gicv2_hyp_init(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
index 8e713aa477..ff22dea40d 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -102,8 +102,29 @@
 #define GICD_TYPE_SEC   0x400
 #define GICD_TYPER_DVIS (1U << 18)
 
-#define GICC_CTL_ENABLE 0x1
-#define GICC_CTL_EOI    (0x1 << 9)
+/*
+ * Xen runs in the Non-secure world. When Security Extensions are present,
+ * Xen accesses the Non-secure GICC_CTLR view, where bit[0] is EnableGrp1
+ * and bits[6:5] are the Group 1 bypass-disable bits. Otherwise Xen sees the
+ * common GICC_CTLR layout, where bit[0] is EnableGrp0, bit[1] is EnableGrp1,
+ * bits[6:5] are the Group 0 bypass-disable bits, and bits[8:7] are the
+ * Group 1 bypass-disable bits.
+ */
+#define GICC_CTL_ENABLE        (0x1 << 0)
+#define GICC_CTL_ENABLE_GRP1   (0x1 << 1)
+#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5)
+#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6)
+#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7)
+#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8)
+
+#define GICC_CTLR_BYPASS_DISABLE_GRP0_MASK              \
+    (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0)
+#define GICC_CTLR_BYPASS_DISABLE_GRP1_MASK              \
+    (GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1)
+#define GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK           \
+    GICC_CTLR_BYPASS_DISABLE_GRP0_MASK
+
+#define GICC_CTL_EOI           (0x1 << 9)
 
 #define GICC_IA_IRQ       0x03ff
 #define GICC_IA_CPU_MASK  0x1c00
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments
Message-Id: <E1wJpfr-00EOds-2C@xenbits.xenproject.org>
Date: Mon, 04 May 2026 09:33:11 +0000

commit f4af571dd70bea97d8de82d7aa39c62c530db897
Author:     Mykola Kvach <mykola_kvach@epam.com>
AuthorDate: Tue Mar 31 21:31:29 2026 +0300
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Mon May 4 10:20:00 2026 +0200

    xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments
    
    SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls
    using Wn, only the least significant 32 bits are significant and the
    upper 32 bits must be ignored by the implementation.
    
    So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the
    argument registers as an error. Instead, they should be discarded when
    decoding the arguments.
    
    Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be
    implementation defined when entering from AArch32. Xen zeros them on
    entry, but that guarantee is only relevant for 32-bit domains.
    
    Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND
    to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64
    handling unchanged.
    
    No functional change is intended for PSCI 0.1.
    
    Suggested-by: Julien Grall <julien@xen.org>
    Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/vpsci.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index bd87ec430d..ac6af6118f 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -305,13 +305,16 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 #define PSCI_ARG32(reg, n) PSCI_ARG(reg, n)
 #endif
 
+#define PSCI_ARG_CONV(reg, n, conv_64) \
+    ((conv_64) ? PSCI_ARG(reg, n) : PSCI_ARG32(reg, n))
+
 /*
  * PSCI 0.1 calls. It will return false if the function ID is not
  * handled.
  */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid)
 {
-    switch ( (uint32_t)get_user_reg(regs, 0) )
+    switch ( fid )
     {
     case PSCI_cpu_off:
     {
@@ -346,6 +349,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
      * adding/removing a function. SSSC_SMCCC_*_REVISION should be
      * updated once per release.
      */
+    bool is_conv_64 = smccc_is_conv_64(fid);
+
     switch ( fid )
     {
     case PSCI_0_2_FN32_PSCI_VERSION:
@@ -378,9 +383,9 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN32_CPU_ON:
     case PSCI_0_2_FN64_CPU_ON:
     {
-        register_t vcpuid = PSCI_ARG(regs, 1);
-        register_t epoint = PSCI_ARG(regs, 2);
-        register_t cid = PSCI_ARG(regs, 3);
+        register_t vcpuid = PSCI_ARG_CONV(regs, 1, is_conv_64);
+        register_t epoint = PSCI_ARG_CONV(regs, 2, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 3, is_conv_64);
 
         perfc_incr(vpsci_cpu_on);
         PSCI_SET_RESULT(regs, do_psci_0_2_cpu_on(vcpuid, epoint, cid));
@@ -391,8 +396,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN64_CPU_SUSPEND:
     {
         uint32_t pstate = PSCI_ARG32(regs, 1);
-        register_t epoint = PSCI_ARG(regs, 2);
-        register_t cid = PSCI_ARG(regs, 3);
+        register_t epoint = PSCI_ARG_CONV(regs, 2, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 3, is_conv_64);
 
         perfc_incr(vpsci_cpu_suspend);
         PSCI_SET_RESULT(regs, do_psci_0_2_cpu_suspend(pstate, epoint, cid));
@@ -402,7 +407,7 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_0_2_FN32_AFFINITY_INFO:
     case PSCI_0_2_FN64_AFFINITY_INFO:
     {
-        register_t taff = PSCI_ARG(regs, 1);
+        register_t taff = PSCI_ARG_CONV(regs, 1, is_conv_64);
         uint32_t laff = PSCI_ARG32(regs, 2);
 
         perfc_incr(vpsci_cpu_affinity_info);
@@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
     case PSCI_1_0_FN32_SYSTEM_SUSPEND:
     case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     {
-        register_t epoint = PSCI_ARG(regs, 1);
-        register_t cid = PSCI_ARG(regs, 2);
-
-        if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
-        {
-            epoint &= GENMASK(31, 0);
-            cid &= GENMASK(31, 0);
-        }
+        register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64);
+        register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64);
 
         perfc_incr(vpsci_system_suspend);
         PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/shadow: unlock P2M slightly earlier in shadow_track_dirty_vram()
Message-Id: <E1wKARm-00FYt1-0r@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:02 +0000

commit d367f87cfd7429aa3646e58e764563ce6f361842
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:20:55 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:20:55 2026 +0200

    x86/shadow: unlock P2M slightly earlier in shadow_track_dirty_vram()
    
    There's no need to call vfree() with the lock still held.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/mm/shadow/hvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index 3565c7940d..cf4862cbc9 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -1200,8 +1200,8 @@ int shadow_track_dirty_vram(struct domain *d,
         paging_unlock(d);
         rc = -EFAULT;
     }
-    vfree(dirty_bitmap);
     p2m_unlock(p2m_get_hostp2m(d));
+    vfree(dirty_bitmap);
     return rc;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] Arm: device.c is init-only when OVERLAY_DTB=n
Message-Id: <E1wKARw-00FYuh-1G@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:12 +0000

commit 227a9aae44a31c440f05e66ed0841b21fb99837d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:21:45 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:21:45 2026 +0200

    Arm: device.c is init-only when OVERLAY_DTB=n
    
    Introduce an annotation similar to __hwdom_init and use it througout the
    file. All external callers are either themselves __init or are limited to
    OVERLAY_DTB=y. Adjust the Makefile accordingly to also have string
    literals moved into .init.rodata.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
---
 xen/arch/arm/Makefile        |  2 +-
 xen/arch/arm/device.c        | 33 ++++++++++++++++++---------------
 xen/include/xen/dt-overlay.h |  8 ++++++++
 3 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 69200b2728..982c6c396a 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o
 obj-y += cpuerrata.o
 obj-y += cpufeature.o
 obj-y += decode.o
-obj-y += device.o
+obj-y += $(if $(CONFIG_OVERLAY_DTB),device.o,device.init.o)
 obj-$(CONFIG_IOREQ_SERVER) += dm.o
 obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o
 obj-y += domain.o
diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
index 74b54cad34..7d9644fd8b 100644
--- a/xen/arch/arm/device.c
+++ b/xen/arch/arm/device.c
@@ -9,6 +9,7 @@
  */
 
 #include <xen/device_tree.h>
+#include <xen/dt-overlay.h>
 #include <xen/errno.h>
 #include <xen/iocap.h>
 #include <xen/lib.h>
@@ -16,8 +17,8 @@
 #include <asm/firmware/sci.h>
 #include <asm/setup.h>
 
-int map_irq_to_domain(struct domain *d, unsigned int irq,
-                      bool need_mapping, const char *devname)
+int __overlay_init map_irq_to_domain(struct domain *d, unsigned int irq,
+                                     bool need_mapping, const char *devname)
 {
     int res;
 
@@ -49,8 +50,8 @@ int map_irq_to_domain(struct domain *d, unsigned int irq,
     return 0;
 }
 
-int map_range_to_domain(const struct dt_device_node *dev,
-                        uint64_t addr, uint64_t len, void *data)
+int __overlay_init map_range_to_domain(const struct dt_device_node *dev,
+                                       uint64_t addr, uint64_t len, void *data)
 {
     struct map_range_data *mr_data = data;
     struct domain *d = mr_data->d;
@@ -124,10 +125,10 @@ int map_range_to_domain(const struct dt_device_node *dev,
  *   < 0 error
  *   0   success
  */
-int map_device_irqs_to_domain(struct domain *d,
-                              struct dt_device_node *dev,
-                              bool need_mapping,
-                              struct rangeset *irq_ranges)
+int __overlay_init map_device_irqs_to_domain(struct domain *d,
+                                             struct dt_device_node *dev,
+                                             bool need_mapping,
+                                             struct rangeset *irq_ranges)
 {
     unsigned int i, nirq;
     int res, irq;
@@ -180,9 +181,9 @@ int map_device_irqs_to_domain(struct domain *d,
     return 0;
 }
 
-static int map_dt_irq_to_domain(const struct dt_device_node *dev,
-                                const struct dt_irq *dt_irq,
-                                void *data)
+static int __overlay_init map_dt_irq_to_domain(const struct dt_device_node *dev,
+                                               const struct dt_irq *dt_irq,
+                                               void *data)
 {
     struct map_range_data *mr_data = data;
     struct domain *d = mr_data->d;
@@ -219,8 +220,8 @@ static int map_dt_irq_to_domain(const struct dt_device_node *dev,
  * then we may need to perform additional mappings in order to make
  * the child resources available to domain 0.
  */
-static int map_device_children(const struct dt_device_node *dev,
-                               struct map_range_data *mr_data)
+static int __overlay_init map_device_children(const struct dt_device_node *dev,
+                                              struct map_range_data *mr_data)
 {
     if ( dt_device_type_is_equal(dev, "pci") )
     {
@@ -250,8 +251,10 @@ static int map_device_children(const struct dt_device_node *dev,
  *  - Assign the device to the guest if it's protected by an IOMMU
  *  - Map the IRQs and iomem regions to DOM0
  */
-int handle_device(struct domain *d, struct dt_device_node *dev, p2m_type_t p2mt,
-                  struct rangeset *iomem_ranges, struct rangeset *irq_ranges)
+int __overlay_init handle_device(struct domain *d, struct dt_device_node *dev,
+                                 p2m_type_t p2mt,
+                                 struct rangeset *iomem_ranges,
+                                 struct rangeset *irq_ranges)
 {
     unsigned int naddr;
     unsigned int i;
diff --git a/xen/include/xen/dt-overlay.h b/xen/include/xen/dt-overlay.h
index b2cedf3f2a..7400382842 100644
--- a/xen/include/xen/dt-overlay.h
+++ b/xen/include/xen/dt-overlay.h
@@ -42,10 +42,18 @@ struct xen_sysctl_dt_overlay;
 struct xen_domctl_dt_overlay;
 
 #ifdef CONFIG_OVERLAY_DTB
+
+#define __overlay_init
+
 long dt_overlay_sysctl(struct xen_sysctl_dt_overlay *op);
 long dt_overlay_domctl(struct domain *d, struct xen_domctl_dt_overlay *op);
+
 #else
+
 #include <xen/errno.h>
+
+#define __overlay_init __init
+
 static inline long dt_overlay_sysctl(struct xen_sysctl_dt_overlay *op)
 {
     return -EOPNOTSUPP;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/mwait-idle: Remove unused driver version constant
Message-Id: <E1wKAS6-00FYw0-1Y@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:22 +0000

commit 6c9344ee3d48b8bb7758c72d9e4eeb8841b8f7ec
Author:     Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
AuthorDate: Tue May 5 08:25:56 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:25:56 2026 +0200

    x86/mwait-idle: Remove unused driver version constant
    
    The MWAIT_IDLE_VERSION constant has not been updated since 2016 and serves
    no useful purpose. The driver version is implicitly defined by the
    hypervisor version, making this constant redundant.
    
    Remove the constant to eliminate potential confusion about version
    tracking.
    
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
    Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
    Link: https://patch.msgid.link/20251215111229.132705-1-dedekind1@gmail.com
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 25ff69011ddf
    
    Adjust description to fit our code base.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/cpu/mwait-idle.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 6776eeb9ac..48b7a1e721 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -58,7 +58,6 @@
 
 #include <acpi/cpufreq/cpufreq.h>
 
-#define MWAIT_IDLE_VERSION "0.4.1"
 #undef PREFIX
 #define PREFIX "mwait-idle: "
 
@@ -1636,9 +1635,6 @@ static int __init mwait_idle_probe(void)
 	if (boot_cpu_has(X86_FEATURE_XEN_ARAT))
 		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 
-	pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n",
-		 boot_cpu_data.model);
-
 	pr_debug(PREFIX "lapic_timer_reliable_states %#x\n",
 		 lapic_timer_reliable_states);
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] tools: remove setup_physical_bridge_port() function
Message-Id: <E1wKASG-00FYxJ-1p@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:32 +0000

commit 280e4ca4dffd1558d237804a8bf349b9c3874660
Author:     Elliott Mitchell <ehem+xen@m5p.com>
AuthorDate: Tue May 5 08:26:41 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:26:41 2026 +0200

    tools: remove setup_physical_bridge_port() function
    
    Only the setup_virtual_bridge_port() function was used.  As such merge
    that with _setup_bridge_port() and leave that as the remaining function.
    The last user of setup_physical_bridge_port() was removed in 9fabe55939a8
    ("tools/hotplug: Remove network-*").
    
    Signed-off-by: Elliott Mitchell <ehem+xen@m5p.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
---
 tools/hotplug/Linux/vif-bridge            |  2 +-
 tools/hotplug/Linux/vif-openvswitch       |  2 +-
 tools/hotplug/Linux/xen-network-common.sh | 22 ++++++----------------
 3 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/tools/hotplug/Linux/vif-bridge b/tools/hotplug/Linux/vif-bridge
index 906047e82f..6164c7a52f 100644
--- a/tools/hotplug/Linux/vif-bridge
+++ b/tools/hotplug/Linux/vif-bridge
@@ -78,7 +78,7 @@ fi
 
 case "$command" in
     add|online)
-        setup_virtual_bridge_port "$dev"
+        setup_bridge_port "$dev"
         set_mtu "$bridge" "$dev" "$type_if"
         add_to_bridge "$bridge" "$dev"
         ;;
diff --git a/tools/hotplug/Linux/vif-openvswitch b/tools/hotplug/Linux/vif-openvswitch
index 18bfb6cefb..a8aea2acb5 100644
--- a/tools/hotplug/Linux/vif-openvswitch
+++ b/tools/hotplug/Linux/vif-openvswitch
@@ -88,7 +88,7 @@ add_to_openvswitch () {
 case "$command" in
     add|online)
         check_tools
-        setup_virtual_bridge_port $dev
+        setup_bridge_port $dev
         add_to_openvswitch $dev
         ;;
 
diff --git a/tools/hotplug/Linux/xen-network-common.sh b/tools/hotplug/Linux/xen-network-common.sh
index 42fa704e8d..0150a4840e 100644
--- a/tools/hotplug/Linux/xen-network-common.sh
+++ b/tools/hotplug/Linux/xen-network-common.sh
@@ -79,32 +79,22 @@ find_dhcpd_arg_file()
 }
 
 # configure interfaces which act as pure bridge ports:
-_setup_bridge_port() {
+setup_bridge_port() {
     local dev="$1"
-    local virtual="$2"
 
     # take interface down ...
     ip link set dev ${dev} down
 
-    if [ $virtual -ne 0 ] ; then
-        # Initialise a dummy MAC address. We choose the numerically
-        # largest non-broadcast address to prevent the address getting
-        # stolen by an Ethernet bridge for STP purposes.
-        # (FE:FF:FF:FF:FF:FF)
-        ip link set dev ${dev} address fe:ff:ff:ff:ff:ff || true
-    fi
+    # Initialise a dummy MAC address. We choose the numerically
+    # largest non-broadcast address to prevent the address getting
+    # stolen by an Ethernet bridge for STP purposes.
+    # (FE:FF:FF:FF:FF:FF)
+    ip link set dev ${dev} address fe:ff:ff:ff:ff:ff || true
 
     # ... and configure it
     ip address flush dev ${dev}
 }
 
-setup_physical_bridge_port() {
-    _setup_bridge_port $1 0
-}
-setup_virtual_bridge_port() {
-    _setup_bridge_port $1 1
-}
-
 # Usage: create_bridge bridge
 create_bridge () {
     local bridge=$1
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/cpuidle: split the max_cstate variable
Message-Id: <E1wKASQ-00FYyV-28@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:42 +0000

commit 93acfeb78b508984aa815d00629cc8b6b90dc047
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:27:29 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:27:29 2026 +0200

    x86/cpuidle: split the max_cstate variable
    
    The admin can control the upper bound wanted not only via command line
    option, but also via XEN_SYSCTL_pm_op_set_max_cstate. While decisions how
    to set up the system are okay this way as long as we deem the command line
    option a strict upper bound, what to do during S3 resume should not be
    based on that potentially varying value. Decisions there need to use
    solely the strict upper bound we may have enforced ourselves (or which was
    forced onto us via command line option).
    
    Rather than altering pit_broadcast_is_available(), drop the function
    altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just
    for that to call into acpi/cpu_idle.c again.
    
    Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/acpi/cpu_idle.c    | 37 +++++++++++++++++++++----------------
 xen/arch/x86/cpu/intel.c        |  4 ++--
 xen/arch/x86/cpu/mwait-idle.c   | 17 +++++++++--------
 xen/arch/x86/include/asm/time.h |  1 -
 xen/arch/x86/time.c             | 11 +++--------
 xen/include/xen/acpi.h          | 34 +++++++++++++++++++---------------
 xen/include/xen/cpuidle.h       |  2 +-
 7 files changed, 55 insertions(+), 51 deletions(-)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 3001e98a6e..1a749fabd2 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -119,7 +119,7 @@ bool lapic_timer_init(void)
         lapic_timer_off = hpet_broadcast_enter;
         lapic_timer_on = hpet_broadcast_exit;
     }
-    else if ( pit_broadcast_is_available() )
+    else if ( cpuidle_usable_deep_cstate() )
     {
         lapic_timer_off = pit_broadcast_enter;
         lapic_timer_on = pit_broadcast_exit;
@@ -131,12 +131,15 @@ bool lapic_timer_init(void)
 }
 
 void (*__read_mostly pm_idle_save)(void);
-unsigned int max_cstate __read_mostly = UINT_MAX;
+
+unsigned int max_usable_cstate __read_mostly = UINT_MAX;
+unsigned int max_allowed_cstate __read_mostly = UINT_MAX;
 unsigned int max_csubstate __read_mostly = UINT_MAX;
 
 static int __init cf_check parse_cstate(const char *s)
 {
-    max_cstate = simple_strtoul(s, &s, 0);
+    max_allowed_cstate = simple_strtoul(s, &s, 0);
+    max_usable_cstate = max_allowed_cstate;
     if ( *s == ',' )
         max_csubstate = simple_strtoul(s + 1, NULL, 0);
     return 0;
@@ -413,10 +416,11 @@ static void cf_check dump_cx(unsigned char key)
     unsigned int cpu;
 
     printk("'%c' pressed -> printing ACPI Cx structures\n", key);
-    if ( max_cstate < UINT_MAX )
+    if ( max_cstate() < UINT_MAX )
     {
-        printk("max state: C%u\n", max_cstate);
-        if ( max_csubstate < UINT_MAX )
+        printk("max state: C%u\n", max_cstate());
+        if ( max_allowed_cstate <= max_usable_cstate &&
+             max_csubstate < UINT_MAX )
             printk("max sub-state: %u\n", max_csubstate);
         else
             printk("max sub-state: unlimited\n");
@@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle(void)
     u32 exp = 0, pred = 0;
     u32 irq_traced[4] = { 0 };
 
-    if ( max_cstate > 0 && power &&
+    if ( max_cstate() > 0 && power &&
          (next_state = cpuidle_current_governor->select(power)) > 0 )
     {
         unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1
-                                                         : max_cstate;
+                                                         : max_cstate();
 
         do {
             cx = &power->states[next_state];
         } while ( (cx->type > max_state ||
                    cx->entry_method == ACPI_CSTATE_EM_NONE ||
                    (cx->entry_method == ACPI_CSTATE_EM_FFH &&
-                    cx->type == max_cstate &&
+                    cx->type == max_allowed_cstate &&
                     (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) &&
                   --next_state );
         if ( next_state )
@@ -1448,7 +1452,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     for ( i = 0; i < nr; ++i )
     {
-        if ( cx[i].type > max_cstate )
+        if ( cx[i].type > max_cstate() )
             break;
         power->states[i + 1] = cx[i];
         power->states[i + 1].idx = i + 1;
@@ -1611,21 +1615,22 @@ int pmstat_reset_cx_stat(unsigned int cpu)
 
 void cpuidle_disable_deep_cstate(void)
 {
-    if ( max_cstate > ACPI_STATE_C1 )
+    if ( max_usable_cstate > ACPI_STATE_C1 )
     {
         if ( local_apic_timer_c2_ok )
-            max_cstate = ACPI_STATE_C2;
+            max_usable_cstate = ACPI_STATE_C2;
         else
-            max_cstate = ACPI_STATE_C1;
+            max_usable_cstate = ACPI_STATE_C1;
     }
 
     hpet_disable_legacy_broadcast();
 }
 
-bool cpuidle_using_deep_cstate(void)
+bool cpuidle_usable_deep_cstate(void)
 {
-    return xen_cpuidle && max_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2
-                                                               : ACPI_STATE_C1);
+    return xen_cpuidle &&
+           max_usable_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2
+                                                       : ACPI_STATE_C1);
 }
 
 static int cf_check cpu_callback(
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 18b3c79dc9..90c9d36186 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -384,12 +384,12 @@ static void probe_c3_errata(const struct cpuinfo_x86 *c)
     };
 
     /* Serialized by the AP bringup code. */
-    if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) &&
+    if ( max_usable_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) &&
          x86_match_cpu(models) )
     {
         printk(XENLOG_WARNING
 	       "Disabling C-states C3 and C6 due to CPU errata\n");
-        max_cstate = 1;
+        max_usable_cstate = 1;
     }
 }
 
diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 48b7a1e721..c0d5767f87 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1044,15 +1044,16 @@ static void cf_check mwait_idle(void)
 	u64 before, after;
 	u32 exp = 0, pred = 0, irq_traced[4] = { 0 };
 
-	if (max_cstate > 0 && power &&
+	if (max_cstate() > 0 && power &&
 	    (next_state = cpuidle_current_governor->select(power)) > 0) {
 		unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1
-								 : max_cstate;
+								 : max_cstate();
 
 		do {
 			cx = &power->states[next_state];
-		} while ((cx->type > max_state || (cx->type == max_cstate &&
-			  MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) &&
+		} while ((cx->type > max_state ||
+			  (cx->type == max_allowed_cstate &&
+			   MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) &&
 			 --next_state);
 		if (!next_state)
 			cx = NULL;
@@ -1457,7 +1458,7 @@ static void __init sklh_idle_state_table_update(void)
 	u64 msr;
 
 	/* if PC10 disabled via cmdline max_cstate=7 or shallower */
-	if (max_cstate <= 7)
+	if (max_cstate() <= 7)
 		return;
 
 	/* if PC10 not present in CPUID.MWAIT.EDX */
@@ -1622,7 +1623,7 @@ static int __init mwait_idle_probe(void)
 	    !mwait_substates)
 		return -ENODEV;
 
-	if (!max_cstate || !opt_mwait_idle) {
+	if (!max_cstate() || !opt_mwait_idle) {
 		pr_debug(PREFIX "disabled\n");
 		return -EPERM;
 	}
@@ -1710,8 +1711,8 @@ static int cf_check mwait_idle_cpu_init(
 		hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 		state = MWAIT_HINT2CSTATE(hint) + 1;
 
-		if (state > max_cstate) {
-			printk(PREFIX "max C-state %u reached\n", max_cstate);
+		if (state > max_cstate()) {
+			printk(PREFIX "max C-state %u reached\n", max_cstate());
 			break;
 		}
 
diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/time.h
index 29e1888ffb..44f995ff05 100644
--- a/xen/arch/x86/include/asm/time.h
+++ b/xen/arch/x86/include/asm/time.h
@@ -31,7 +31,6 @@ int cpu_frequency_change(u64 freq);
 
 void cf_check pit_broadcast_enter(void);
 void cf_check pit_broadcast_exit(void);
-int pit_broadcast_is_available(void);
 
 uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks);
 
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 008d9e97d9..8209d37d32 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -517,7 +517,7 @@ static int64_t __init cf_check init_hpet(struct platform_timesource *pts)
     bool disable_hpet = false;
 
     if ( hpet_address && strcmp(opt_clocksource, pts->id) &&
-         cpuidle_using_deep_cstate() )
+         cpuidle_usable_deep_cstate() )
     {
         if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0),
                              PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL )
@@ -2663,7 +2663,7 @@ static int _disable_pit_irq(bool init)
      * XXX dom0 may rely on RTC interrupt delivery, so only enable
      * hpet_broadcast if FSB mode available or if force_hpet_broadcast.
      */
-    if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) )
+    if ( cpuidle_usable_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) )
     {
         init ? hpet_broadcast_init() : hpet_broadcast_resume();
         if ( !hpet_broadcast_is_available() )
@@ -2715,11 +2715,6 @@ void cf_check pit_broadcast_exit(void)
         reprogram_timer(this_cpu(timer_deadline));
 }
 
-int pit_broadcast_is_available(void)
-{
-    return cpuidle_using_deep_cstate();
-}
-
 void send_timer_event(struct vcpu *v)
 {
     send_guest_vcpu_virq(v, VIRQ_TIMER);
@@ -3007,7 +3002,7 @@ static void cf_check dump_softtsc(unsigned char key)
     else if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC ) )
     {
         printk("TSC has constant rate, ");
-        if ( max_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 )
+        if ( max_usable_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 )
             printk("no deep Cstates, passed warp test, deemed reliable, ");
         else
             printk("deep Cstates possible, so not reliable, ");
diff --git a/xen/include/xen/acpi.h b/xen/include/xen/acpi.h
index ca87cd15a8..2fdf38cf74 100644
--- a/xen/include/xen/acpi.h
+++ b/xen/include/xen/acpi.h
@@ -142,30 +142,34 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
 #ifdef	CONFIG_ACPI_CSTATE
 /*
- * max_cstate sets the highest legal C-state.
- * max_cstate = 0: C0 okay, but not C1
- * max_cstate = 1: C1 okay, but not C2
- * max_cstate = 2: C2 okay, but not C3 etc.
-
- * max_csubstate sets the highest legal C-state sub-state. Only applies to the
- * highest legal C-state.
- * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E
- * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2
- * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3
- * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3
+ * max_{allowed,usable}_cstate sets the highest allowed / usable C-state.
+ * max_usable_cstate, while affected by the command line, is internally driven,
+ * whereas max_allowed_cstate can be set from both command line and systcl.
+ * max_*_cstate = 0: C0 okay, but not C1
+ * max_*_cstate = 1: C1 okay, but not C2
+ * max_*_cstate = 2: C2 okay, but not C3 etc.
+ *
+ * max_csubstate sets the highest allowed C-state sub-state. Only applies to
+ * the highest allowed C-state.
+ * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E
+ * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2
+ * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3
+ * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3
  */
 
-extern unsigned int max_cstate;
+extern unsigned int max_usable_cstate;
+extern unsigned int max_allowed_cstate;
 extern unsigned int max_csubstate;
 
+#define max_cstate() min(max_usable_cstate, max_allowed_cstate)
+
 static inline unsigned int acpi_get_cstate_limit(void)
 {
-	return max_cstate;
+	return max_allowed_cstate;
 }
 static inline void acpi_set_cstate_limit(unsigned int new_limit)
 {
-	max_cstate = new_limit;
-	return;
+	max_allowed_cstate = new_limit;
 }
 
 static inline unsigned int acpi_get_csubstate_limit(void)
diff --git a/xen/include/xen/cpuidle.h b/xen/include/xen/cpuidle.h
index 120e354fe3..80b730cf02 100644
--- a/xen/include/xen/cpuidle.h
+++ b/xen/include/xen/cpuidle.h
@@ -89,7 +89,7 @@ struct cpuidle_governor
 extern int8_t xen_cpuidle;
 extern struct cpuidle_governor *cpuidle_current_governor;
 
-bool cpuidle_using_deep_cstate(void);
+bool cpuidle_usable_deep_cstate(void);
 void cpuidle_disable_deep_cstate(void);
 
 #define CPUIDLE_DRIVER_STATE_START  1
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/HVM: drop dead code from HVM_PARAM_IDENT_PT setting
Message-Id: <E1wKASa-00FYzG-2W@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:44:52 +0000

commit 76a79d86662053f1144133ecc7b6030c5577bee9
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:28:56 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:28:56 2026 +0200

    x86/HVM: drop dead code from HVM_PARAM_IDENT_PT setting
    
    The setting of d->arch.hvm.params[] will uniformly happen at the bottom of
    hvm_set_param(), hence as per Misra's classification redundantly doing so
    earlier is "dead code".
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Jason Andryuk <jason.andryuk@amd.com>
---
 xen/arch/x86/hvm/hvm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 4a81afce02..f759a397c5 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4242,10 +4242,7 @@ static int hvm_set_param(struct domain *d, uint32_t index, uint64_t value)
          * capabilities.  Short circuit the pause if possible.
          */
         if ( paging_mode_shadow(d) || !using_vmx() )
-        {
-            d->arch.hvm.params[index] = value;
             break;
-        }
 
         /*
          * Update GUEST_CR3 in each VMCS to point at identity map.
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/mm: normalize page count types to unsigned long
Message-Id: <E1wKASk-00FYzs-2n@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:45:02 +0000

commit 48054287a840011bce4c07f3db47ea1a4c669155
Author:     Bernhard Kaindl <bernhard.kaindl@citrix.com>
AuthorDate: Tue May 5 08:29:45 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:29:45 2026 +0200

    xen/mm: normalize page count types to unsigned long
    
    The current use of long for total_avail_pages and outstanding_claims
    creates an unnecessary mix of signed and unsigned types during page
    allocation calculations. This necessitates awkward constructs
    like '+ 0UL' to satisfy type matching in macros such as min().
    
    Address this by normalizing `total_avail_pages` and `outstanding_claims`
    from `long` to `unsigned long`.
    
    As a direct consequence of making `total_avail_pages` unsigned, the
    post-decrement assertions checking for `>= 0` are no longer logically
    sound. Adjust those assertions to pre-decrement checks.
    
    No functional change intended.
    
    Suggested-by: Jan Beulich <jbeulich@suse.com>
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/common/page_alloc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index b1edef8712..2c4ff2c34c 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -484,10 +484,11 @@ static heap_by_zone_and_order_t *_heap[MAX_NUMNODES];
 static unsigned long node_need_scrub[MAX_NUMNODES];
 
 static unsigned long *avail[MAX_NUMNODES];
-static long total_avail_pages;
+static unsigned long total_avail_pages;
 
 static DEFINE_SPINLOCK(heap_lock);
-static long outstanding_claims; /* total outstanding claims by all domains */
+/* Total outstanding claims by all domains */
+static unsigned long outstanding_claims;
 
 static unsigned long avail_heap_pages(
     unsigned int zone_lo, unsigned int zone_hi, unsigned int node)
@@ -1047,8 +1048,8 @@ static struct page_info *alloc_heap_pages(
 
     ASSERT(avail[node][zone] >= request);
     avail[node][zone] -= request;
+    ASSERT(total_avail_pages >= request);
     total_avail_pages -= request;
-    ASSERT(total_avail_pages >= 0);
 
     if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) )
     {
@@ -1240,8 +1241,8 @@ static int reserve_offlined_page(struct page_info *head)
             continue;
 
         avail[node][zone]--;
+        ASSERT(total_avail_pages > 0);
         total_avail_pages--;
-        ASSERT(total_avail_pages >= 0);
 
         page_list_add_tail(cur_head,
                            test_bit(_PGC_broken, &cur_head->count_info) ?
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CHANGELOG: add xenstored watch depth feature
Message-Id: <E1wKASu-00FZ0e-38@xenbits.xenproject.org>
Date: Tue, 05 May 2026 07:45:12 +0000

commit 07bff81a219a756309e1c75e967b9c432e59c6e4
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue May 5 08:30:20 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:30:20 2026 +0200

    CHANGELOG: add xenstored watch depth feature
    
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index bb41d89997..ce46020dbd 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 ### Added
  - Support for per-domain Xenstore quota in C xenstored (includes
    xenstore-stubdom), libxl and xl.
+ - Support for Xenstore watch depth feature in C xenstored (includes
+   xenstore-stubdom).
  - On x86:
    - Support for Bus Lock Threshold on AMD Zen5 and later CPUs, used by Xen to
      mitigate (by rate-limiting) the system wide impact of an HVM guest
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/shadow: unlock P2M slightly earlier in shadow_track_dirty_vram()
Message-Id: <E1wKBNp-00FbaB-1g@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:01 +0000

commit d367f87cfd7429aa3646e58e764563ce6f361842
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:20:55 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:20:55 2026 +0200

    x86/shadow: unlock P2M slightly earlier in shadow_track_dirty_vram()
    
    There's no need to call vfree() with the lock still held.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/mm/shadow/hvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c
index 3565c7940d..cf4862cbc9 100644
--- a/xen/arch/x86/mm/shadow/hvm.c
+++ b/xen/arch/x86/mm/shadow/hvm.c
@@ -1200,8 +1200,8 @@ int shadow_track_dirty_vram(struct domain *d,
         paging_unlock(d);
         rc = -EFAULT;
     }
-    vfree(dirty_bitmap);
     p2m_unlock(p2m_get_hostp2m(d));
+    vfree(dirty_bitmap);
     return rc;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] Arm: device.c is init-only when OVERLAY_DTB=n
Message-Id: <E1wKBNz-00FbbM-1z@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:11 +0000

commit 227a9aae44a31c440f05e66ed0841b21fb99837d
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:21:45 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:21:45 2026 +0200

    Arm: device.c is init-only when OVERLAY_DTB=n
    
    Introduce an annotation similar to __hwdom_init and use it througout the
    file. All external callers are either themselves __init or are limited to
    OVERLAY_DTB=y. Adjust the Makefile accordingly to also have string
    literals moved into .init.rodata.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
---
 xen/arch/arm/Makefile        |  2 +-
 xen/arch/arm/device.c        | 33 ++++++++++++++++++---------------
 xen/include/xen/dt-overlay.h |  8 ++++++++
 3 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 69200b2728..982c6c396a 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o
 obj-y += cpuerrata.o
 obj-y += cpufeature.o
 obj-y += decode.o
-obj-y += device.o
+obj-y += $(if $(CONFIG_OVERLAY_DTB),device.o,device.init.o)
 obj-$(CONFIG_IOREQ_SERVER) += dm.o
 obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o
 obj-y += domain.o
diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
index 74b54cad34..7d9644fd8b 100644
--- a/xen/arch/arm/device.c
+++ b/xen/arch/arm/device.c
@@ -9,6 +9,7 @@
  */
 
 #include <xen/device_tree.h>
+#include <xen/dt-overlay.h>
 #include <xen/errno.h>
 #include <xen/iocap.h>
 #include <xen/lib.h>
@@ -16,8 +17,8 @@
 #include <asm/firmware/sci.h>
 #include <asm/setup.h>
 
-int map_irq_to_domain(struct domain *d, unsigned int irq,
-                      bool need_mapping, const char *devname)
+int __overlay_init map_irq_to_domain(struct domain *d, unsigned int irq,
+                                     bool need_mapping, const char *devname)
 {
     int res;
 
@@ -49,8 +50,8 @@ int map_irq_to_domain(struct domain *d, unsigned int irq,
     return 0;
 }
 
-int map_range_to_domain(const struct dt_device_node *dev,
-                        uint64_t addr, uint64_t len, void *data)
+int __overlay_init map_range_to_domain(const struct dt_device_node *dev,
+                                       uint64_t addr, uint64_t len, void *data)
 {
     struct map_range_data *mr_data = data;
     struct domain *d = mr_data->d;
@@ -124,10 +125,10 @@ int map_range_to_domain(const struct dt_device_node *dev,
  *   < 0 error
  *   0   success
  */
-int map_device_irqs_to_domain(struct domain *d,
-                              struct dt_device_node *dev,
-                              bool need_mapping,
-                              struct rangeset *irq_ranges)
+int __overlay_init map_device_irqs_to_domain(struct domain *d,
+                                             struct dt_device_node *dev,
+                                             bool need_mapping,
+                                             struct rangeset *irq_ranges)
 {
     unsigned int i, nirq;
     int res, irq;
@@ -180,9 +181,9 @@ int map_device_irqs_to_domain(struct domain *d,
     return 0;
 }
 
-static int map_dt_irq_to_domain(const struct dt_device_node *dev,
-                                const struct dt_irq *dt_irq,
-                                void *data)
+static int __overlay_init map_dt_irq_to_domain(const struct dt_device_node *dev,
+                                               const struct dt_irq *dt_irq,
+                                               void *data)
 {
     struct map_range_data *mr_data = data;
     struct domain *d = mr_data->d;
@@ -219,8 +220,8 @@ static int map_dt_irq_to_domain(const struct dt_device_node *dev,
  * then we may need to perform additional mappings in order to make
  * the child resources available to domain 0.
  */
-static int map_device_children(const struct dt_device_node *dev,
-                               struct map_range_data *mr_data)
+static int __overlay_init map_device_children(const struct dt_device_node *dev,
+                                              struct map_range_data *mr_data)
 {
     if ( dt_device_type_is_equal(dev, "pci") )
     {
@@ -250,8 +251,10 @@ static int map_device_children(const struct dt_device_node *dev,
  *  - Assign the device to the guest if it's protected by an IOMMU
  *  - Map the IRQs and iomem regions to DOM0
  */
-int handle_device(struct domain *d, struct dt_device_node *dev, p2m_type_t p2mt,
-                  struct rangeset *iomem_ranges, struct rangeset *irq_ranges)
+int __overlay_init handle_device(struct domain *d, struct dt_device_node *dev,
+                                 p2m_type_t p2mt,
+                                 struct rangeset *iomem_ranges,
+                                 struct rangeset *irq_ranges)
 {
     unsigned int naddr;
     unsigned int i;
diff --git a/xen/include/xen/dt-overlay.h b/xen/include/xen/dt-overlay.h
index b2cedf3f2a..7400382842 100644
--- a/xen/include/xen/dt-overlay.h
+++ b/xen/include/xen/dt-overlay.h
@@ -42,10 +42,18 @@ struct xen_sysctl_dt_overlay;
 struct xen_domctl_dt_overlay;
 
 #ifdef CONFIG_OVERLAY_DTB
+
+#define __overlay_init
+
 long dt_overlay_sysctl(struct xen_sysctl_dt_overlay *op);
 long dt_overlay_domctl(struct domain *d, struct xen_domctl_dt_overlay *op);
+
 #else
+
 #include <xen/errno.h>
+
+#define __overlay_init __init
+
 static inline long dt_overlay_sysctl(struct xen_sysctl_dt_overlay *op)
 {
     return -EOPNOTSUPP;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/mwait-idle: Remove unused driver version constant
Message-Id: <E1wKBO9-00FbcO-2J@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:21 +0000

commit 6c9344ee3d48b8bb7758c72d9e4eeb8841b8f7ec
Author:     Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
AuthorDate: Tue May 5 08:25:56 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:25:56 2026 +0200

    x86/mwait-idle: Remove unused driver version constant
    
    The MWAIT_IDLE_VERSION constant has not been updated since 2016 and serves
    no useful purpose. The driver version is implicitly defined by the
    hypervisor version, making this constant redundant.
    
    Remove the constant to eliminate potential confusion about version
    tracking.
    
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
    Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
    Link: https://patch.msgid.link/20251215111229.132705-1-dedekind1@gmail.com
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 25ff69011ddf
    
    Adjust description to fit our code base.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/cpu/mwait-idle.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 6776eeb9ac..48b7a1e721 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -58,7 +58,6 @@
 
 #include <acpi/cpufreq/cpufreq.h>
 
-#define MWAIT_IDLE_VERSION "0.4.1"
 #undef PREFIX
 #define PREFIX "mwait-idle: "
 
@@ -1636,9 +1635,6 @@ static int __init mwait_idle_probe(void)
 	if (boot_cpu_has(X86_FEATURE_XEN_ARAT))
 		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 
-	pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n",
-		 boot_cpu_data.model);
-
 	pr_debug(PREFIX "lapic_timer_reliable_states %#x\n",
 		 lapic_timer_reliable_states);
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] tools: remove setup_physical_bridge_port() function
Message-Id: <E1wKBOJ-00FbdZ-2Z@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:31 +0000

commit 280e4ca4dffd1558d237804a8bf349b9c3874660
Author:     Elliott Mitchell <ehem+xen@m5p.com>
AuthorDate: Tue May 5 08:26:41 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:26:41 2026 +0200

    tools: remove setup_physical_bridge_port() function
    
    Only the setup_virtual_bridge_port() function was used.  As such merge
    that with _setup_bridge_port() and leave that as the remaining function.
    The last user of setup_physical_bridge_port() was removed in 9fabe55939a8
    ("tools/hotplug: Remove network-*").
    
    Signed-off-by: Elliott Mitchell <ehem+xen@m5p.com>
    Acked-by: Anthony PERARD <anthony.perard@vates.tech>
---
 tools/hotplug/Linux/vif-bridge            |  2 +-
 tools/hotplug/Linux/vif-openvswitch       |  2 +-
 tools/hotplug/Linux/xen-network-common.sh | 22 ++++++----------------
 3 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/tools/hotplug/Linux/vif-bridge b/tools/hotplug/Linux/vif-bridge
index 906047e82f..6164c7a52f 100644
--- a/tools/hotplug/Linux/vif-bridge
+++ b/tools/hotplug/Linux/vif-bridge
@@ -78,7 +78,7 @@ fi
 
 case "$command" in
     add|online)
-        setup_virtual_bridge_port "$dev"
+        setup_bridge_port "$dev"
         set_mtu "$bridge" "$dev" "$type_if"
         add_to_bridge "$bridge" "$dev"
         ;;
diff --git a/tools/hotplug/Linux/vif-openvswitch b/tools/hotplug/Linux/vif-openvswitch
index 18bfb6cefb..a8aea2acb5 100644
--- a/tools/hotplug/Linux/vif-openvswitch
+++ b/tools/hotplug/Linux/vif-openvswitch
@@ -88,7 +88,7 @@ add_to_openvswitch () {
 case "$command" in
     add|online)
         check_tools
-        setup_virtual_bridge_port $dev
+        setup_bridge_port $dev
         add_to_openvswitch $dev
         ;;
 
diff --git a/tools/hotplug/Linux/xen-network-common.sh b/tools/hotplug/Linux/xen-network-common.sh
index 42fa704e8d..0150a4840e 100644
--- a/tools/hotplug/Linux/xen-network-common.sh
+++ b/tools/hotplug/Linux/xen-network-common.sh
@@ -79,32 +79,22 @@ find_dhcpd_arg_file()
 }
 
 # configure interfaces which act as pure bridge ports:
-_setup_bridge_port() {
+setup_bridge_port() {
     local dev="$1"
-    local virtual="$2"
 
     # take interface down ...
     ip link set dev ${dev} down
 
-    if [ $virtual -ne 0 ] ; then
-        # Initialise a dummy MAC address. We choose the numerically
-        # largest non-broadcast address to prevent the address getting
-        # stolen by an Ethernet bridge for STP purposes.
-        # (FE:FF:FF:FF:FF:FF)
-        ip link set dev ${dev} address fe:ff:ff:ff:ff:ff || true
-    fi
+    # Initialise a dummy MAC address. We choose the numerically
+    # largest non-broadcast address to prevent the address getting
+    # stolen by an Ethernet bridge for STP purposes.
+    # (FE:FF:FF:FF:FF:FF)
+    ip link set dev ${dev} address fe:ff:ff:ff:ff:ff || true
 
     # ... and configure it
     ip address flush dev ${dev}
 }
 
-setup_physical_bridge_port() {
-    _setup_bridge_port $1 0
-}
-setup_virtual_bridge_port() {
-    _setup_bridge_port $1 1
-}
-
 # Usage: create_bridge bridge
 create_bridge () {
     local bridge=$1
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/cpuidle: split the max_cstate variable
Message-Id: <E1wKBOT-00Fbeb-2v@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:41 +0000

commit 93acfeb78b508984aa815d00629cc8b6b90dc047
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:27:29 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:27:29 2026 +0200

    x86/cpuidle: split the max_cstate variable
    
    The admin can control the upper bound wanted not only via command line
    option, but also via XEN_SYSCTL_pm_op_set_max_cstate. While decisions how
    to set up the system are okay this way as long as we deem the command line
    option a strict upper bound, what to do during S3 resume should not be
    based on that potentially varying value. Decisions there need to use
    solely the strict upper bound we may have enforced ourselves (or which was
    forced onto us via command line option).
    
    Rather than altering pit_broadcast_is_available(), drop the function
    altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just
    for that to call into acpi/cpu_idle.c again.
    
    Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/acpi/cpu_idle.c    | 37 +++++++++++++++++++++----------------
 xen/arch/x86/cpu/intel.c        |  4 ++--
 xen/arch/x86/cpu/mwait-idle.c   | 17 +++++++++--------
 xen/arch/x86/include/asm/time.h |  1 -
 xen/arch/x86/time.c             | 11 +++--------
 xen/include/xen/acpi.h          | 34 +++++++++++++++++++---------------
 xen/include/xen/cpuidle.h       |  2 +-
 7 files changed, 55 insertions(+), 51 deletions(-)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 3001e98a6e..1a749fabd2 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -119,7 +119,7 @@ bool lapic_timer_init(void)
         lapic_timer_off = hpet_broadcast_enter;
         lapic_timer_on = hpet_broadcast_exit;
     }
-    else if ( pit_broadcast_is_available() )
+    else if ( cpuidle_usable_deep_cstate() )
     {
         lapic_timer_off = pit_broadcast_enter;
         lapic_timer_on = pit_broadcast_exit;
@@ -131,12 +131,15 @@ bool lapic_timer_init(void)
 }
 
 void (*__read_mostly pm_idle_save)(void);
-unsigned int max_cstate __read_mostly = UINT_MAX;
+
+unsigned int max_usable_cstate __read_mostly = UINT_MAX;
+unsigned int max_allowed_cstate __read_mostly = UINT_MAX;
 unsigned int max_csubstate __read_mostly = UINT_MAX;
 
 static int __init cf_check parse_cstate(const char *s)
 {
-    max_cstate = simple_strtoul(s, &s, 0);
+    max_allowed_cstate = simple_strtoul(s, &s, 0);
+    max_usable_cstate = max_allowed_cstate;
     if ( *s == ',' )
         max_csubstate = simple_strtoul(s + 1, NULL, 0);
     return 0;
@@ -413,10 +416,11 @@ static void cf_check dump_cx(unsigned char key)
     unsigned int cpu;
 
     printk("'%c' pressed -> printing ACPI Cx structures\n", key);
-    if ( max_cstate < UINT_MAX )
+    if ( max_cstate() < UINT_MAX )
     {
-        printk("max state: C%u\n", max_cstate);
-        if ( max_csubstate < UINT_MAX )
+        printk("max state: C%u\n", max_cstate());
+        if ( max_allowed_cstate <= max_usable_cstate &&
+             max_csubstate < UINT_MAX )
             printk("max sub-state: %u\n", max_csubstate);
         else
             printk("max sub-state: unlimited\n");
@@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle(void)
     u32 exp = 0, pred = 0;
     u32 irq_traced[4] = { 0 };
 
-    if ( max_cstate > 0 && power &&
+    if ( max_cstate() > 0 && power &&
          (next_state = cpuidle_current_governor->select(power)) > 0 )
     {
         unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1
-                                                         : max_cstate;
+                                                         : max_cstate();
 
         do {
             cx = &power->states[next_state];
         } while ( (cx->type > max_state ||
                    cx->entry_method == ACPI_CSTATE_EM_NONE ||
                    (cx->entry_method == ACPI_CSTATE_EM_FFH &&
-                    cx->type == max_cstate &&
+                    cx->type == max_allowed_cstate &&
                     (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) &&
                   --next_state );
         if ( next_state )
@@ -1448,7 +1452,7 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
 
     for ( i = 0; i < nr; ++i )
     {
-        if ( cx[i].type > max_cstate )
+        if ( cx[i].type > max_cstate() )
             break;
         power->states[i + 1] = cx[i];
         power->states[i + 1].idx = i + 1;
@@ -1611,21 +1615,22 @@ int pmstat_reset_cx_stat(unsigned int cpu)
 
 void cpuidle_disable_deep_cstate(void)
 {
-    if ( max_cstate > ACPI_STATE_C1 )
+    if ( max_usable_cstate > ACPI_STATE_C1 )
     {
         if ( local_apic_timer_c2_ok )
-            max_cstate = ACPI_STATE_C2;
+            max_usable_cstate = ACPI_STATE_C2;
         else
-            max_cstate = ACPI_STATE_C1;
+            max_usable_cstate = ACPI_STATE_C1;
     }
 
     hpet_disable_legacy_broadcast();
 }
 
-bool cpuidle_using_deep_cstate(void)
+bool cpuidle_usable_deep_cstate(void)
 {
-    return xen_cpuidle && max_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2
-                                                               : ACPI_STATE_C1);
+    return xen_cpuidle &&
+           max_usable_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2
+                                                       : ACPI_STATE_C1);
 }
 
 static int cf_check cpu_callback(
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 18b3c79dc9..90c9d36186 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -384,12 +384,12 @@ static void probe_c3_errata(const struct cpuinfo_x86 *c)
     };
 
     /* Serialized by the AP bringup code. */
-    if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) &&
+    if ( max_usable_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) &&
          x86_match_cpu(models) )
     {
         printk(XENLOG_WARNING
 	       "Disabling C-states C3 and C6 due to CPU errata\n");
-        max_cstate = 1;
+        max_usable_cstate = 1;
     }
 }
 
diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index 48b7a1e721..c0d5767f87 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1044,15 +1044,16 @@ static void cf_check mwait_idle(void)
 	u64 before, after;
 	u32 exp = 0, pred = 0, irq_traced[4] = { 0 };
 
-	if (max_cstate > 0 && power &&
+	if (max_cstate() > 0 && power &&
 	    (next_state = cpuidle_current_governor->select(power)) > 0) {
 		unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1
-								 : max_cstate;
+								 : max_cstate();
 
 		do {
 			cx = &power->states[next_state];
-		} while ((cx->type > max_state || (cx->type == max_cstate &&
-			  MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) &&
+		} while ((cx->type > max_state ||
+			  (cx->type == max_allowed_cstate &&
+			   MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) &&
 			 --next_state);
 		if (!next_state)
 			cx = NULL;
@@ -1457,7 +1458,7 @@ static void __init sklh_idle_state_table_update(void)
 	u64 msr;
 
 	/* if PC10 disabled via cmdline max_cstate=7 or shallower */
-	if (max_cstate <= 7)
+	if (max_cstate() <= 7)
 		return;
 
 	/* if PC10 not present in CPUID.MWAIT.EDX */
@@ -1622,7 +1623,7 @@ static int __init mwait_idle_probe(void)
 	    !mwait_substates)
 		return -ENODEV;
 
-	if (!max_cstate || !opt_mwait_idle) {
+	if (!max_cstate() || !opt_mwait_idle) {
 		pr_debug(PREFIX "disabled\n");
 		return -EPERM;
 	}
@@ -1710,8 +1711,8 @@ static int cf_check mwait_idle_cpu_init(
 		hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 		state = MWAIT_HINT2CSTATE(hint) + 1;
 
-		if (state > max_cstate) {
-			printk(PREFIX "max C-state %u reached\n", max_cstate);
+		if (state > max_cstate()) {
+			printk(PREFIX "max C-state %u reached\n", max_cstate());
 			break;
 		}
 
diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/time.h
index 29e1888ffb..44f995ff05 100644
--- a/xen/arch/x86/include/asm/time.h
+++ b/xen/arch/x86/include/asm/time.h
@@ -31,7 +31,6 @@ int cpu_frequency_change(u64 freq);
 
 void cf_check pit_broadcast_enter(void);
 void cf_check pit_broadcast_exit(void);
-int pit_broadcast_is_available(void);
 
 uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks);
 
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 008d9e97d9..8209d37d32 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -517,7 +517,7 @@ static int64_t __init cf_check init_hpet(struct platform_timesource *pts)
     bool disable_hpet = false;
 
     if ( hpet_address && strcmp(opt_clocksource, pts->id) &&
-         cpuidle_using_deep_cstate() )
+         cpuidle_usable_deep_cstate() )
     {
         if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0),
                              PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL )
@@ -2663,7 +2663,7 @@ static int _disable_pit_irq(bool init)
      * XXX dom0 may rely on RTC interrupt delivery, so only enable
      * hpet_broadcast if FSB mode available or if force_hpet_broadcast.
      */
-    if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) )
+    if ( cpuidle_usable_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) )
     {
         init ? hpet_broadcast_init() : hpet_broadcast_resume();
         if ( !hpet_broadcast_is_available() )
@@ -2715,11 +2715,6 @@ void cf_check pit_broadcast_exit(void)
         reprogram_timer(this_cpu(timer_deadline));
 }
 
-int pit_broadcast_is_available(void)
-{
-    return cpuidle_using_deep_cstate();
-}
-
 void send_timer_event(struct vcpu *v)
 {
     send_guest_vcpu_virq(v, VIRQ_TIMER);
@@ -3007,7 +3002,7 @@ static void cf_check dump_softtsc(unsigned char key)
     else if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC ) )
     {
         printk("TSC has constant rate, ");
-        if ( max_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 )
+        if ( max_usable_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 )
             printk("no deep Cstates, passed warp test, deemed reliable, ");
         else
             printk("deep Cstates possible, so not reliable, ");
diff --git a/xen/include/xen/acpi.h b/xen/include/xen/acpi.h
index ca87cd15a8..2fdf38cf74 100644
--- a/xen/include/xen/acpi.h
+++ b/xen/include/xen/acpi.h
@@ -142,30 +142,34 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
 #ifdef	CONFIG_ACPI_CSTATE
 /*
- * max_cstate sets the highest legal C-state.
- * max_cstate = 0: C0 okay, but not C1
- * max_cstate = 1: C1 okay, but not C2
- * max_cstate = 2: C2 okay, but not C3 etc.
-
- * max_csubstate sets the highest legal C-state sub-state. Only applies to the
- * highest legal C-state.
- * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E
- * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2
- * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3
- * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3
+ * max_{allowed,usable}_cstate sets the highest allowed / usable C-state.
+ * max_usable_cstate, while affected by the command line, is internally driven,
+ * whereas max_allowed_cstate can be set from both command line and systcl.
+ * max_*_cstate = 0: C0 okay, but not C1
+ * max_*_cstate = 1: C1 okay, but not C2
+ * max_*_cstate = 2: C2 okay, but not C3 etc.
+ *
+ * max_csubstate sets the highest allowed C-state sub-state. Only applies to
+ * the highest allowed C-state.
+ * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E
+ * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2
+ * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3
+ * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3
  */
 
-extern unsigned int max_cstate;
+extern unsigned int max_usable_cstate;
+extern unsigned int max_allowed_cstate;
 extern unsigned int max_csubstate;
 
+#define max_cstate() min(max_usable_cstate, max_allowed_cstate)
+
 static inline unsigned int acpi_get_cstate_limit(void)
 {
-	return max_cstate;
+	return max_allowed_cstate;
 }
 static inline void acpi_set_cstate_limit(unsigned int new_limit)
 {
-	max_cstate = new_limit;
-	return;
+	max_allowed_cstate = new_limit;
 }
 
 static inline unsigned int acpi_get_csubstate_limit(void)
diff --git a/xen/include/xen/cpuidle.h b/xen/include/xen/cpuidle.h
index 120e354fe3..80b730cf02 100644
--- a/xen/include/xen/cpuidle.h
+++ b/xen/include/xen/cpuidle.h
@@ -89,7 +89,7 @@ struct cpuidle_governor
 extern int8_t xen_cpuidle;
 extern struct cpuidle_governor *cpuidle_current_governor;
 
-bool cpuidle_using_deep_cstate(void);
+bool cpuidle_usable_deep_cstate(void);
 void cpuidle_disable_deep_cstate(void);
 
 #define CPUIDLE_DRIVER_STATE_START  1
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/HVM: drop dead code from HVM_PARAM_IDENT_PT setting
Message-Id: <E1wKBOe-00Fbfs-01@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:44:52 +0000

commit 76a79d86662053f1144133ecc7b6030c5577bee9
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 5 08:28:56 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:28:56 2026 +0200

    x86/HVM: drop dead code from HVM_PARAM_IDENT_PT setting
    
    The setting of d->arch.hvm.params[] will uniformly happen at the bottom of
    hvm_set_param(), hence as per Misra's classification redundantly doing so
    earlier is "dead code".
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Jason Andryuk <jason.andryuk@amd.com>
---
 xen/arch/x86/hvm/hvm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 4a81afce02..f759a397c5 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4242,10 +4242,7 @@ static int hvm_set_param(struct domain *d, uint32_t index, uint64_t value)
          * capabilities.  Short circuit the pause if possible.
          */
         if ( paging_mode_shadow(d) || !using_vmx() )
-        {
-            d->arch.hvm.params[index] = value;
             break;
-        }
 
         /*
          * Update GUEST_CR3 in each VMCS to point at identity map.
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/mm: normalize page count types to unsigned long
Message-Id: <E1wKBOo-00Fbgc-0J@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:45:02 +0000

commit 48054287a840011bce4c07f3db47ea1a4c669155
Author:     Bernhard Kaindl <bernhard.kaindl@citrix.com>
AuthorDate: Tue May 5 08:29:45 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:29:45 2026 +0200

    xen/mm: normalize page count types to unsigned long
    
    The current use of long for total_avail_pages and outstanding_claims
    creates an unnecessary mix of signed and unsigned types during page
    allocation calculations. This necessitates awkward constructs
    like '+ 0UL' to satisfy type matching in macros such as min().
    
    Address this by normalizing `total_avail_pages` and `outstanding_claims`
    from `long` to `unsigned long`.
    
    As a direct consequence of making `total_avail_pages` unsigned, the
    post-decrement assertions checking for `>= 0` are no longer logically
    sound. Adjust those assertions to pre-decrement checks.
    
    No functional change intended.
    
    Suggested-by: Jan Beulich <jbeulich@suse.com>
    Signed-off-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/common/page_alloc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index b1edef8712..2c4ff2c34c 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -484,10 +484,11 @@ static heap_by_zone_and_order_t *_heap[MAX_NUMNODES];
 static unsigned long node_need_scrub[MAX_NUMNODES];
 
 static unsigned long *avail[MAX_NUMNODES];
-static long total_avail_pages;
+static unsigned long total_avail_pages;
 
 static DEFINE_SPINLOCK(heap_lock);
-static long outstanding_claims; /* total outstanding claims by all domains */
+/* Total outstanding claims by all domains */
+static unsigned long outstanding_claims;
 
 static unsigned long avail_heap_pages(
     unsigned int zone_lo, unsigned int zone_hi, unsigned int node)
@@ -1047,8 +1048,8 @@ static struct page_info *alloc_heap_pages(
 
     ASSERT(avail[node][zone] >= request);
     avail[node][zone] -= request;
+    ASSERT(total_avail_pages >= request);
     total_avail_pages -= request;
-    ASSERT(total_avail_pages >= 0);
 
     if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) )
     {
@@ -1240,8 +1241,8 @@ static int reserve_offlined_page(struct page_info *head)
             continue;
 
         avail[node][zone]--;
+        ASSERT(total_avail_pages > 0);
         total_avail_pages--;
-        ASSERT(total_avail_pages >= 0);
 
         page_list_add_tail(cur_head,
                            test_bit(_PGC_broken, &cur_head->count_info) ?
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CHANGELOG: add xenstored watch depth feature
Message-Id: <E1wKBOy-00Fbh4-0d@xenbits.xenproject.org>
Date: Tue, 05 May 2026 08:45:12 +0000

commit 07bff81a219a756309e1c75e967b9c432e59c6e4
Author:     Juergen Gross <jgross@suse.com>
AuthorDate: Tue May 5 08:30:20 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 5 08:30:20 2026 +0200

    CHANGELOG: add xenstored watch depth feature
    
    Signed-off-by: Juergen Gross <jgross@suse.com>
    Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index bb41d89997..ce46020dbd 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 ### Added
  - Support for per-domain Xenstore quota in C xenstored (includes
    xenstore-stubdom), libxl and xl.
+ - Support for Xenstore watch depth feature in C xenstored (includes
+   xenstore-stubdom).
  - On x86:
    - Support for Bus Lock Threshold on AMD Zen5 and later CPUs, used by Xen to
      mitigate (by rate-limiting) the system wide impact of an HVM guest
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] ARM/vgic: Use for_each_set_bit() in vgic_sync_from_lrs()
Message-Id: <E1wKDQc-00FiXu-1M@xenbits.xenproject.org>
Date: Tue, 05 May 2026 10:55:02 +0000

commit b4fd29dfe1f8114f5b978a5f8307ba37f1d9595d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Feb 25 13:20:12 2026 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    ARM/vgic: Use for_each_set_bit() in vgic_sync_from_lrs()
    
    lr_mask doesn't have bits set beyond the hardware limit, with the upper bits
    remaining zero.  Therefore, for_each_set_bit() is a better option.
    
    For ARM64, bloat-o-meter reports:
    
      Function                                     old     new   delta
      vgic_sync_from_lrs                           208     168     -40
    
    but this doesn't highlight that it also removes a call to find_next_bit() from
    each loop iteration.
    
    No functional change.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Julien Grall <julien@xen.org>
---
 xen/arch/arm/gic-vgic.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c
index ea48c5375a..fae80e6cd2 100644
--- a/xen/arch/arm/gic-vgic.c
+++ b/xen/arch/arm/gic-vgic.c
@@ -241,9 +241,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
 
 void vgic_sync_from_lrs(struct vcpu *v)
 {
-    int i = 0;
     unsigned long flags;
-    unsigned int nr_lrs = gic_get_nr_lrs();
 
     /* The idle domain has no LRs to be cleared. Since gic_restore_state
      * doesn't write any LR registers for the idle domain they could be
@@ -255,11 +253,8 @@ void vgic_sync_from_lrs(struct vcpu *v)
 
     spin_lock_irqsave(&v->arch.vgic.lock, flags);
 
-    while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask),
-                              nr_lrs, i)) < nr_lrs ) {
+    for_each_set_bit ( i, this_cpu(lr_mask) )
         gic_update_one_lr(v, i);
-        i++;
-    }
 
     spin_unlock_irqrestore(&v->arch.vgic.lock, flags);
 }
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/boot: Disable interrupts when establishing SSP
Message-Id: <E1wKDQm-00FiYZ-1g@xenbits.xenproject.org>
Date: Tue, 05 May 2026 10:55:12 +0000

commit acfd2631b95e29fd68b98d902a1663e07474ed5f
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 17:50:44 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    x86/boot: Disable interrupts when establishing SSP
    
    Gitlab CI reported a crash on boot on Alder Lake hardware.  The bug is years
    old, making it an incredibly rare occurance:
    
      (XEN) *** DOUBLE FAULT ***
      (XEN) ----[ Xen-4.22-unstable  x86_64  debug=y ubsan=y  Not tainted ]----
      (XEN) CPU:    0
      (XEN) RIP:    e008:[<ffff82d04077bbc4>] arch/x86/setup.c#reinit_bsp_stack+0xfa/0x160
      (XEN) RFLAGS: 0000000000010202   CONTEXT: hypervisor
      (XEN) rax: 0000000000000007   rbx: ffff83049a4b0000   rcx: 00000000000006a2
      (XEN) rdx: 0000000000000000   rsi: 0000000000000000   rdi: 0000000000000000
      (XEN) rbp: ffff83049a4b7f00   rsp: ffff83049a4b7ef8   r8:  ffff830497e47000
      (XEN) r9:  00000000ffffffff   r10: 00000000900c2121   r11: 000000009a392956
      (XEN) r12: ffff830497e47000   r13: ffff830497e49f40   r14: 0000000000000000
      (XEN) r15: ffff82d0407dad10   cr0: 0000000080050033   cr4: 0000000000f526e0
      (XEN) cr3: 0000000043c16000   cr2: fffffffffffffffc
      (XEN) fsb: 0000000000000000   gsb: 0000000000000000   gss: 0000000000000000
      (XEN) ds: 0000   es: 0000   fs: 0000   gs: 0000   ss: 0000   cs: e008
      (XEN) Xen code around <ffff82d04077bbc4> (arch/x86/setup.c#reinit_bsp_stack+0xfa/0x160):
      (XEN)  00 b9 a2 06 00 00 0f 30 <80> 3d 71 26 f1 ff 00 74 3e 48 8d 93 f8 5f 00 00
      (XEN) Valid stack range: ffff83049a4b6000-ffff83049a4b8000, sp=ffff83049a4b7ef8, tss.rsp0=ffff83049a4b7fb0
      (XEN) No stack overflow detected. Skipping stack trace.
      (XEN)
      (XEN) ****************************************
      (XEN) Panic on CPU 0:
      (XEN) DOUBLE FAULT -- system shutdown
      (XEN) ****************************************
    
    This is on the instruction boundary after enabling CET (writing MSR_S_CET) and
    prior to establishing SSP.  Despite identifying this as a critical window
    where any fault was deadly (the CPU tries to push a shadow stack frame at 0,
    hence the CR2 value wrapping around to the top of the address space), I
    clearly forgot that this meant interrupts too, which are enabled.
    
    Disable interrupts during the critical period.
    
    Fixes: b60ab42db2f0 ("x86/shstk: Activate Supervisor Shadow Stacks")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
---
 xen/arch/x86/setup.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index d041cbd5f6..19ee857abf 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -908,6 +908,13 @@ static void __init noreturn reinit_bsp_stack(void)
 
     if ( cpu_has_xen_shstk )
     {
+        /*
+         * Immediately after enabling CET, SSP is 0 and most interrupts and
+         * exceptions are fatal.  Like the SYSCALL/SYSENTER gaps, IST vectors
+         * (including NMI and #MC) are safe owing to IST switching the shstk.
+         */
+        local_irq_disable();
+
         wrmsrl(MSR_S_CET, xen_msr_s_cet_value());
 
         /*
@@ -932,6 +939,8 @@ static void __init noreturn reinit_bsp_stack(void)
         }
         else
             asm volatile ( "setssbsy" ::: "memory" );
+
+        local_irq_enable();
     }
 
     reset_stack_and_jump(init_done);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/svm: Always sync guest CR2 on VMExit
Message-Id: <E1wKDQw-00FiZ1-1z@xenbits.xenproject.org>
Date: Tue, 05 May 2026 10:55:22 +0000

commit 3e6bca616b344aaa62602fcef0021255d467c2fd
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 20:17:29 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    x86/svm: Always sync guest CR2 on VMExit
    
    Under SVM, there are two copies of guest CR2.  One is v->arch.hvm.guest_cr[2]
    and one is in the VMCB.
    
    Xen doesn't intercept CR2 accesses, so this mostly goes unnoticed; hardware
    loads and saves the guest CR2 in the VMCB across VMRUN/VMExit.
    
    For HAP guests (where #PF is not intercepted, and therefore we don't typically
    inject #PF either), this causes the guest CR2 value to be lost on migrate.  As
    migration is cooperative and not done from the #PF handler, this also goes
    unnoticed by guests.
    
    It also means that an emulated MOV-from-CR2 reads a stale value.
    
    Reported-by: Stefano Stabellini <sstabellini@kernel.org>
    Fixes: d1bd157fbc9b ("Big merge the HVM full-virtualisation abstractions.")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Tested-by: Stefano Stabellini <sstabellini@kernel.org>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/hvm/svm/svm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index ced6166847..f49d2ebbfd 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -2505,6 +2505,7 @@ void asmlinkage svm_vmexit_handler(void)
     hvm_sanitize_regs_fields(
         regs, !(vmcb_get_efer(vmcb) & EFER_LMA) || !(vmcb->cs.l));
 
+    v->arch.hvm.guest_cr[2] = vmcb_get_cr2(vmcb);
     if ( paging_mode_hap(v->domain) )
         v->arch.hvm.guest_cr[3] = v->arch.hvm.hw_cr[3] = vmcb_get_cr3(vmcb);
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] ARM/vgic: Use for_each_set_bit() in vgic_sync_from_lrs()
Message-Id: <E1wKEMg-00FlDq-0w@xenbits.xenproject.org>
Date: Tue, 05 May 2026 11:55:02 +0000

commit b4fd29dfe1f8114f5b978a5f8307ba37f1d9595d
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Wed Feb 25 13:20:12 2026 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    ARM/vgic: Use for_each_set_bit() in vgic_sync_from_lrs()
    
    lr_mask doesn't have bits set beyond the hardware limit, with the upper bits
    remaining zero.  Therefore, for_each_set_bit() is a better option.
    
    For ARM64, bloat-o-meter reports:
    
      Function                                     old     new   delta
      vgic_sync_from_lrs                           208     168     -40
    
    but this doesn't highlight that it also removes a call to find_next_bit() from
    each loop iteration.
    
    No functional change.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Julien Grall <julien@xen.org>
---
 xen/arch/arm/gic-vgic.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c
index ea48c5375a..fae80e6cd2 100644
--- a/xen/arch/arm/gic-vgic.c
+++ b/xen/arch/arm/gic-vgic.c
@@ -241,9 +241,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
 
 void vgic_sync_from_lrs(struct vcpu *v)
 {
-    int i = 0;
     unsigned long flags;
-    unsigned int nr_lrs = gic_get_nr_lrs();
 
     /* The idle domain has no LRs to be cleared. Since gic_restore_state
      * doesn't write any LR registers for the idle domain they could be
@@ -255,11 +253,8 @@ void vgic_sync_from_lrs(struct vcpu *v)
 
     spin_lock_irqsave(&v->arch.vgic.lock, flags);
 
-    while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask),
-                              nr_lrs, i)) < nr_lrs ) {
+    for_each_set_bit ( i, this_cpu(lr_mask) )
         gic_update_one_lr(v, i);
-        i++;
-    }
 
     spin_unlock_irqrestore(&v->arch.vgic.lock, flags);
 }
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/boot: Disable interrupts when establishing SSP
Message-Id: <E1wKEMq-00FlEI-1E@xenbits.xenproject.org>
Date: Tue, 05 May 2026 11:55:12 +0000

commit acfd2631b95e29fd68b98d902a1663e07474ed5f
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 17:50:44 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    x86/boot: Disable interrupts when establishing SSP
    
    Gitlab CI reported a crash on boot on Alder Lake hardware.  The bug is years
    old, making it an incredibly rare occurance:
    
      (XEN) *** DOUBLE FAULT ***
      (XEN) ----[ Xen-4.22-unstable  x86_64  debug=y ubsan=y  Not tainted ]----
      (XEN) CPU:    0
      (XEN) RIP:    e008:[<ffff82d04077bbc4>] arch/x86/setup.c#reinit_bsp_stack+0xfa/0x160
      (XEN) RFLAGS: 0000000000010202   CONTEXT: hypervisor
      (XEN) rax: 0000000000000007   rbx: ffff83049a4b0000   rcx: 00000000000006a2
      (XEN) rdx: 0000000000000000   rsi: 0000000000000000   rdi: 0000000000000000
      (XEN) rbp: ffff83049a4b7f00   rsp: ffff83049a4b7ef8   r8:  ffff830497e47000
      (XEN) r9:  00000000ffffffff   r10: 00000000900c2121   r11: 000000009a392956
      (XEN) r12: ffff830497e47000   r13: ffff830497e49f40   r14: 0000000000000000
      (XEN) r15: ffff82d0407dad10   cr0: 0000000080050033   cr4: 0000000000f526e0
      (XEN) cr3: 0000000043c16000   cr2: fffffffffffffffc
      (XEN) fsb: 0000000000000000   gsb: 0000000000000000   gss: 0000000000000000
      (XEN) ds: 0000   es: 0000   fs: 0000   gs: 0000   ss: 0000   cs: e008
      (XEN) Xen code around <ffff82d04077bbc4> (arch/x86/setup.c#reinit_bsp_stack+0xfa/0x160):
      (XEN)  00 b9 a2 06 00 00 0f 30 <80> 3d 71 26 f1 ff 00 74 3e 48 8d 93 f8 5f 00 00
      (XEN) Valid stack range: ffff83049a4b6000-ffff83049a4b8000, sp=ffff83049a4b7ef8, tss.rsp0=ffff83049a4b7fb0
      (XEN) No stack overflow detected. Skipping stack trace.
      (XEN)
      (XEN) ****************************************
      (XEN) Panic on CPU 0:
      (XEN) DOUBLE FAULT -- system shutdown
      (XEN) ****************************************
    
    This is on the instruction boundary after enabling CET (writing MSR_S_CET) and
    prior to establishing SSP.  Despite identifying this as a critical window
    where any fault was deadly (the CPU tries to push a shadow stack frame at 0,
    hence the CR2 value wrapping around to the top of the address space), I
    clearly forgot that this meant interrupts too, which are enabled.
    
    Disable interrupts during the critical period.
    
    Fixes: b60ab42db2f0 ("x86/shstk: Activate Supervisor Shadow Stacks")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
---
 xen/arch/x86/setup.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index d041cbd5f6..19ee857abf 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -908,6 +908,13 @@ static void __init noreturn reinit_bsp_stack(void)
 
     if ( cpu_has_xen_shstk )
     {
+        /*
+         * Immediately after enabling CET, SSP is 0 and most interrupts and
+         * exceptions are fatal.  Like the SYSCALL/SYSENTER gaps, IST vectors
+         * (including NMI and #MC) are safe owing to IST switching the shstk.
+         */
+        local_irq_disable();
+
         wrmsrl(MSR_S_CET, xen_msr_s_cet_value());
 
         /*
@@ -932,6 +939,8 @@ static void __init noreturn reinit_bsp_stack(void)
         }
         else
             asm volatile ( "setssbsy" ::: "memory" );
+
+        local_irq_enable();
     }
 
     reset_stack_and_jump(init_done);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/svm: Always sync guest CR2 on VMExit
Message-Id: <E1wKEN0-00FlF0-1b@xenbits.xenproject.org>
Date: Tue, 05 May 2026 11:55:22 +0000

commit 3e6bca616b344aaa62602fcef0021255d467c2fd
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Fri May 1 20:17:29 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 5 11:45:00 2026 +0100

    x86/svm: Always sync guest CR2 on VMExit
    
    Under SVM, there are two copies of guest CR2.  One is v->arch.hvm.guest_cr[2]
    and one is in the VMCB.
    
    Xen doesn't intercept CR2 accesses, so this mostly goes unnoticed; hardware
    loads and saves the guest CR2 in the VMCB across VMRUN/VMExit.
    
    For HAP guests (where #PF is not intercepted, and therefore we don't typically
    inject #PF either), this causes the guest CR2 value to be lost on migrate.  As
    migration is cooperative and not done from the #PF handler, this also goes
    unnoticed by guests.
    
    It also means that an emulated MOV-from-CR2 reads a stale value.
    
    Reported-by: Stefano Stabellini <sstabellini@kernel.org>
    Fixes: d1bd157fbc9b ("Big merge the HVM full-virtualisation abstractions.")
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Tested-by: Stefano Stabellini <sstabellini@kernel.org>
    Reviewed-by: Teddy Astie <teddy.astie@vates.tech>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/hvm/svm/svm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index ced6166847..f49d2ebbfd 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -2505,6 +2505,7 @@ void asmlinkage svm_vmexit_handler(void)
     hvm_sanitize_regs_fields(
         regs, !(vmcb_get_efer(vmcb) & EFER_LMA) || !(vmcb->cs.l));
 
+    v->arch.hvm.guest_cr[2] = vmcb_get_cr2(vmcb);
     if ( paging_mode_hap(v->domain) )
         v->arch.hvm.guest_cr[3] = v->arch.hvm.hw_cr[3] = vmcb_get_cr3(vmcb);
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] automation/gitlab: introduce macOS build jobs
Message-Id: <E1wKKzx-00GAlf-2S@xenbits.xenproject.org>
Date: Tue, 05 May 2026 19:00:01 +0000

commit 278953f6c1551e392585b7f2229aa28086bb1f39
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Apr 23 18:19:38 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Tue May 5 20:52:48 2026 +0200

    automation/gitlab: introduce macOS build jobs
    
    With the imminent decommission of CirrusCI we will lose the limited macOS
    build testing done there.  Introduce two Gitlab macOS build jobs that
    reproduce the ones present on CirrusCI.
    
    According to the "Community programs" Gitlab documentation [0] we get
    50,000 compute minutes per month.  The arm64 job takes ~1m 15s, and the
    x86_64 one ~2m.  I think it's likely enough given the amount of minutes we
    have available.  We might need to reconsider if we add more tasks that
    consume compute minutes.
    
    [0] https://docs.gitlab.com/subscriptions/community_programs/#gitlab-for-open-source
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 automation/gitlab-ci/build.yaml | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index eff96beaa5..463ed2f96d 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -815,3 +815,33 @@ debian-13-riscv64-gcc-randconfig:
     KBUILD_DEFCONFIG: tiny64_defconfig
     RANDCONFIG: y
     <<: *riscv-fixed-randconfig
+
+# macOS build jobs
+.macos-26:
+  <<: *build
+  tags:
+    - saas-macos-medium-m1
+  image: macos-26-xcode-26
+  variables:
+    HOMEBREW_NO_AUTO_UPDATE: 1
+    HOSTCC: clang
+    HYPERVISOR_ONLY: y
+    <<: *gcc
+  script:
+    - brew install ${CROSS_COMPILE}gcc ${CROSS_COMPILE}binutils
+    - alias nproc="sysctl -n hw.ncpu"
+    - ./automation/scripts/build 2>&1 | tee build.log
+
+macos-26-x86_64:
+  extends:
+    - .macos-26
+  variables:
+    XEN_TARGET_ARCH: x86_64
+    CROSS_COMPILE: x86_64-elf-
+
+macos-26-arm64:
+  extends:
+    - .macos-26
+  variables:
+    XEN_TARGET_ARCH: arm64
+    CROSS_COMPILE: aarch64-elf-
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] automation/gitlab: introduce macOS build jobs
Message-Id: <E1wKM6f-00GE1X-1o@xenbits.xenproject.org>
Date: Tue, 05 May 2026 20:11:01 +0000

commit 278953f6c1551e392585b7f2229aa28086bb1f39
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Thu Apr 23 18:19:38 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Tue May 5 20:52:48 2026 +0200

    automation/gitlab: introduce macOS build jobs
    
    With the imminent decommission of CirrusCI we will lose the limited macOS
    build testing done there.  Introduce two Gitlab macOS build jobs that
    reproduce the ones present on CirrusCI.
    
    According to the "Community programs" Gitlab documentation [0] we get
    50,000 compute minutes per month.  The arm64 job takes ~1m 15s, and the
    x86_64 one ~2m.  I think it's likely enough given the amount of minutes we
    have available.  We might need to reconsider if we add more tasks that
    consume compute minutes.
    
    [0] https://docs.gitlab.com/subscriptions/community_programs/#gitlab-for-open-source
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 automation/gitlab-ci/build.yaml | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index eff96beaa5..463ed2f96d 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -815,3 +815,33 @@ debian-13-riscv64-gcc-randconfig:
     KBUILD_DEFCONFIG: tiny64_defconfig
     RANDCONFIG: y
     <<: *riscv-fixed-randconfig
+
+# macOS build jobs
+.macos-26:
+  <<: *build
+  tags:
+    - saas-macos-medium-m1
+  image: macos-26-xcode-26
+  variables:
+    HOMEBREW_NO_AUTO_UPDATE: 1
+    HOSTCC: clang
+    HYPERVISOR_ONLY: y
+    <<: *gcc
+  script:
+    - brew install ${CROSS_COMPILE}gcc ${CROSS_COMPILE}binutils
+    - alias nproc="sysctl -n hw.ncpu"
+    - ./automation/scripts/build 2>&1 | tee build.log
+
+macos-26-x86_64:
+  extends:
+    - .macos-26
+  variables:
+    XEN_TARGET_ARCH: x86_64
+    CROSS_COMPILE: x86_64-elf-
+
+macos-26-arm64:
+  extends:
+    - .macos-26
+  variables:
+    XEN_TARGET_ARCH: arm64
+    CROSS_COMPILE: aarch64-elf-
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: Refresh the Debian 12 cppcheck container
Message-Id: <E1wKbGM-00Gxxw-0z@xenbits.xenproject.org>
Date: Wed, 06 May 2026 12:22:02 +0000

commit e8c1feab33cb28ea066506fea998fc6733b3e9a2
Author:     Javi Merino <javi.merino@cloud.com>
AuthorDate: Mon Oct 21 11:07:54 2024 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 13:14:36 2026 +0100

    CI: Refresh the Debian 12 cppcheck container
    
    Rework the container to derive from bookworm-slim, and to build and run
    cppcheck as a normal user.  User heredocs for readability and use apt-get
    --no-install-recommends to keep the size down.
    
    Changed the libpcre3-dev dependency to libpcre3, as the -dev package
    is only needed for building, not for running.
    
    Signed-off-by: Javi Merino <javi.merino@cloud.com>
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 .../build/debian/12-arm64v8-cppcheck.dockerfile    | 86 ++++++++++++++++++++++
 .../build/debian/bookworm-cppcheck.dockerfile      | 54 --------------
 automation/gitlab-ci/build.yaml                    | 12 +--
 automation/scripts/containerize                    |  2 +-
 4 files changed, 93 insertions(+), 61 deletions(-)

diff --git a/automation/build/debian/12-arm64v8-cppcheck.dockerfile b/automation/build/debian/12-arm64v8-cppcheck.dockerfile
new file mode 100644
index 0000000000..50d2614453
--- /dev/null
+++ b/automation/build/debian/12-arm64v8-cppcheck.dockerfile
@@ -0,0 +1,86 @@
+# syntax=docker/dockerfile:1
+FROM --platform=linux/arm64/v8 debian:bookworm-slim AS builder
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV CPPCHECK_VERSION=2.7
+
+# dependencies for cppcheck build
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    useradd --home /build --create-home user
+
+    apt-get update
+
+    DEPS=(
+        build-essential
+        ca-certificates
+        curl
+        libpcre3-dev
+        python-is-python3
+    )
+
+    apt-get -y --no-install-recommends install "${DEPS[@]}"
+
+    rm -rf /var/lib/apt/lists*
+EOF
+
+WORKDIR /build
+USER user
+
+# cppcheck release build (see cppcheck readme.md)
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    curl -fsSLO https://github.com/danmar/cppcheck/archive/"$CPPCHECK_VERSION".tar.gz
+    echo "5fd20549bb2fabf9a8026f772779d8cc6a5782c8f17500408529f7747afbc526  ${CPPCHECK_VERSION}.tar.gz" | sha256sum -c -
+
+    tar oxf "$CPPCHECK_VERSION".tar.gz
+    cd cppcheck-"$CPPCHECK_VERSION"
+
+    MAKE_OPTS=(
+        MATCHCOMPILER=yes
+        DESTDIR=/build/out
+        FILESDIR="/usr/share/cppcheck"
+        HAVE_RULES=yes CXXFLAGS="-O2 -DNDEBUG -Wall -Wno-sign-compare -Wno-unused-function"
+    )
+    make install -j$(nproc) "${MAKE_OPTS[@]}"
+EOF
+
+FROM --platform=linux/arm64/v8 debian:bookworm-slim
+COPY --from=builder /build/out/usr/bin/cppcheck /usr/bin/cppcheck
+COPY --from=builder /build/out/usr/share/cppcheck /usr/share/cppcheck
+
+LABEL maintainer.name="The Xen Project"
+LABEL maintainer.email="xen-devel@lists.xenproject.org"
+
+ENV DEBIAN_FRONTEND=noninteractive
+
+# dependencies for cppcheck analysis including Xen-only build/cross-build
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    useradd --create-home user
+
+    apt-get update
+
+    DEPS=(
+        bison
+        build-essential
+        python-is-python3
+        libpcre3
+        flex
+        gcc-arm-linux-gnueabihf
+        gcc-x86-64-linux-gnu
+    )
+
+    apt-get --yes --no-install-recommends install "${DEPS[@]}"
+
+    rm -rf /var/lib/apt/lists*
+EOF
+
+USER user
+WORKDIR /build
diff --git a/automation/build/debian/bookworm-cppcheck.dockerfile b/automation/build/debian/bookworm-cppcheck.dockerfile
deleted file mode 100644
index fe4cd4a1aa..0000000000
--- a/automation/build/debian/bookworm-cppcheck.dockerfile
+++ /dev/null
@@ -1,54 +0,0 @@
-# syntax=docker/dockerfile:1
-FROM --platform=linux/arm64/v8 debian:bookworm AS builder
-
-ENV DEBIAN_FRONTEND=noninteractive
-ENV CPPCHECK_VERSION=2.7
-ENV USER root
-
-# dependencies for cppcheck build
-RUN apt-get update && \
-    apt-get --quiet --yes install \
-        curl \
-        build-essential \
-        python-is-python3 \
-        libpcre3-dev
-
-RUN mkdir /build
-WORKDIR /build
-
-# cppcheck release build (see cppcheck readme.md)
-RUN curl -fsSLO https://github.com/danmar/cppcheck/archive/"$CPPCHECK_VERSION".tar.gz && \
-    tar xvzf "$CPPCHECK_VERSION".tar.gz && \
-    cd cppcheck-"$CPPCHECK_VERSION" && \
-    make install -j$(nproc) \
-        MATCHCOMPILER=yes \
-        FILESDIR=/usr/share/cppcheck \
-        HAVE_RULES=yes CXXFLAGS="-O2 -DNDEBUG -Wall -Wno-sign-compare -Wno-unused-function"
-
-FROM --platform=linux/arm64/v8 debian:bookworm
-COPY --from=builder /usr/bin/cppcheck /usr/bin/cppcheck
-COPY --from=builder /usr/share/cppcheck /usr/share/cppcheck
-
-LABEL maintainer.name="The Xen Project" \
-      maintainer.email="xen-devel@lists.xenproject.org"
-
-ENV DEBIAN_FRONTEND=noninteractive
-ENV USER root
-
-RUN mkdir /build
-WORKDIR /build
-
-# dependencies for cppcheck analysis including Xen-only build/cross-build
-RUN apt-get update && \
-    apt-get --quiet --yes install \
-        build-essential \
-        python-is-python3 \
-        libpcre3-dev \
-        flex \
-        bison \
-        gcc-arm-linux-gnueabihf \
-        gcc-x86-64-linux-gnu \
-        && \
-        apt-get autoremove -y && \
-        apt-get clean && \
-        rm -rf /var/lib/apt/lists* /tmp/* /var/tmp/*
diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 463ed2f96d..f058957291 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -510,26 +510,26 @@ yocto-qemux86-64:
 
 # Cppcheck analysis jobs
 
-debian-bookworm-gcc-cppcheck:
+debian-12-x86_64-gcc-cppcheck:
   extends: .gcc-x86-64-cross-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CROSS_COMPILE: /usr/bin/x86_64-linux-gnu-
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
-debian-bookworm-gcc-arm32-cppcheck:
+debian-12-arm32-gcc-cppcheck:
   extends: .gcc-arm32-cross-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CROSS_COMPILE: /usr/bin/arm-linux-gnueabihf-
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
-debian-bookworm-gcc-arm64-cppcheck:
+debian-12-arm64-gcc-cppcheck:
   extends: .gcc-arm64-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
diff --git a/automation/scripts/containerize b/automation/scripts/containerize
index 743567cb77..ad3e237270 100755
--- a/automation/scripts/containerize
+++ b/automation/scripts/containerize
@@ -40,7 +40,7 @@ case "_${CONTAINER}" in
     _bookworm-i386|_bookworm-x86_32) CONTAINER="${BASE}/debian:12-x86_32" ;;
     _bookworm-arm64v8-arm32-gcc) CONTAINER="${BASE}/debian:bookworm-arm64v8-arm32-gcc" ;;
     _bookworm-arm64v8) CONTAINER="${BASE}/debian:bookworm-arm64v8" ;;
-    _bookworm-cppcheck) CONTAINER="${BASE}/debian:bookworm-cppcheck" ;;
+    _bookworm-cppcheck) CONTAINER="${BASE}/debian:12-arm64v8-cppcheck" ;;
     _opensuse-leap|_leap) CONTAINER="${BASE}/opensuse:leap-15.6-x86_64" ;;
     _opensuse-tumbleweed|_tumbleweed) CONTAINER="${BASE}/opensuse:tumbleweed-x86_64" ;;
     _xenial) CONTAINER="${BASE}/ubuntu:16.04-x86_64" ;;
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xvmalloc: adjust XVFREE() ordering
Message-Id: <E1wKcCQ-00H1Fy-1O@xenbits.xenproject.org>
Date: Wed, 06 May 2026 13:22:02 +0000

commit 96ffccef5a5f598ffbd263971b92132391f1606a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed May 6 13:59:37 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:11 2026 +0200

    xvmalloc: adjust XVFREE() ordering
    
    What c4f427ec879e ("xen: Swap order of actions in the FREE*() macros") did
    should have been done right away when XVFREE() was introduced.
    
    Fixes: 9102fcd9579f ("mm: introduce xvmalloc() et al and use for grant table allocations")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/include/xen/xvmalloc.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/include/xen/xvmalloc.h b/xen/include/xen/xvmalloc.h
index 110b10e88c..83c9d4dea2 100644
--- a/xen/include/xen/xvmalloc.h
+++ b/xen/include/xen/xvmalloc.h
@@ -71,8 +71,9 @@ void *_xvrealloc(void *va, size_t size, unsigned int align);
 
 /* Free an allocation, and zero the pointer to it. */
 #define XVFREE(p) do { \
-    xvfree(p);         \
+    void *_ptr_ = (p); \
     (p) = NULL;        \
+    xvfree(_ptr_);     \
 } while ( false )
 
 static inline void *_xvmalloc_array(
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] EFI: adjust cfg file buffer freeing
Message-Id: <E1wKcCa-00H1Gg-1m@xenbits.xenproject.org>
Date: Wed, 06 May 2026 13:22:12 +0000

commit 4ff927133ebc32498fd4af49a8025a846cfe1dc6
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed May 6 14:00:19 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:11 2026 +0200

    EFI: adjust cfg file buffer freeing
    
    The boot services FreePages() needs passing the size. Since we allocated
    one more byte to put a trailing nul there, we also need to bump the size
    passed there. Make a small helper function to centralize this.
    
    Note that there's no permanent memory leak because of the oversight: The
    allocation is done using EfiLoaderData, and all memory of that type is
    later reclaimed anyway.
    
    Fixes: df75f77092c1 ("EFI: avoid OOB config file reads")
    Reported-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 xen/common/efi/boot.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index b44762878b..9ea2183c0b 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -778,6 +778,16 @@ static void __init efi_relocate_esrt(EFI_SYSTEM_TABLE *SystemTable)
  */
 #include "efi-boot.h"
 
+static void __init free_cfg(void)
+{
+    if ( !cfg.need_to_free )
+        return;
+
+    /* One extra byte was allocated to put a nul character there. */
+    efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size + 1));
+    cfg.need_to_free = false;
+}
+
 void __init noreturn blexit(const CHAR16 *str)
 {
     if ( str )
@@ -787,8 +797,7 @@ void __init noreturn blexit(const CHAR16 *str)
     if ( !efi_bs )
         efi_arch_halt();
 
-    if ( cfg.need_to_free )
-        efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
+    free_cfg();
     if ( kernel.need_to_free )
         efi_bs->FreePages(kernel.addr, PFN_UP(kernel.size));
     if ( ramdisk.need_to_free )
@@ -1557,11 +1566,7 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
             name.s = get_value(&cfg, "global", "chain");
             if ( !name.s )
                 break;
-            if ( cfg.need_to_free )
-            {
-                efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
-                cfg.need_to_free = false;
-            }
+            free_cfg();
             if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) )
             {
                 PrintStr(L"Chained configuration file '");
@@ -1631,11 +1636,7 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
 
         efi_arch_cfg_file_late(loaded_image, dir_handle, section.s);
 
-        if ( cfg.need_to_free )
-        {
-            efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
-            cfg.need_to_free = false;
-        }
+        free_cfg();
 
         if ( dir_handle )
             dir_handle->Close(dir_handle);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xsm/flask: Fix undefined behaviour in avc_dump_av()
Message-Id: <E1wKcCk-00H1H2-2E@xenbits.xenproject.org>
Date: Wed, 06 May 2026 13:22:22 +0000

commit 4f9457ece11a6231b7a17a11a873b8b4b9376fdc
Author:     Dmytro Prokopchuk <dmytro_prokopchuk1@epam.com>
AuthorDate: Wed May 6 14:00:58 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:18 2026 +0200

    xsm/flask: Fix undefined behaviour in avc_dump_av()
    
    When booting Xen with CONFIG_USBAN=y and CONFIG_XSM_FLASK=y,
    UBSAN reports undefined behaviour in avc_dump_av() due to a left
    shift on a signed int:
    
    (XEN) [    1.104348] ================================================================================
    (XEN) [    1.105096] UBSAN: Undefined behaviour in xsm/flask/avc.c:184:14
    (XEN) [    1.106052] left shift of 1073741824 by 1 places cannot be represented in type 'int'
    (XEN) [    1.107546] Xen WARN at common/ubsan/ubsan.c:176
    (XEN) [    1.108295] ----[ Xen-4.21.1  arm64  debug=y ubsan=y  Not tainted ]----
    (XEN) [    1.108848] CPU:    0
    (XEN) [    1.109147] PC:     00000a00002f64fc ubsan.c#ubsan_epilogue+0x10/0xd4
    [...]
    (XEN) [    1.146320] Xen call trace:
    (XEN) [    1.146663]    [<00000a00002f64fc>] ubsan.c#ubsan_epilogue+0x10/0xd4 (PC)
    (XEN) [    1.147227]    [<00000a00002f7bc4>] __ubsan_handle_shift_out_of_bounds+0x1a0/0x290 (LR)
    (XEN) [    1.147868]
    (XEN) [    1.148177] ================================================================================
    
    This can be solved by making 'perm' an unsigned 32-bit type (u32).
    
    Signed-off-by: Dmytro Prokopchuk <dmytro_prokopchuk1@epam.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 xen/xsm/flask/avc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/xsm/flask/avc.c b/xen/xsm/flask/avc.c
index 3d39e55cae..6e1972d21b 100644
--- a/xen/xsm/flask/avc.c
+++ b/xen/xsm/flask/avc.c
@@ -152,7 +152,8 @@ static void __attribute__ ((format (printf, 2, 3)))
  */
 static void avc_dump_av(struct avc_dump_buf *buf, u16 tclass, u32 av)
 {
-    int i, i2, perm;
+    int i, i2;
+    uint32_t perm;
 
     if ( av == 0 )
     {
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: Refresh the Debian 12 cppcheck container
Message-Id: <E1wKe4X-00H8oB-29@xenbits.xenproject.org>
Date: Wed, 06 May 2026 15:22:01 +0000

commit e8c1feab33cb28ea066506fea998fc6733b3e9a2
Author:     Javi Merino <javi.merino@cloud.com>
AuthorDate: Mon Oct 21 11:07:54 2024 +0100
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 13:14:36 2026 +0100

    CI: Refresh the Debian 12 cppcheck container
    
    Rework the container to derive from bookworm-slim, and to build and run
    cppcheck as a normal user.  User heredocs for readability and use apt-get
    --no-install-recommends to keep the size down.
    
    Changed the libpcre3-dev dependency to libpcre3, as the -dev package
    is only needed for building, not for running.
    
    Signed-off-by: Javi Merino <javi.merino@cloud.com>
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 .../build/debian/12-arm64v8-cppcheck.dockerfile    | 86 ++++++++++++++++++++++
 .../build/debian/bookworm-cppcheck.dockerfile      | 54 --------------
 automation/gitlab-ci/build.yaml                    | 12 +--
 automation/scripts/containerize                    |  2 +-
 4 files changed, 93 insertions(+), 61 deletions(-)

diff --git a/automation/build/debian/12-arm64v8-cppcheck.dockerfile b/automation/build/debian/12-arm64v8-cppcheck.dockerfile
new file mode 100644
index 0000000000..50d2614453
--- /dev/null
+++ b/automation/build/debian/12-arm64v8-cppcheck.dockerfile
@@ -0,0 +1,86 @@
+# syntax=docker/dockerfile:1
+FROM --platform=linux/arm64/v8 debian:bookworm-slim AS builder
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV CPPCHECK_VERSION=2.7
+
+# dependencies for cppcheck build
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    useradd --home /build --create-home user
+
+    apt-get update
+
+    DEPS=(
+        build-essential
+        ca-certificates
+        curl
+        libpcre3-dev
+        python-is-python3
+    )
+
+    apt-get -y --no-install-recommends install "${DEPS[@]}"
+
+    rm -rf /var/lib/apt/lists*
+EOF
+
+WORKDIR /build
+USER user
+
+# cppcheck release build (see cppcheck readme.md)
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    curl -fsSLO https://github.com/danmar/cppcheck/archive/"$CPPCHECK_VERSION".tar.gz
+    echo "5fd20549bb2fabf9a8026f772779d8cc6a5782c8f17500408529f7747afbc526  ${CPPCHECK_VERSION}.tar.gz" | sha256sum -c -
+
+    tar oxf "$CPPCHECK_VERSION".tar.gz
+    cd cppcheck-"$CPPCHECK_VERSION"
+
+    MAKE_OPTS=(
+        MATCHCOMPILER=yes
+        DESTDIR=/build/out
+        FILESDIR="/usr/share/cppcheck"
+        HAVE_RULES=yes CXXFLAGS="-O2 -DNDEBUG -Wall -Wno-sign-compare -Wno-unused-function"
+    )
+    make install -j$(nproc) "${MAKE_OPTS[@]}"
+EOF
+
+FROM --platform=linux/arm64/v8 debian:bookworm-slim
+COPY --from=builder /build/out/usr/bin/cppcheck /usr/bin/cppcheck
+COPY --from=builder /build/out/usr/share/cppcheck /usr/share/cppcheck
+
+LABEL maintainer.name="The Xen Project"
+LABEL maintainer.email="xen-devel@lists.xenproject.org"
+
+ENV DEBIAN_FRONTEND=noninteractive
+
+# dependencies for cppcheck analysis including Xen-only build/cross-build
+RUN <<EOF
+#!/bin/bash
+    set -eu
+
+    useradd --create-home user
+
+    apt-get update
+
+    DEPS=(
+        bison
+        build-essential
+        python-is-python3
+        libpcre3
+        flex
+        gcc-arm-linux-gnueabihf
+        gcc-x86-64-linux-gnu
+    )
+
+    apt-get --yes --no-install-recommends install "${DEPS[@]}"
+
+    rm -rf /var/lib/apt/lists*
+EOF
+
+USER user
+WORKDIR /build
diff --git a/automation/build/debian/bookworm-cppcheck.dockerfile b/automation/build/debian/bookworm-cppcheck.dockerfile
deleted file mode 100644
index fe4cd4a1aa..0000000000
--- a/automation/build/debian/bookworm-cppcheck.dockerfile
+++ /dev/null
@@ -1,54 +0,0 @@
-# syntax=docker/dockerfile:1
-FROM --platform=linux/arm64/v8 debian:bookworm AS builder
-
-ENV DEBIAN_FRONTEND=noninteractive
-ENV CPPCHECK_VERSION=2.7
-ENV USER root
-
-# dependencies for cppcheck build
-RUN apt-get update && \
-    apt-get --quiet --yes install \
-        curl \
-        build-essential \
-        python-is-python3 \
-        libpcre3-dev
-
-RUN mkdir /build
-WORKDIR /build
-
-# cppcheck release build (see cppcheck readme.md)
-RUN curl -fsSLO https://github.com/danmar/cppcheck/archive/"$CPPCHECK_VERSION".tar.gz && \
-    tar xvzf "$CPPCHECK_VERSION".tar.gz && \
-    cd cppcheck-"$CPPCHECK_VERSION" && \
-    make install -j$(nproc) \
-        MATCHCOMPILER=yes \
-        FILESDIR=/usr/share/cppcheck \
-        HAVE_RULES=yes CXXFLAGS="-O2 -DNDEBUG -Wall -Wno-sign-compare -Wno-unused-function"
-
-FROM --platform=linux/arm64/v8 debian:bookworm
-COPY --from=builder /usr/bin/cppcheck /usr/bin/cppcheck
-COPY --from=builder /usr/share/cppcheck /usr/share/cppcheck
-
-LABEL maintainer.name="The Xen Project" \
-      maintainer.email="xen-devel@lists.xenproject.org"
-
-ENV DEBIAN_FRONTEND=noninteractive
-ENV USER root
-
-RUN mkdir /build
-WORKDIR /build
-
-# dependencies for cppcheck analysis including Xen-only build/cross-build
-RUN apt-get update && \
-    apt-get --quiet --yes install \
-        build-essential \
-        python-is-python3 \
-        libpcre3-dev \
-        flex \
-        bison \
-        gcc-arm-linux-gnueabihf \
-        gcc-x86-64-linux-gnu \
-        && \
-        apt-get autoremove -y && \
-        apt-get clean && \
-        rm -rf /var/lib/apt/lists* /tmp/* /var/tmp/*
diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 463ed2f96d..f058957291 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -510,26 +510,26 @@ yocto-qemux86-64:
 
 # Cppcheck analysis jobs
 
-debian-bookworm-gcc-cppcheck:
+debian-12-x86_64-gcc-cppcheck:
   extends: .gcc-x86-64-cross-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CROSS_COMPILE: /usr/bin/x86_64-linux-gnu-
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
-debian-bookworm-gcc-arm32-cppcheck:
+debian-12-arm32-gcc-cppcheck:
   extends: .gcc-arm32-cross-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CROSS_COMPILE: /usr/bin/arm-linux-gnueabihf-
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
-debian-bookworm-gcc-arm64-cppcheck:
+debian-12-arm64-gcc-cppcheck:
   extends: .gcc-arm64-build
   variables:
-    CONTAINER: debian:bookworm-cppcheck
+    CONTAINER: debian:12-arm64v8-cppcheck
     CPPCHECK: y
     HYPERVISOR_ONLY: y
 
diff --git a/automation/scripts/containerize b/automation/scripts/containerize
index 743567cb77..ad3e237270 100755
--- a/automation/scripts/containerize
+++ b/automation/scripts/containerize
@@ -40,7 +40,7 @@ case "_${CONTAINER}" in
     _bookworm-i386|_bookworm-x86_32) CONTAINER="${BASE}/debian:12-x86_32" ;;
     _bookworm-arm64v8-arm32-gcc) CONTAINER="${BASE}/debian:bookworm-arm64v8-arm32-gcc" ;;
     _bookworm-arm64v8) CONTAINER="${BASE}/debian:bookworm-arm64v8" ;;
-    _bookworm-cppcheck) CONTAINER="${BASE}/debian:bookworm-cppcheck" ;;
+    _bookworm-cppcheck) CONTAINER="${BASE}/debian:12-arm64v8-cppcheck" ;;
     _opensuse-leap|_leap) CONTAINER="${BASE}/opensuse:leap-15.6-x86_64" ;;
     _opensuse-tumbleweed|_tumbleweed) CONTAINER="${BASE}/opensuse:tumbleweed-x86_64" ;;
     _xenial) CONTAINER="${BASE}/ubuntu:16.04-x86_64" ;;
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xvmalloc: adjust XVFREE() ordering
Message-Id: <E1wKf0b-00HCOr-36@xenbits.xenproject.org>
Date: Wed, 06 May 2026 16:22:01 +0000

commit 96ffccef5a5f598ffbd263971b92132391f1606a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed May 6 13:59:37 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:11 2026 +0200

    xvmalloc: adjust XVFREE() ordering
    
    What c4f427ec879e ("xen: Swap order of actions in the FREE*() macros") did
    should have been done right away when XVFREE() was introduced.
    
    Fixes: 9102fcd9579f ("mm: introduce xvmalloc() et al and use for grant table allocations")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/include/xen/xvmalloc.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/include/xen/xvmalloc.h b/xen/include/xen/xvmalloc.h
index 110b10e88c..83c9d4dea2 100644
--- a/xen/include/xen/xvmalloc.h
+++ b/xen/include/xen/xvmalloc.h
@@ -71,8 +71,9 @@ void *_xvrealloc(void *va, size_t size, unsigned int align);
 
 /* Free an allocation, and zero the pointer to it. */
 #define XVFREE(p) do { \
-    xvfree(p);         \
+    void *_ptr_ = (p); \
     (p) = NULL;        \
+    xvfree(_ptr_);     \
 } while ( false )
 
 static inline void *_xvmalloc_array(
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] EFI: adjust cfg file buffer freeing
Message-Id: <E1wKf0m-00HCPZ-0B@xenbits.xenproject.org>
Date: Wed, 06 May 2026 16:22:12 +0000

commit 4ff927133ebc32498fd4af49a8025a846cfe1dc6
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Wed May 6 14:00:19 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:11 2026 +0200

    EFI: adjust cfg file buffer freeing
    
    The boot services FreePages() needs passing the size. Since we allocated
    one more byte to put a trailing nul there, we also need to bump the size
    passed there. Make a small helper function to centralize this.
    
    Note that there's no permanent memory leak because of the oversight: The
    allocation is done using EfiLoaderData, and all memory of that type is
    later reclaimed anyway.
    
    Fixes: df75f77092c1 ("EFI: avoid OOB config file reads")
    Reported-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Bernhard Kaindl <bernhard.kaindl@citrix.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 xen/common/efi/boot.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index b44762878b..9ea2183c0b 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -778,6 +778,16 @@ static void __init efi_relocate_esrt(EFI_SYSTEM_TABLE *SystemTable)
  */
 #include "efi-boot.h"
 
+static void __init free_cfg(void)
+{
+    if ( !cfg.need_to_free )
+        return;
+
+    /* One extra byte was allocated to put a nul character there. */
+    efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size + 1));
+    cfg.need_to_free = false;
+}
+
 void __init noreturn blexit(const CHAR16 *str)
 {
     if ( str )
@@ -787,8 +797,7 @@ void __init noreturn blexit(const CHAR16 *str)
     if ( !efi_bs )
         efi_arch_halt();
 
-    if ( cfg.need_to_free )
-        efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
+    free_cfg();
     if ( kernel.need_to_free )
         efi_bs->FreePages(kernel.addr, PFN_UP(kernel.size));
     if ( ramdisk.need_to_free )
@@ -1557,11 +1566,7 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
             name.s = get_value(&cfg, "global", "chain");
             if ( !name.s )
                 break;
-            if ( cfg.need_to_free )
-            {
-                efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
-                cfg.need_to_free = false;
-            }
+            free_cfg();
             if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) )
             {
                 PrintStr(L"Chained configuration file '");
@@ -1631,11 +1636,7 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
 
         efi_arch_cfg_file_late(loaded_image, dir_handle, section.s);
 
-        if ( cfg.need_to_free )
-        {
-            efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
-            cfg.need_to_free = false;
-        }
+        free_cfg();
 
         if ( dir_handle )
             dir_handle->Close(dir_handle);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xsm/flask: Fix undefined behaviour in avc_dump_av()
Message-Id: <E1wKf0w-00HCSh-0X@xenbits.xenproject.org>
Date: Wed, 06 May 2026 16:22:22 +0000

commit 4f9457ece11a6231b7a17a11a873b8b4b9376fdc
Author:     Dmytro Prokopchuk <dmytro_prokopchuk1@epam.com>
AuthorDate: Wed May 6 14:00:58 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Wed May 6 15:11:18 2026 +0200

    xsm/flask: Fix undefined behaviour in avc_dump_av()
    
    When booting Xen with CONFIG_USBAN=y and CONFIG_XSM_FLASK=y,
    UBSAN reports undefined behaviour in avc_dump_av() due to a left
    shift on a signed int:
    
    (XEN) [    1.104348] ================================================================================
    (XEN) [    1.105096] UBSAN: Undefined behaviour in xsm/flask/avc.c:184:14
    (XEN) [    1.106052] left shift of 1073741824 by 1 places cannot be represented in type 'int'
    (XEN) [    1.107546] Xen WARN at common/ubsan/ubsan.c:176
    (XEN) [    1.108295] ----[ Xen-4.21.1  arm64  debug=y ubsan=y  Not tainted ]----
    (XEN) [    1.108848] CPU:    0
    (XEN) [    1.109147] PC:     00000a00002f64fc ubsan.c#ubsan_epilogue+0x10/0xd4
    [...]
    (XEN) [    1.146320] Xen call trace:
    (XEN) [    1.146663]    [<00000a00002f64fc>] ubsan.c#ubsan_epilogue+0x10/0xd4 (PC)
    (XEN) [    1.147227]    [<00000a00002f7bc4>] __ubsan_handle_shift_out_of_bounds+0x1a0/0x290 (LR)
    (XEN) [    1.147868]
    (XEN) [    1.148177] ================================================================================
    
    This can be solved by making 'perm' an unsigned 32-bit type (u32).
    
    Signed-off-by: Dmytro Prokopchuk <dmytro_prokopchuk1@epam.com>
    Acked-by: Daniel P. Smith <dpsmith@apertussolutions.com>
---
 xen/xsm/flask/avc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/xsm/flask/avc.c b/xen/xsm/flask/avc.c
index 3d39e55cae..6e1972d21b 100644
--- a/xen/xsm/flask/avc.c
+++ b/xen/xsm/flask/avc.c
@@ -152,7 +152,8 @@ static void __attribute__ ((format (printf, 2, 3)))
  */
 static void avc_dump_av(struct avc_dump_buf *buf, u16 tclass, u32 av)
 {
-    int i, i2, perm;
+    int i, i2;
+    uint32_t perm;
 
     if ( av == 0 )
     {
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] iommu/amd-vi: do not zero IOMMU MMIO region
Message-Id: <E1wKgSb-00HOGa-2X@xenbits.xenproject.org>
Date: Wed, 06 May 2026 17:55:01 +0000

commit bdb30883f3528676f8b736e4ec0e475914289993
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue May 5 15:13:28 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Wed May 6 18:56:59 2026 +0200

    iommu/amd-vi: do not zero IOMMU MMIO region
    
    Attempting to memset the whole IOMMU MMIO region to zero is dangerous to
    say the least.  We don't know which registers might be there, nor which
    values might be safe for those registers.  On a forthcoming platform doing
    the zeroing of the MMIO region does put the IOMMU in a broken state, which
    is not recoverable by the IOMMU initialization procedure in Xen.
    
    Instead just zero the control register, which mimics the current behavior
    with regards to how the control register is handled, and ensures the IOMU
    setup is done with the unit disabled.  This approach will need revisiting
    in order to support Preboot DMA Protection.
    
    Fold map_iommu_mmio_region() into its only caller, as the function body is
    just an ioremap() call after the removal of the memset().
    
    Fixes: 0700c962ac2d ("Add AMD IOMMU support into hypervisor")
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper@citrix.com>
---
 xen/drivers/passthrough/amd/iommu_init.c | 33 ++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c
index d77dd85112..e0c8925c33 100644
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -42,18 +42,6 @@ static bool iommu_has_ht_flag(struct amd_iommu *iommu, u8 mask)
     return iommu->ht_flags & mask;
 }
 
-static int __init map_iommu_mmio_region(struct amd_iommu *iommu)
-{
-    iommu->mmio_base = ioremap(iommu->mmio_base_phys,
-                               IOMMU_MMIO_REGION_LENGTH);
-    if ( !iommu->mmio_base )
-        return -ENOMEM;
-
-    memset(iommu->mmio_base, 0, IOMMU_MMIO_REGION_LENGTH);
-
-    return 0;
-}
-
 static void __init unmap_iommu_mmio_region(struct amd_iommu *iommu)
 {
     if ( iommu->mmio_base )
@@ -1367,11 +1355,14 @@ static int __init amd_iommu_prepare_one(struct amd_iommu *iommu)
 {
     int rc = alloc_ivrs_mappings(iommu->sbdf.seg);
 
-    if ( !rc )
-        rc = map_iommu_mmio_region(iommu);
     if ( rc )
         return rc;
 
+    iommu->mmio_base = ioremap(iommu->mmio_base_phys,
+                               IOMMU_MMIO_REGION_LENGTH);
+    if ( !iommu->mmio_base )
+        return -ENOMEM;
+
     get_iommu_features(iommu);
 
     /*
@@ -1381,6 +1372,20 @@ static int __init amd_iommu_prepare_one(struct amd_iommu *iommu)
     if ( amd_iommu_max_paging_mode < amd_iommu_min_paging_mode )
         return -ERANGE;
 
+    /*
+     * Check whether the IOMMU is already enabled and unconditionally disable
+     * it (zero the control register) ahead of Xen setup.  Needs to be
+     * revisited to support Preboot DMA Protection.
+     */
+    iommu->ctrl.raw = readq(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
+    if ( iommu->ctrl.iommu_en )
+        printk(XENLOG_WARNING
+               "AMD-Vi: IOMMU %pp enabled by firmware (ctrl %016lx)\n",
+               &iommu->sbdf, iommu->ctrl.raw);
+
+    iommu->ctrl.raw = 0;
+    writeq(0, iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
+
     return 0;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] iommu/amd-vi: do not zero IOMMU MMIO region
Message-Id: <E1wKhon-00HS8w-2K@xenbits.xenproject.org>
Date: Wed, 06 May 2026 19:22:01 +0000

commit bdb30883f3528676f8b736e4ec0e475914289993
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Tue May 5 15:13:28 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Wed May 6 18:56:59 2026 +0200

    iommu/amd-vi: do not zero IOMMU MMIO region
    
    Attempting to memset the whole IOMMU MMIO region to zero is dangerous to
    say the least.  We don't know which registers might be there, nor which
    values might be safe for those registers.  On a forthcoming platform doing
    the zeroing of the MMIO region does put the IOMMU in a broken state, which
    is not recoverable by the IOMMU initialization procedure in Xen.
    
    Instead just zero the control register, which mimics the current behavior
    with regards to how the control register is handled, and ensures the IOMU
    setup is done with the unit disabled.  This approach will need revisiting
    in order to support Preboot DMA Protection.
    
    Fold map_iommu_mmio_region() into its only caller, as the function body is
    just an ioremap() call after the removal of the memset().
    
    Fixes: 0700c962ac2d ("Add AMD IOMMU support into hypervisor")
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Andrew Cooper <andrew.cooper@citrix.com>
---
 xen/drivers/passthrough/amd/iommu_init.c | 33 ++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c
index d77dd85112..e0c8925c33 100644
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -42,18 +42,6 @@ static bool iommu_has_ht_flag(struct amd_iommu *iommu, u8 mask)
     return iommu->ht_flags & mask;
 }
 
-static int __init map_iommu_mmio_region(struct amd_iommu *iommu)
-{
-    iommu->mmio_base = ioremap(iommu->mmio_base_phys,
-                               IOMMU_MMIO_REGION_LENGTH);
-    if ( !iommu->mmio_base )
-        return -ENOMEM;
-
-    memset(iommu->mmio_base, 0, IOMMU_MMIO_REGION_LENGTH);
-
-    return 0;
-}
-
 static void __init unmap_iommu_mmio_region(struct amd_iommu *iommu)
 {
     if ( iommu->mmio_base )
@@ -1367,11 +1355,14 @@ static int __init amd_iommu_prepare_one(struct amd_iommu *iommu)
 {
     int rc = alloc_ivrs_mappings(iommu->sbdf.seg);
 
-    if ( !rc )
-        rc = map_iommu_mmio_region(iommu);
     if ( rc )
         return rc;
 
+    iommu->mmio_base = ioremap(iommu->mmio_base_phys,
+                               IOMMU_MMIO_REGION_LENGTH);
+    if ( !iommu->mmio_base )
+        return -ENOMEM;
+
     get_iommu_features(iommu);
 
     /*
@@ -1381,6 +1372,20 @@ static int __init amd_iommu_prepare_one(struct amd_iommu *iommu)
     if ( amd_iommu_max_paging_mode < amd_iommu_min_paging_mode )
         return -ERANGE;
 
+    /*
+     * Check whether the IOMMU is already enabled and unconditionally disable
+     * it (zero the control register) ahead of Xen setup.  Needs to be
+     * revisited to support Preboot DMA Protection.
+     */
+    iommu->ctrl.raw = readq(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
+    if ( iommu->ctrl.iommu_en )
+        printk(XENLOG_WARNING
+               "AMD-Vi: IOMMU %pp enabled by firmware (ctrl %016lx)\n",
+               &iommu->sbdf, iommu->ctrl.raw);
+
+    iommu->ctrl.raw = 0;
+    writeq(0, iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
+
     return 0;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen: introduce CONFIG_HAS_DOMAIN_TYPE
Message-Id: <E1wKyfx-000l8j-1X@xenbits.xenproject.org>
Date: Thu, 07 May 2026 13:22:01 +0000

commit 9f976dec039c2a5ddeb389efbaae8d726e17e84a
Author:     Oleksii Kurochko <oleksii.kurochko@gmail.com>
AuthorDate: Thu May 7 10:58:23 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu May 7 13:26:52 2026 +0200

    xen: introduce CONFIG_HAS_DOMAIN_TYPE
    
    As domain type is part of common code now there is no any reason
    to have architecture-specific set_domain_type() functions so
    it is dropped.
    
    Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE
    for consistency. Also, drop and add some parentheses to be aligned
    with the similar if() below.
    
    x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as
    x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no
    longer builds, the fallback is currently only relevant for arm32.
    
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/arm/Kconfig               |  1 +
 xen/arch/arm/arm64/domctl.c        |  4 ++--
 xen/arch/arm/dom0less-build.c      | 14 --------------
 xen/arch/arm/domain_build.c        | 12 +++++-------
 xen/arch/arm/include/asm/domain.h  | 16 ----------------
 xen/arch/arm/include/asm/kernel.h  |  4 ----
 xen/arch/arm/kernel.c              | 16 ++++++++--------
 xen/common/Kconfig                 |  3 +++
 xen/include/xen/dom0less-build.h   |  2 --
 xen/include/xen/domain.h           | 13 +++++++++++++
 xen/include/xen/fdt-domain-build.h | 10 ++++++++++
 xen/include/xen/fdt-kernel.h       |  5 +++++
 xen/include/xen/sched.h            |  4 ++++
 13 files changed, 51 insertions(+), 53 deletions(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 2f2b501fda..79622b46a1 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -7,6 +7,7 @@ config ARM_64
 	def_bool y
 	depends on !ARM_32
 	select 64BIT
+	select HAS_DOMAIN_TYPE
 	select HAS_FAST_MULTIPLY
 	select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH
 
diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c
index 8720d126c9..9e9a29eb1e 100644
--- a/xen/arch/arm/arm64/domctl.c
+++ b/xen/arch/arm/arm64/domctl.c
@@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type)
         return -EINVAL;
     if ( domain_tot_pages(d) != 0 )
         return -EBUSY;
-    if ( d->arch.type == type )
+    if ( d->type == type )
         return 0;
 
-    d->arch.type = type;
+    d->type = type;
 
     if ( is_64bit_domain(d) )
         for_each_vcpu(d, v)
diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 4181c10538..6f73c65e51 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo)
     return 0;
 }
 
-/* TODO: make arch.type generic ? */
-#ifdef CONFIG_ARM_64
-void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
-{
-    /* type must be set before allocate memory */
-    d->arch.type = kinfo->arch.type;
-}
-#else
-void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
-{
-    /* Nothing to do */
-}
-#endif
-
 int __init init_vuart(struct domain *d, struct kernel_info *kinfo,
                       const struct dt_device_node *node)
 {
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a3ff701023..ad665cd3c0 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1771,15 +1771,15 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo)
     BUG_ON(d->vcpu[0] == NULL);
     BUG_ON(v->is_initialised);
 
-#ifdef CONFIG_ARM_64
+#ifdef CONFIG_HAS_DOMAIN_TYPE
     /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */
-    if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT )
+    if ( !cpu_has_el1_32 && (kinfo->type == DOMAIN_32BIT) )
     {
         printk("Platform does not support 32-bit domain\n");
         return -EINVAL;
     }
 
-    if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) )
+    if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) )
     {
         printk("SVE is not available for 32-bit domain\n");
         return -EINVAL;
@@ -1893,10 +1893,8 @@ int __init construct_hwdom(struct kernel_info *kinfo,
 
     iommu_hwdom_init(d);
 
-#ifdef CONFIG_ARM_64
-    /* type must be set before allocate_memory */
-    d->arch.type = kinfo->arch.type;
-#endif
+    set_domain_type(d, kinfo);
+
     find_gnttab_region(d, kinfo);
     if ( is_domain_direct_mapped(d) )
         allocate_memory_11(d, kinfo);
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index ffe5d0d9f0..b24f02d269 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -18,18 +18,6 @@ struct hvm_domain
     uint64_t              params[HVM_NR_PARAMS];
 };
 
-#ifdef CONFIG_ARM_64
-enum domain_type {
-    DOMAIN_32BIT,
-    DOMAIN_64BIT,
-};
-#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT)
-#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT)
-#else
-#define is_32bit_domain(d) (1)
-#define is_64bit_domain(d) (0)
-#endif
-
 /*
  * Is the domain using the host memory layout?
  *
@@ -62,10 +50,6 @@ struct paging_domain {
 
 struct arch_domain
 {
-#ifdef CONFIG_ARM_64
-    enum domain_type type;
-#endif
-
 #ifdef CONFIG_ARM64_SVE
     /* max SVE encoded vector length */
     uint8_t sve_vl;
diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h
index 7c3b7fde5b..21f4273fa1 100644
--- a/xen/arch/arm/include/asm/kernel.h
+++ b/xen/arch/arm/include/asm/kernel.h
@@ -10,10 +10,6 @@
 
 struct arch_kernel_info
 {
-#ifdef CONFIG_ARM_64
-    enum domain_type type;
-#endif
-
     /* Enable pl011 emulation */
     bool vpl011;
 };
diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c
index 7544fd50a2..9395b5af87 100644
--- a/xen/arch/arm/kernel.c
+++ b/xen/arch/arm/kernel.c
@@ -100,8 +100,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info)
     const struct membanks *mem = kernel_info_get_mem(info);
     paddr_t load_addr;
 
-#ifdef CONFIG_ARM_64
-    if ( (info->arch.type == DOMAIN_64BIT) && (info->zimage.start == 0) )
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    if ( (info->type == DOMAIN_64BIT) && (info->zimage.start == 0) )
         return mem->bank[0].start + info->zimage.text_offset;
 #endif
 
@@ -268,14 +268,14 @@ int __init kernel_uimage_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-#ifdef CONFIG_ARM_64
+#ifdef CONFIG_HAS_DOMAIN_TYPE
     switch ( uimage.arch )
     {
     case IH_ARCH_ARM:
-        info->arch.type = DOMAIN_32BIT;
+        info->type = DOMAIN_32BIT;
         break;
     case IH_ARCH_ARM64:
-        info->arch.type = DOMAIN_64BIT;
+        info->type = DOMAIN_64BIT;
         break;
     default:
         printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch);
@@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-    info->arch.type = DOMAIN_64BIT;
+    info->type = DOMAIN_64BIT;
 
     return 0;
 }
@@ -396,8 +396,8 @@ static int __init kernel_zimage32_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-#ifdef CONFIG_ARM_64
-    info->arch.type = DOMAIN_32BIT;
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    info->type = DOMAIN_32BIT;
 #endif
 
     return 0;
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 0a20aa0a12..5ff71480ee 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -128,6 +128,9 @@ config HAS_DEVICE_TREE_DISCOVERY
 config HAS_DOM0LESS
 	bool
 
+config HAS_DOMAIN_TYPE
+	bool
+
 config HAS_DIT # Data Independent Timing
 	bool
 
diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h
index faaf660424..4118dec76c 100644
--- a/xen/include/xen/dom0less-build.h
+++ b/xen/include/xen/dom0less-build.h
@@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo,
 int make_intc_domU_node(struct kernel_info *kinfo);
 int make_arch_nodes(struct kernel_info *kinfo);
 
-void set_domain_type(struct domain *d, struct kernel_info *kinfo);
-
 int init_intc_phandle(struct kernel_info *kinfo, const char *name,
                       const int node_next, const void *pfdt);
 
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index 93c0fd00c1..a095190fc7 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -13,6 +13,19 @@ struct guest_area {
     void *map;
 };
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+enum __packed domain_type {
+    DOMAIN_32BIT,
+    DOMAIN_64BIT,
+};
+#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT)
+#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT)
+#elif !defined(CONFIG_64BIT)
+/* At the moment on 32-bit-only platforms all domains are 32-bit. */
+#define is_32bit_domain(d) true
+#define is_64bit_domain(d) false
+#endif
+
 #include <asm/domain.h>
 
 typedef union {
diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h
index 0d40d8cfa1..9465a1021f 100644
--- a/xen/include/xen/fdt-domain-build.h
+++ b/xen/include/xen/fdt-domain-build.h
@@ -7,6 +7,7 @@
 #include <xen/device_tree.h>
 #include <xen/fdt-kernel.h>
 #include <xen/mm.h>
+#include <xen/sched.h>
 #include <xen/types.h>
 
 struct domain;
@@ -69,6 +70,15 @@ static inline uint32_t alloc_phandle(struct kernel_info *kinfo)
     return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++;
 }
 
+static inline void set_domain_type(struct domain *d, const struct kernel_info *kinfo)
+{
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    /* Type must be set before allocating memory. */
+    ASSERT(!domain_tot_pages(d));
+    d->type = kinfo->type;
+#endif
+}
+
 #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */
 
 /*
diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h
index 4d0467bb39..86a37a1304 100644
--- a/xen/include/xen/fdt-kernel.h
+++ b/xen/include/xen/fdt-kernel.h
@@ -9,6 +9,7 @@
 
 #include <xen/bootinfo.h>
 #include <xen/device_tree.h>
+#include <xen/domain.h>
 #include <xen/types.h>
 
 #if __has_include(<asm/kernel.h>)
@@ -65,6 +66,10 @@ struct kernel_info {
         } zimage;
     };
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    enum domain_type type;
+#endif
+
 #if __has_include(<asm/kernel.h>)
     struct arch_kernel_info arch;
 #endif
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index 212c7d765c..00db1da12f 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -386,6 +386,10 @@ struct domain
 {
     domid_t          domain_id;
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    enum domain_type type;
+#endif
+
     unsigned int     max_vcpus;
 
     uint64_t         unique_id;       /* Unique domain identifier */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/time: make early NOW() uses slightly more precise
Message-Id: <E1wKzc2-000o63-0i@xenbits.xenproject.org>
Date: Thu, 07 May 2026 14:22:02 +0000

commit 4526d67634664bac3a441b37caa22d9b2e7a34d8
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu May 7 13:25:17 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:10:52 2026 +0200

    x86/time: make early NOW() uses slightly more precise
    
    For early NOW() uses to yield sufficiently precise results (scaling incurs
    some error, which grows with the delta being scaled), init_percpu_time()
    wants to have run as early as possible. With 93340297802b ("x86/time:
    calibrate TSC against platform timer") having moved the invocation of
    init_platform_timer() from init_xen_time() to early_time_init(), this
    other call could be moved as well.
    
    Moving, however, has the unwanted effect of then growing the gap until
    time calibration runs for the 1st time. Therefore keep the present
    invocation, and add another from early_time_init().
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/time.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 8209d37d32..c708c80be3 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -2597,6 +2597,11 @@ int __init init_xen_time(void)
     /* Finish platform timer initialization. */
     try_platform_timer_tail();
 
+    /*
+     * While early_time_init() called this already, call it again here to
+     * reduce the gap until local_time_calibration() gets to run for the
+     * first time.
+     */
     init_percpu_time();
 
     init_timer(&calibration_timer, time_calibration, NULL, 0);
@@ -2642,6 +2647,8 @@ void __init early_time_init(void)
     set_time_scale(&t->tsc_scale, tmp);
     t->stamp.local_tsc = boot_tsc_stamp;
 
+    init_percpu_time();
+
     cpu_khz = DIV_ROUND(tmp, 1000);
     printk("Detected %lu.%03lu MHz processor.\n", 
            cpu_khz / 1000, cpu_khz % 1000);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/time: make do_settime() uses more accurate
Message-Id: <E1wKzcH-000o9Q-0y@xenbits.xenproject.org>
Date: Thu, 07 May 2026 14:22:17 +0000

commit 54ca0aadc8219b19199703038205cd01c2611995
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu May 7 13:26:03 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:10:52 2026 +0200

    x86/time: make do_settime() uses more accurate
    
    As a comment next to one of the invocations states, get_wallclock_time()
    can take over a second. The order of evaluation of function arguments is
    in principle unspecified; in practice at least gcc looks to be evaluating
    them from last to first. Hence with NOW() invoked first, the respective
    value passed to do_settime() can be off by over a second (which is in
    contrast to __get_cmos_time() attempting to get the time exactly after an
    update, i.e. [pretty] precisely at a seconds boundary).
    
    This also addresses a Misra C:2012 rule 13.2 ("The value of an expression
    and its persistent side-effects shall be the same under all permitted
    evaluation orders") violation each. The violations aren't flagged because
    the entire file is (bogusly) excluded from scanning.
    
    Fixes: f64134cdb81c ("x86: Fix time_resume() to notify all domains of wallclock change")
    Fixes: 0bfcf984b727 ("x86: Reintroduce clocksource=tsc")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/time.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index c708c80be3..98e8ef19e4 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -2575,6 +2575,8 @@ __initcall(verify_tsc_reliability);
 /* Late init function (after interrupts are enabled). */
 int __init init_xen_time(void)
 {
+    unsigned long wc;
+
     tsc_check_writability();
 
     open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
@@ -2592,7 +2594,8 @@ int __init init_xen_time(void)
     printk(XENLOG_INFO "Wallclock source: %s\n", wallclock_type_to_string());
 
     /* NB. get_wallclock_time() can take over one second to execute. */
-    do_settime(get_wallclock_time(), 0, NOW());
+    wc = get_wallclock_time();
+    do_settime(wc, 0,  NOW());
 
     /* Finish platform timer initialization. */
     try_platform_timer_tail();
@@ -2752,6 +2755,8 @@ int time_suspend(void)
 
 int time_resume(void)
 {
+    unsigned long wc;
+
     preinit_pit();
 
     resume_platform_timer();
@@ -2763,7 +2768,8 @@ int time_resume(void)
 
     set_timer(&calibration_timer, NOW() + EPOCH);
 
-    do_settime(get_wallclock_time() + cmos_utc_offset, 0, NOW());
+    wc = get_wallclock_time();
+    do_settime(wc + cmos_utc_offset, 0, NOW());
 
     update_vcpu_system_time(current);
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/riscv: fix MMIO alignment check in imsic_init()
Message-Id: <E1wKzcR-000o9s-1I@xenbits.xenproject.org>
Date: Thu, 07 May 2026 14:22:27 +0000

commit 2611377cf9c92b43b04a33810f03fa07bf8ba954
Author:     Oleksii Kurochko <oleksii.kurochko@gmail.com>
AuthorDate: Thu May 7 13:27:07 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:11:03 2026 +0200

    xen/riscv: fix MMIO alignment check in imsic_init()
    
    The MMIO alignment check in imsic_init() incorrectly uses cpu as
    the index into mmios[]. The loop index should be used instead.
    Otherwise, the alignment check may be performed on the wrong MMIO
    address.
    
    Fix the index used in the alignment check and corresponding printk.
    
    Fixes: c9bd8b322ecbb ("xen/riscv: imsic_init() implementation")
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/riscv/imsic.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c
index a4460576f6..f7b70a8da0 100644
--- a/xen/arch/riscv/imsic.c
+++ b/xen/arch/riscv/imsic.c
@@ -451,11 +451,11 @@ int __init imsic_init(const struct dt_device_node *node)
             continue;
         }
 
-        if ( !IS_ALIGNED(mmios[cpu].base_addr + reloff,
-                         IMSIC_MMIO_PAGE_SZ) )
+        if ( !IS_ALIGNED(mmios[index].base_addr + reloff, IMSIC_MMIO_PAGE_SZ) )
         {
             printk(XENLOG_WARNING "%s: MMIO address %#lx is not aligned on a page\n",
-                   node->name, msi[cpu].base_addr + reloff);
+                   node->name, mmios[index].base_addr + reloff);
+
             continue;
         }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen: introduce CONFIG_HAS_DOMAIN_TYPE
Message-Id: <E1wL1U9-000vz0-2T@xenbits.xenproject.org>
Date: Thu, 07 May 2026 16:22:01 +0000

commit 9f976dec039c2a5ddeb389efbaae8d726e17e84a
Author:     Oleksii Kurochko <oleksii.kurochko@gmail.com>
AuthorDate: Thu May 7 10:58:23 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Thu May 7 13:26:52 2026 +0200

    xen: introduce CONFIG_HAS_DOMAIN_TYPE
    
    As domain type is part of common code now there is no any reason
    to have architecture-specific set_domain_type() functions so
    it is dropped.
    
    Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE
    for consistency. Also, drop and add some parentheses to be aligned
    with the similar if() below.
    
    x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as
    x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no
    longer builds, the fallback is currently only relevant for arm32.
    
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Michal Orzel <michal.orzel@amd.com>
    Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/arm/Kconfig               |  1 +
 xen/arch/arm/arm64/domctl.c        |  4 ++--
 xen/arch/arm/dom0less-build.c      | 14 --------------
 xen/arch/arm/domain_build.c        | 12 +++++-------
 xen/arch/arm/include/asm/domain.h  | 16 ----------------
 xen/arch/arm/include/asm/kernel.h  |  4 ----
 xen/arch/arm/kernel.c              | 16 ++++++++--------
 xen/common/Kconfig                 |  3 +++
 xen/include/xen/dom0less-build.h   |  2 --
 xen/include/xen/domain.h           | 13 +++++++++++++
 xen/include/xen/fdt-domain-build.h | 10 ++++++++++
 xen/include/xen/fdt-kernel.h       |  5 +++++
 xen/include/xen/sched.h            |  4 ++++
 13 files changed, 51 insertions(+), 53 deletions(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 2f2b501fda..79622b46a1 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -7,6 +7,7 @@ config ARM_64
 	def_bool y
 	depends on !ARM_32
 	select 64BIT
+	select HAS_DOMAIN_TYPE
 	select HAS_FAST_MULTIPLY
 	select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH
 
diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c
index 8720d126c9..9e9a29eb1e 100644
--- a/xen/arch/arm/arm64/domctl.c
+++ b/xen/arch/arm/arm64/domctl.c
@@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type)
         return -EINVAL;
     if ( domain_tot_pages(d) != 0 )
         return -EBUSY;
-    if ( d->arch.type == type )
+    if ( d->type == type )
         return 0;
 
-    d->arch.type = type;
+    d->type = type;
 
     if ( is_64bit_domain(d) )
         for_each_vcpu(d, v)
diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 4181c10538..6f73c65e51 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo)
     return 0;
 }
 
-/* TODO: make arch.type generic ? */
-#ifdef CONFIG_ARM_64
-void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
-{
-    /* type must be set before allocate memory */
-    d->arch.type = kinfo->arch.type;
-}
-#else
-void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
-{
-    /* Nothing to do */
-}
-#endif
-
 int __init init_vuart(struct domain *d, struct kernel_info *kinfo,
                       const struct dt_device_node *node)
 {
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a3ff701023..ad665cd3c0 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1771,15 +1771,15 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo)
     BUG_ON(d->vcpu[0] == NULL);
     BUG_ON(v->is_initialised);
 
-#ifdef CONFIG_ARM_64
+#ifdef CONFIG_HAS_DOMAIN_TYPE
     /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */
-    if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT )
+    if ( !cpu_has_el1_32 && (kinfo->type == DOMAIN_32BIT) )
     {
         printk("Platform does not support 32-bit domain\n");
         return -EINVAL;
     }
 
-    if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) )
+    if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) )
     {
         printk("SVE is not available for 32-bit domain\n");
         return -EINVAL;
@@ -1893,10 +1893,8 @@ int __init construct_hwdom(struct kernel_info *kinfo,
 
     iommu_hwdom_init(d);
 
-#ifdef CONFIG_ARM_64
-    /* type must be set before allocate_memory */
-    d->arch.type = kinfo->arch.type;
-#endif
+    set_domain_type(d, kinfo);
+
     find_gnttab_region(d, kinfo);
     if ( is_domain_direct_mapped(d) )
         allocate_memory_11(d, kinfo);
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index ffe5d0d9f0..b24f02d269 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -18,18 +18,6 @@ struct hvm_domain
     uint64_t              params[HVM_NR_PARAMS];
 };
 
-#ifdef CONFIG_ARM_64
-enum domain_type {
-    DOMAIN_32BIT,
-    DOMAIN_64BIT,
-};
-#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT)
-#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT)
-#else
-#define is_32bit_domain(d) (1)
-#define is_64bit_domain(d) (0)
-#endif
-
 /*
  * Is the domain using the host memory layout?
  *
@@ -62,10 +50,6 @@ struct paging_domain {
 
 struct arch_domain
 {
-#ifdef CONFIG_ARM_64
-    enum domain_type type;
-#endif
-
 #ifdef CONFIG_ARM64_SVE
     /* max SVE encoded vector length */
     uint8_t sve_vl;
diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h
index 7c3b7fde5b..21f4273fa1 100644
--- a/xen/arch/arm/include/asm/kernel.h
+++ b/xen/arch/arm/include/asm/kernel.h
@@ -10,10 +10,6 @@
 
 struct arch_kernel_info
 {
-#ifdef CONFIG_ARM_64
-    enum domain_type type;
-#endif
-
     /* Enable pl011 emulation */
     bool vpl011;
 };
diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c
index 7544fd50a2..9395b5af87 100644
--- a/xen/arch/arm/kernel.c
+++ b/xen/arch/arm/kernel.c
@@ -100,8 +100,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info)
     const struct membanks *mem = kernel_info_get_mem(info);
     paddr_t load_addr;
 
-#ifdef CONFIG_ARM_64
-    if ( (info->arch.type == DOMAIN_64BIT) && (info->zimage.start == 0) )
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    if ( (info->type == DOMAIN_64BIT) && (info->zimage.start == 0) )
         return mem->bank[0].start + info->zimage.text_offset;
 #endif
 
@@ -268,14 +268,14 @@ int __init kernel_uimage_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-#ifdef CONFIG_ARM_64
+#ifdef CONFIG_HAS_DOMAIN_TYPE
     switch ( uimage.arch )
     {
     case IH_ARCH_ARM:
-        info->arch.type = DOMAIN_32BIT;
+        info->type = DOMAIN_32BIT;
         break;
     case IH_ARCH_ARM64:
-        info->arch.type = DOMAIN_64BIT;
+        info->type = DOMAIN_64BIT;
         break;
     default:
         printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch);
@@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-    info->arch.type = DOMAIN_64BIT;
+    info->type = DOMAIN_64BIT;
 
     return 0;
 }
@@ -396,8 +396,8 @@ static int __init kernel_zimage32_probe(struct kernel_info *info,
 
     info->load = kernel_zimage_load;
 
-#ifdef CONFIG_ARM_64
-    info->arch.type = DOMAIN_32BIT;
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    info->type = DOMAIN_32BIT;
 #endif
 
     return 0;
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 0a20aa0a12..5ff71480ee 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -128,6 +128,9 @@ config HAS_DEVICE_TREE_DISCOVERY
 config HAS_DOM0LESS
 	bool
 
+config HAS_DOMAIN_TYPE
+	bool
+
 config HAS_DIT # Data Independent Timing
 	bool
 
diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h
index faaf660424..4118dec76c 100644
--- a/xen/include/xen/dom0less-build.h
+++ b/xen/include/xen/dom0less-build.h
@@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo,
 int make_intc_domU_node(struct kernel_info *kinfo);
 int make_arch_nodes(struct kernel_info *kinfo);
 
-void set_domain_type(struct domain *d, struct kernel_info *kinfo);
-
 int init_intc_phandle(struct kernel_info *kinfo, const char *name,
                       const int node_next, const void *pfdt);
 
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index 93c0fd00c1..a095190fc7 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -13,6 +13,19 @@ struct guest_area {
     void *map;
 };
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+enum __packed domain_type {
+    DOMAIN_32BIT,
+    DOMAIN_64BIT,
+};
+#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT)
+#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT)
+#elif !defined(CONFIG_64BIT)
+/* At the moment on 32-bit-only platforms all domains are 32-bit. */
+#define is_32bit_domain(d) true
+#define is_64bit_domain(d) false
+#endif
+
 #include <asm/domain.h>
 
 typedef union {
diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h
index 0d40d8cfa1..9465a1021f 100644
--- a/xen/include/xen/fdt-domain-build.h
+++ b/xen/include/xen/fdt-domain-build.h
@@ -7,6 +7,7 @@
 #include <xen/device_tree.h>
 #include <xen/fdt-kernel.h>
 #include <xen/mm.h>
+#include <xen/sched.h>
 #include <xen/types.h>
 
 struct domain;
@@ -69,6 +70,15 @@ static inline uint32_t alloc_phandle(struct kernel_info *kinfo)
     return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++;
 }
 
+static inline void set_domain_type(struct domain *d, const struct kernel_info *kinfo)
+{
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    /* Type must be set before allocating memory. */
+    ASSERT(!domain_tot_pages(d));
+    d->type = kinfo->type;
+#endif
+}
+
 #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */
 
 /*
diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h
index 4d0467bb39..86a37a1304 100644
--- a/xen/include/xen/fdt-kernel.h
+++ b/xen/include/xen/fdt-kernel.h
@@ -9,6 +9,7 @@
 
 #include <xen/bootinfo.h>
 #include <xen/device_tree.h>
+#include <xen/domain.h>
 #include <xen/types.h>
 
 #if __has_include(<asm/kernel.h>)
@@ -65,6 +66,10 @@ struct kernel_info {
         } zimage;
     };
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    enum domain_type type;
+#endif
+
 #if __has_include(<asm/kernel.h>)
     struct arch_kernel_info arch;
 #endif
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index 212c7d765c..00db1da12f 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -386,6 +386,10 @@ struct domain
 {
     domid_t          domain_id;
 
+#ifdef CONFIG_HAS_DOMAIN_TYPE
+    enum domain_type type;
+#endif
+
     unsigned int     max_vcpus;
 
     uint64_t         unique_id;       /* Unique domain identifier */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/time: make early NOW() uses slightly more precise
Message-Id: <E1wL1UJ-000vzq-31@xenbits.xenproject.org>
Date: Thu, 07 May 2026 16:22:11 +0000

commit 4526d67634664bac3a441b37caa22d9b2e7a34d8
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu May 7 13:25:17 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:10:52 2026 +0200

    x86/time: make early NOW() uses slightly more precise
    
    For early NOW() uses to yield sufficiently precise results (scaling incurs
    some error, which grows with the delta being scaled), init_percpu_time()
    wants to have run as early as possible. With 93340297802b ("x86/time:
    calibrate TSC against platform timer") having moved the invocation of
    init_platform_timer() from init_xen_time() to early_time_init(), this
    other call could be moved as well.
    
    Moving, however, has the unwanted effect of then growing the gap until
    time calibration runs for the 1st time. Therefore keep the present
    invocation, and add another from early_time_init().
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/time.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index 8209d37d32..c708c80be3 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -2597,6 +2597,11 @@ int __init init_xen_time(void)
     /* Finish platform timer initialization. */
     try_platform_timer_tail();
 
+    /*
+     * While early_time_init() called this already, call it again here to
+     * reduce the gap until local_time_calibration() gets to run for the
+     * first time.
+     */
     init_percpu_time();
 
     init_timer(&calibration_timer, time_calibration, NULL, 0);
@@ -2642,6 +2647,8 @@ void __init early_time_init(void)
     set_time_scale(&t->tsc_scale, tmp);
     t->stamp.local_tsc = boot_tsc_stamp;
 
+    init_percpu_time();
+
     cpu_khz = DIV_ROUND(tmp, 1000);
     printk("Detected %lu.%03lu MHz processor.\n", 
            cpu_khz / 1000, cpu_khz % 1000);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/time: make do_settime() uses more accurate
Message-Id: <E1wL1UU-000w0Y-06@xenbits.xenproject.org>
Date: Thu, 07 May 2026 16:22:22 +0000

commit 54ca0aadc8219b19199703038205cd01c2611995
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Thu May 7 13:26:03 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:10:52 2026 +0200

    x86/time: make do_settime() uses more accurate
    
    As a comment next to one of the invocations states, get_wallclock_time()
    can take over a second. The order of evaluation of function arguments is
    in principle unspecified; in practice at least gcc looks to be evaluating
    them from last to first. Hence with NOW() invoked first, the respective
    value passed to do_settime() can be off by over a second (which is in
    contrast to __get_cmos_time() attempting to get the time exactly after an
    update, i.e. [pretty] precisely at a seconds boundary).
    
    This also addresses a Misra C:2012 rule 13.2 ("The value of an expression
    and its persistent side-effects shall be the same under all permitted
    evaluation orders") violation each. The violations aren't flagged because
    the entire file is (bogusly) excluded from scanning.
    
    Fixes: f64134cdb81c ("x86: Fix time_resume() to notify all domains of wallclock change")
    Fixes: 0bfcf984b727 ("x86: Reintroduce clocksource=tsc")
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/time.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
index c708c80be3..98e8ef19e4 100644
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -2575,6 +2575,8 @@ __initcall(verify_tsc_reliability);
 /* Late init function (after interrupts are enabled). */
 int __init init_xen_time(void)
 {
+    unsigned long wc;
+
     tsc_check_writability();
 
     open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
@@ -2592,7 +2594,8 @@ int __init init_xen_time(void)
     printk(XENLOG_INFO "Wallclock source: %s\n", wallclock_type_to_string());
 
     /* NB. get_wallclock_time() can take over one second to execute. */
-    do_settime(get_wallclock_time(), 0, NOW());
+    wc = get_wallclock_time();
+    do_settime(wc, 0,  NOW());
 
     /* Finish platform timer initialization. */
     try_platform_timer_tail();
@@ -2752,6 +2755,8 @@ int time_suspend(void)
 
 int time_resume(void)
 {
+    unsigned long wc;
+
     preinit_pit();
 
     resume_platform_timer();
@@ -2763,7 +2768,8 @@ int time_resume(void)
 
     set_timer(&calibration_timer, NOW() + EPOCH);
 
-    do_settime(get_wallclock_time() + cmos_utc_offset, 0, NOW());
+    wc = get_wallclock_time();
+    do_settime(wc + cmos_utc_offset, 0, NOW());
 
     update_vcpu_system_time(current);
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/riscv: fix MMIO alignment check in imsic_init()
Message-Id: <E1wL1Ue-000w15-0P@xenbits.xenproject.org>
Date: Thu, 07 May 2026 16:22:32 +0000

commit 2611377cf9c92b43b04a33810f03fa07bf8ba954
Author:     Oleksii Kurochko <oleksii.kurochko@gmail.com>
AuthorDate: Thu May 7 13:27:07 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Thu May 7 16:11:03 2026 +0200

    xen/riscv: fix MMIO alignment check in imsic_init()
    
    The MMIO alignment check in imsic_init() incorrectly uses cpu as
    the index into mmios[]. The loop index should be used instead.
    Otherwise, the alignment check may be performed on the wrong MMIO
    address.
    
    Fix the index used in the alignment check and corresponding printk.
    
    Fixes: c9bd8b322ecbb ("xen/riscv: imsic_init() implementation")
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/riscv/imsic.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c
index a4460576f6..f7b70a8da0 100644
--- a/xen/arch/riscv/imsic.c
+++ b/xen/arch/riscv/imsic.c
@@ -451,11 +451,11 @@ int __init imsic_init(const struct dt_device_node *node)
             continue;
         }
 
-        if ( !IS_ALIGNED(mmios[cpu].base_addr + reloff,
-                         IMSIC_MMIO_PAGE_SZ) )
+        if ( !IS_ALIGNED(mmios[index].base_addr + reloff, IMSIC_MMIO_PAGE_SZ) )
         {
             printk(XENLOG_WARNING "%s: MMIO address %#lx is not aligned on a page\n",
-                   node->name, msi[cpu].base_addr + reloff);
+                   node->name, mmios[index].base_addr + reloff);
+
             continue;
         }
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: skip holes in physical address space when setting up frametable
Message-Id: <E1wLFhl-001tbC-2z@xenbits.xenproject.org>
Date: Fri, 08 May 2026 07:33:01 +0000

commit 10d417b8b62efa5093707c1dfe9bd48e0abeb331
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed May 6 10:41:37 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Fri May 8 08:52:27 2026 +0200

    xen/arm: skip holes in physical address space when setting up frametable
    
    Refactor setup_frametable_mappings() into init_frametable(), modeled
    after x86's implementation. Instead of mapping one contiguous frametable
    covering ram_start to ram_end (including holes), iterate the
    pdx_group_valid bitmap to allocate and map frametable memory only for
    valid PDX groups, skipping gaps in the physical address space.
    
    This reduces memory consumption on systems with sparse RAM layouts by
    not allocating frametable entries for non-existent memory regions.
    
    The chunk allocator rounds chunk_size up to PAGE_SIZE only, rather than
    to a larger mapping granularity, to avoid overshooting past chunk
    boundaries into subsequent gaps or valid regions. This rounding has no
    impact for in-loop chunks given that chunk size is a multiple of 14MB
    on Arm64 and 2MB on Arm32. The rounding matters only for the last
    out-of-loop chunk.
    
    Physical allocations prefer 32MB alignment so that map_pages_to_xen()
    can use the contiguous bit for larger TLB entries where virtual
    alignment also permits. Fall back to 2MB if the chunk is smaller than
    32MB.
    
    Add a comment explaining why we don't use pdx_to_page(). For complete
    discussion see [1].
    
    As ram_end is no longer needed by init_frametable(), drop the now-dead
    ram_end/bank_end computation from setup_mm().
    
    Update the MPU implementation to match the new init_frametable()
    signature. Since MPU has no virtual address translation (ma == va),
    hole-skipping is not possible and the frametable remains a single
    contiguous allocation.
    
    [1] https://lore.kernel.org/xen-devel/20260430125103.401811-1-michal.orzel@amd.com/T/#m803025eb6720a1425443dd0f8e72be93ef02f344
    
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/arm32/mmu/mm.c   |   3 +-
 xen/arch/arm/include/asm/mm.h |   4 +-
 xen/arch/arm/mm.c             |   5 +--
 xen/arch/arm/mmu/mm.c         | 100 ++++++++++++++++++++++++++++++++----------
 xen/arch/arm/mpu/mm.c         |  23 +++++-----
 5 files changed, 93 insertions(+), 42 deletions(-)

diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c
index 5e4766ddcf..0b595baa11 100644
--- a/xen/arch/arm/arm32/mmu/mm.c
+++ b/xen/arch/arm/arm32/mmu/mm.c
@@ -178,8 +178,7 @@ void __init setup_mm(void)
 
     setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages);
 
-    /* Frame table covers all of RAM region, including holes */
-    setup_frametable_mappings(ram_start, ram_end);
+    init_frametable(ram_start);
 
     /*
      * The allocators may need to use map_domain_page() (such as for
diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index 72a6928624..2eb8465aa9 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -196,8 +196,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr);
 extern void remove_early_mappings(void);
 /* Prepare the memory subystem to bring-up the given secondary CPU */
 extern int prepare_secondary_mm(int cpu);
-/* Map a frame table to cover physical addresses ps through pe */
-extern void setup_frametable_mappings(paddr_t ps, paddr_t pe);
+/* Map a frame table */
+void init_frametable(paddr_t ram_start);
 /* Helper function to setup memory management */
 void setup_mm_helper(void);
 /* map a physical range in virtual memory */
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 6eddbcf912..65aea71c43 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -33,7 +33,6 @@ void __init setup_mm(void)
 {
     const struct membanks *banks = bootinfo_get_mem();
     paddr_t ram_start = INVALID_PADDR;
-    paddr_t ram_end = 0;
     paddr_t ram_size = 0;
     unsigned int i;
 
@@ -42,11 +41,9 @@ void __init setup_mm(void)
     for ( i = 0; i < banks->nr_banks; i++ )
     {
         const struct membank *bank = &banks->bank[i];
-        paddr_t bank_end = bank->start + bank->size;
 
         ram_size = ram_size + bank->size;
         ram_start = min(ram_start, bank->start);
-        ram_end = max(ram_end, bank_end);
     }
 
     total_pages = ram_size >> PAGE_SHIFT;
@@ -62,7 +59,7 @@ void __init setup_mm(void)
 
     setup_mm_helper();
 
-    setup_frametable_mappings(ram_start, ram_end);
+    init_frametable(ram_start);
 
     init_staticmem_pages();
     init_sharedmem_pages();
diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c
index 6604f3bf4e..10c7dfb1ef 100644
--- a/xen/arch/arm/mmu/mm.c
+++ b/xen/arch/arm/mmu/mm.c
@@ -1,23 +1,61 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <xen/bitops.h>
 #include <xen/init.h>
 #include <xen/lib.h>
 #include <xen/macros.h>
 #include <xen/mm.h>
 #include <xen/mm-frame.h>
 #include <xen/pdx.h>
+#include <xen/sizes.h>
 #include <xen/string.h>
 
-/* Map a frame table to cover physical addresses ps through pe */
-void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+static void __init init_frametable_chunk(unsigned long pdx_s,
+                                         unsigned long pdx_e)
 {
-    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) -
-                            mfn_to_pdx(maddr_to_mfn(ps)) + 1;
-    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
-    mfn_t base_mfn;
-    const unsigned long mapping_size = frametable_size < MB(32) ? MB(2)
-                                                                : MB(32);
+    unsigned long nr_pdxs = pdx_e - pdx_s;
+    unsigned long chunk_size = nr_pdxs * sizeof(struct page_info);
+    unsigned long pfn_align;
+    struct page_info *pg;
     int rc;
+    mfn_t base_mfn;
+
+    /*
+     * In-loop chunks span whole PDX groups, which are always page-size
+     * aligned. The last chunk ending at max_pdx may not be, so round up.
+     */
+    chunk_size = ROUNDUP(chunk_size, PAGE_SIZE);
+
+    /*
+     * Try to align the allocation to the contiguous mapping size so that
+     * map_pages_to_xen() can use the contiguous bit.
+     */
+    pfn_align = ((chunk_size >= MB(32)) ? MB(32) : MB(2)) >> PAGE_SHIFT;
+
+    base_mfn = alloc_boot_pages(chunk_size >> PAGE_SHIFT, pfn_align);
+
+    /*
+     * Resolve the frametable VA via mfn_to_page(pdx_to_mfn(...)) rather
+     * than pdx_to_page() because the generic pdx_to_page() does not subtract
+     * frametable_base_pdx. There's more work to be done to make it generic, so
+     * for now route through mfn_to_page(), which on Arm applies the
+     * frametable_base_pdx offset and yields the correct VA.
+     */
+    pg = mfn_to_page(pdx_to_mfn(pdx_s));
+    rc = map_pages_to_xen((unsigned long)pg, base_mfn,
+                          chunk_size >> PAGE_SHIFT,
+                          PAGE_HYPERVISOR_RW | _PAGE_BLOCK);
+    if ( rc )
+        panic("Unable to setup the frametable mappings\n");
+
+    memset(pg, 0, nr_pdxs * sizeof(struct page_info));
+    memset(pg + nr_pdxs, -1,
+           chunk_size - nr_pdxs * sizeof(struct page_info));
+}
+
+void __init init_frametable(paddr_t ram_start)
+{
+    unsigned int sidx, nidx, max_idx;
 
     /*
      * The size of paddr_t should be sufficient for the complete range of
@@ -26,24 +64,40 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
     BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
     BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
 
-    if ( frametable_size > FRAMETABLE_SIZE )
-        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
-              ps, pe);
+    /* init_frametable_chunk() allocation alignment assumes 4KB granule */
+    BUILD_BUG_ON(PAGE_SIZE != SZ_4K);
 
-    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps));
-    /* Round up to 2M or 32M boundary, as appropriate. */
-    frametable_size = ROUNDUP(frametable_size, mapping_size);
-    base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12));
+    /* In-loop chunks must produce page-aligned frametable regions */
+    BUILD_BUG_ON((PDX_GROUP_COUNT * sizeof(struct page_info)) % PAGE_SIZE);
 
-    rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn,
-                          frametable_size >> PAGE_SHIFT,
-                          PAGE_HYPERVISOR_RW | _PAGE_BLOCK);
-    if ( rc )
-        panic("Unable to setup the frametable mappings.\n");
+    max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT);
+    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start));
+
+    /*
+     * Mapping address in init_frametable_chunk must be page-aligned
+     * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this
+     * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of
+     * PAGE_SIZE by construction.
+     */
+    frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT);
+
+    if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR )
+        panic("Frametable too small\n");
+
+    for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx )
+    {
+        unsigned int eidx;
+
+        eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx);
+        nidx = find_next_bit(pdx_group_valid, max_idx, eidx);
+
+        if ( nidx >= max_idx )
+            break;
+
+        init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT);
+    }
 
-    memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info));
-    memset(&frame_table[nr_pdxs], -1,
-           frametable_size - (nr_pdxs * sizeof(struct page_info)));
+    init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx);
 }
 
 /*
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index aff88bd3a9..9c568831c1 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned int attributes)
     return 0;
 }
 
-/* Map a frame table to cover physical addresses ps through pe */
-void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+/*
+ * Allocate a contiguous frame table covering ram_start through max_pdx.
+ * Unlike the MMU version, MPU cannot skip holes because there is no virtual
+ * address translation (ma == va).
+ */
+void __init init_frametable(paddr_t ram_start)
 {
+    unsigned long nr_pdxs, frametable_size;
     mfn_t base_mfn;
-    paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE);
-    paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE);
-
-    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) -
-                            mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1;
-    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
 
     /*
      * The size of paddr_t should be sufficient for the complete range of
@@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
     BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
     BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
 
+    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start));
+    nr_pdxs = max_pdx - frametable_base_pdx;
+    frametable_size = nr_pdxs * sizeof(struct page_info);
+
     if ( frametable_size > FRAMETABLE_SIZE )
-        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
-              ps, pe);
+        panic("Frametable too small\n");
 
-    frametable_base_pdx = paddr_to_pdx(aligned_ps);
     frametable_size = ROUNDUP(frametable_size, PAGE_SIZE);
 
     base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: skip holes in physical address space when setting up frametable
Message-Id: <E1wLJS2-0025hI-0j@xenbits.xenproject.org>
Date: Fri, 08 May 2026 11:33:02 +0000

commit 10d417b8b62efa5093707c1dfe9bd48e0abeb331
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Wed May 6 10:41:37 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Fri May 8 08:52:27 2026 +0200

    xen/arm: skip holes in physical address space when setting up frametable
    
    Refactor setup_frametable_mappings() into init_frametable(), modeled
    after x86's implementation. Instead of mapping one contiguous frametable
    covering ram_start to ram_end (including holes), iterate the
    pdx_group_valid bitmap to allocate and map frametable memory only for
    valid PDX groups, skipping gaps in the physical address space.
    
    This reduces memory consumption on systems with sparse RAM layouts by
    not allocating frametable entries for non-existent memory regions.
    
    The chunk allocator rounds chunk_size up to PAGE_SIZE only, rather than
    to a larger mapping granularity, to avoid overshooting past chunk
    boundaries into subsequent gaps or valid regions. This rounding has no
    impact for in-loop chunks given that chunk size is a multiple of 14MB
    on Arm64 and 2MB on Arm32. The rounding matters only for the last
    out-of-loop chunk.
    
    Physical allocations prefer 32MB alignment so that map_pages_to_xen()
    can use the contiguous bit for larger TLB entries where virtual
    alignment also permits. Fall back to 2MB if the chunk is smaller than
    32MB.
    
    Add a comment explaining why we don't use pdx_to_page(). For complete
    discussion see [1].
    
    As ram_end is no longer needed by init_frametable(), drop the now-dead
    ram_end/bank_end computation from setup_mm().
    
    Update the MPU implementation to match the new init_frametable()
    signature. Since MPU has no virtual address translation (ma == va),
    hole-skipping is not possible and the frametable remains a single
    contiguous allocation.
    
    [1] https://lore.kernel.org/xen-devel/20260430125103.401811-1-michal.orzel@amd.com/T/#m803025eb6720a1425443dd0f8e72be93ef02f344
    
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Tested-by: Luca Fancellu <luca.fancellu@arm.com>
    Acked-by: Stefano Stabellini <sstabellini@kernel.org>
---
 xen/arch/arm/arm32/mmu/mm.c   |   3 +-
 xen/arch/arm/include/asm/mm.h |   4 +-
 xen/arch/arm/mm.c             |   5 +--
 xen/arch/arm/mmu/mm.c         | 100 ++++++++++++++++++++++++++++++++----------
 xen/arch/arm/mpu/mm.c         |  23 +++++-----
 5 files changed, 93 insertions(+), 42 deletions(-)

diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c
index 5e4766ddcf..0b595baa11 100644
--- a/xen/arch/arm/arm32/mmu/mm.c
+++ b/xen/arch/arm/arm32/mmu/mm.c
@@ -178,8 +178,7 @@ void __init setup_mm(void)
 
     setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages);
 
-    /* Frame table covers all of RAM region, including holes */
-    setup_frametable_mappings(ram_start, ram_end);
+    init_frametable(ram_start);
 
     /*
      * The allocators may need to use map_domain_page() (such as for
diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index 72a6928624..2eb8465aa9 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -196,8 +196,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr);
 extern void remove_early_mappings(void);
 /* Prepare the memory subystem to bring-up the given secondary CPU */
 extern int prepare_secondary_mm(int cpu);
-/* Map a frame table to cover physical addresses ps through pe */
-extern void setup_frametable_mappings(paddr_t ps, paddr_t pe);
+/* Map a frame table */
+void init_frametable(paddr_t ram_start);
 /* Helper function to setup memory management */
 void setup_mm_helper(void);
 /* map a physical range in virtual memory */
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 6eddbcf912..65aea71c43 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -33,7 +33,6 @@ void __init setup_mm(void)
 {
     const struct membanks *banks = bootinfo_get_mem();
     paddr_t ram_start = INVALID_PADDR;
-    paddr_t ram_end = 0;
     paddr_t ram_size = 0;
     unsigned int i;
 
@@ -42,11 +41,9 @@ void __init setup_mm(void)
     for ( i = 0; i < banks->nr_banks; i++ )
     {
         const struct membank *bank = &banks->bank[i];
-        paddr_t bank_end = bank->start + bank->size;
 
         ram_size = ram_size + bank->size;
         ram_start = min(ram_start, bank->start);
-        ram_end = max(ram_end, bank_end);
     }
 
     total_pages = ram_size >> PAGE_SHIFT;
@@ -62,7 +59,7 @@ void __init setup_mm(void)
 
     setup_mm_helper();
 
-    setup_frametable_mappings(ram_start, ram_end);
+    init_frametable(ram_start);
 
     init_staticmem_pages();
     init_sharedmem_pages();
diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c
index 6604f3bf4e..10c7dfb1ef 100644
--- a/xen/arch/arm/mmu/mm.c
+++ b/xen/arch/arm/mmu/mm.c
@@ -1,23 +1,61 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <xen/bitops.h>
 #include <xen/init.h>
 #include <xen/lib.h>
 #include <xen/macros.h>
 #include <xen/mm.h>
 #include <xen/mm-frame.h>
 #include <xen/pdx.h>
+#include <xen/sizes.h>
 #include <xen/string.h>
 
-/* Map a frame table to cover physical addresses ps through pe */
-void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+static void __init init_frametable_chunk(unsigned long pdx_s,
+                                         unsigned long pdx_e)
 {
-    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) -
-                            mfn_to_pdx(maddr_to_mfn(ps)) + 1;
-    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
-    mfn_t base_mfn;
-    const unsigned long mapping_size = frametable_size < MB(32) ? MB(2)
-                                                                : MB(32);
+    unsigned long nr_pdxs = pdx_e - pdx_s;
+    unsigned long chunk_size = nr_pdxs * sizeof(struct page_info);
+    unsigned long pfn_align;
+    struct page_info *pg;
     int rc;
+    mfn_t base_mfn;
+
+    /*
+     * In-loop chunks span whole PDX groups, which are always page-size
+     * aligned. The last chunk ending at max_pdx may not be, so round up.
+     */
+    chunk_size = ROUNDUP(chunk_size, PAGE_SIZE);
+
+    /*
+     * Try to align the allocation to the contiguous mapping size so that
+     * map_pages_to_xen() can use the contiguous bit.
+     */
+    pfn_align = ((chunk_size >= MB(32)) ? MB(32) : MB(2)) >> PAGE_SHIFT;
+
+    base_mfn = alloc_boot_pages(chunk_size >> PAGE_SHIFT, pfn_align);
+
+    /*
+     * Resolve the frametable VA via mfn_to_page(pdx_to_mfn(...)) rather
+     * than pdx_to_page() because the generic pdx_to_page() does not subtract
+     * frametable_base_pdx. There's more work to be done to make it generic, so
+     * for now route through mfn_to_page(), which on Arm applies the
+     * frametable_base_pdx offset and yields the correct VA.
+     */
+    pg = mfn_to_page(pdx_to_mfn(pdx_s));
+    rc = map_pages_to_xen((unsigned long)pg, base_mfn,
+                          chunk_size >> PAGE_SHIFT,
+                          PAGE_HYPERVISOR_RW | _PAGE_BLOCK);
+    if ( rc )
+        panic("Unable to setup the frametable mappings\n");
+
+    memset(pg, 0, nr_pdxs * sizeof(struct page_info));
+    memset(pg + nr_pdxs, -1,
+           chunk_size - nr_pdxs * sizeof(struct page_info));
+}
+
+void __init init_frametable(paddr_t ram_start)
+{
+    unsigned int sidx, nidx, max_idx;
 
     /*
      * The size of paddr_t should be sufficient for the complete range of
@@ -26,24 +64,40 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
     BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
     BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
 
-    if ( frametable_size > FRAMETABLE_SIZE )
-        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
-              ps, pe);
+    /* init_frametable_chunk() allocation alignment assumes 4KB granule */
+    BUILD_BUG_ON(PAGE_SIZE != SZ_4K);
 
-    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps));
-    /* Round up to 2M or 32M boundary, as appropriate. */
-    frametable_size = ROUNDUP(frametable_size, mapping_size);
-    base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12));
+    /* In-loop chunks must produce page-aligned frametable regions */
+    BUILD_BUG_ON((PDX_GROUP_COUNT * sizeof(struct page_info)) % PAGE_SIZE);
 
-    rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn,
-                          frametable_size >> PAGE_SHIFT,
-                          PAGE_HYPERVISOR_RW | _PAGE_BLOCK);
-    if ( rc )
-        panic("Unable to setup the frametable mappings.\n");
+    max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT);
+    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start));
+
+    /*
+     * Mapping address in init_frametable_chunk must be page-aligned
+     * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this
+     * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of
+     * PAGE_SIZE by construction.
+     */
+    frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT);
+
+    if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR )
+        panic("Frametable too small\n");
+
+    for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx )
+    {
+        unsigned int eidx;
+
+        eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx);
+        nidx = find_next_bit(pdx_group_valid, max_idx, eidx);
+
+        if ( nidx >= max_idx )
+            break;
+
+        init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT);
+    }
 
-    memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info));
-    memset(&frame_table[nr_pdxs], -1,
-           frametable_size - (nr_pdxs * sizeof(struct page_info)));
+    init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx);
 }
 
 /*
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index aff88bd3a9..9c568831c1 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned int attributes)
     return 0;
 }
 
-/* Map a frame table to cover physical addresses ps through pe */
-void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+/*
+ * Allocate a contiguous frame table covering ram_start through max_pdx.
+ * Unlike the MMU version, MPU cannot skip holes because there is no virtual
+ * address translation (ma == va).
+ */
+void __init init_frametable(paddr_t ram_start)
 {
+    unsigned long nr_pdxs, frametable_size;
     mfn_t base_mfn;
-    paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE);
-    paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE);
-
-    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) -
-                            mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1;
-    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
 
     /*
      * The size of paddr_t should be sufficient for the complete range of
@@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
     BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
     BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
 
+    frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start));
+    nr_pdxs = max_pdx - frametable_base_pdx;
+    frametable_size = nr_pdxs * sizeof(struct page_info);
+
     if ( frametable_size > FRAMETABLE_SIZE )
-        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
-              ps, pe);
+        panic("Frametable too small\n");
 
-    frametable_base_pdx = paddr_to_pdx(aligned_ps);
     frametable_size = ROUNDUP(frametable_size, PAGE_SIZE);
 
     base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] time: drop dead code from gmtime()
Message-Id: <E1wMQPW-000D7Y-0g@xenbits.xenproject.org>
Date: Mon, 11 May 2026 13:11:02 +0000

commit 4909438bc397b8d31d6b48a44498ca1ec242324b
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 13:19:31 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon May 11 13:19:31 2026 +0200

    time: drop dead code from gmtime()
    
    "days", as calculated, can't be negative. Drop the respective loop and
    change its type. Similarly "rem" can't be negative and doesn't require
    more than 32 bits. Change its type, too.
    
    As a consequence, the tm_wday calculation also can't yield negative
    values, so the respective conditional can be dropped as well.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/common/time.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/xen/common/time.c b/xen/common/time.c
index c873b5731b..04a65f00b3 100644
--- a/xen/common/time.c
+++ b/xen/common/time.c
@@ -45,7 +45,8 @@ static DEFINE_SPINLOCK(wc_lock);
 struct tm gmtime(unsigned long t)
 {
     struct tm tbuf;
-    long days, rem;
+    unsigned long days;
+    unsigned int rem;
     int y;
     const unsigned short int *ip;
 
@@ -70,18 +71,11 @@ struct tm gmtime(unsigned long t)
     tbuf.tm_sec = rem % 60;
     /* January 1, 1970 was a Thursday.  */
     tbuf.tm_wday = (4 + days) % 7;
-    if ( tbuf.tm_wday < 0 )
-        tbuf.tm_wday += 7;
     while ( days >= (rem = __isleap(y) ? 366 : 365) )
     {
         ++y;
         days -= rem;
     }
-    while ( days < 0 )
-    {
-        --y;
-        days += __isleap(y) ? 366 : 365;
-    }
     tbuf.tm_year = y - 1900;
     tbuf.tm_yday = days;
     /* SAF-14-safe use boolean as an array index */
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: re-work Xen artifacts collection
Message-Id: <E1wMcAE-000vGd-0V@xenbits.xenproject.org>
Date: Tue, 12 May 2026 01:44:02 +0000

commit 87dd994a3e98f86c3e29505c4b11b14b8eb7af1a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 15:04:32 2026 +0200
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Mon May 11 18:40:53 2026 -0700

    CI: re-work Xen artifacts collection
    
    There's no need to do this separately from three places. Once moved to the
    bottom of the script, the need for this to be a function also disappears.
    
    While there also make sure xen-syms is collected. This is rather more
    useful for analysis of possible problems than its stripped counterpart.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/scripts/build | 30 +++++++++++-------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/automation/scripts/build b/automation/scripts/build
index 359ee18444..2df154398d 100755
--- a/automation/scripts/build
+++ b/automation/scripts/build
@@ -44,30 +44,15 @@ cp xen/.config xen-config
 # Directory for the artefacts to be dumped into
 mkdir -p binaries
 
-collect_xen_artefacts()
-{
-    local f
-
-    for f in xen/xen xen/xen.efi; do
-        if [[ -f $f ]]; then
-            cp $f binaries/
-        fi
-    done
-}
-
 if [[ "${CPPCHECK}" == "y" ]] && [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Cppcheck analysis invokes Xen-only build
     xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc)
 
     # Preserve artefacts
-    collect_xen_artefacts
     cp xen/cppcheck-report/xen-cppcheck.txt xen-cppcheck.txt
 elif [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Xen-only build
     make -j$(nproc) xen
-
-    # Preserve artefacts
-    collect_xen_artefacts
 else
     # Full build.  Figure out our ./configure options
     cfgargs=("--prefix=/usr")
@@ -108,9 +93,16 @@ else
     make -j$(nproc) dist
 
     # Preserve artefacts
-    # Note: Some smoke tests depending on finding binaries/xen on a full build
-    # even though dist/ contains everything, while some containers don't even
-    # build Xen
     (cd dist/install; find | cpio -R 0:0 -o -H newc | gzip) > binaries/xen-tools.cpio.gz
-    collect_xen_artefacts
 fi
+
+# Preserve Xen artefacts
+#
+# Note: Some smoke tests depend on finding binaries/xen on a full build
+# even though dist/ contains everything, while some containers don't even
+# build Xen.
+for f in xen/xen xen/xen-syms xen/xen.efi; do
+    if [[ -f $f ]]; then
+        cp $f binaries/
+    fi
+done
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] CI: collect certain intermediate files as artifacts
Message-Id: <E1wMcAO-000vHv-0v@xenbits.xenproject.org>
Date: Tue, 12 May 2026 01:44:12 +0000

commit 2121f895036809fccaa5181aed25a16b13adf647
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 15:05:02 2026 +0200
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Mon May 11 18:40:58 2026 -0700

    CI: collect certain intermediate files as artifacts
    
    When one of the linking passes fails, additional intermediate files are
    still in place. Having them available for analysis of the underlying
    problem can be pretty helpful. Collect some into a new intermediates/
    directory. (Nothing new will be collected if linking succeeds.)
    
    As the script is run with -e passed to bash, defer exit if the main
    "make" (or substituent script thereof) failed. This way more artifacts
    are collected, potentially making it easier to analyze the failure.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/gitlab-ci/build.yaml |  1 +
 automation/scripts/build        | 25 ++++++++++++++++++-------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index f058957291..7f5b5938e8 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -6,6 +6,7 @@
   artifacts:
     paths:
       - binaries/
+      - intermediates/
       - xen-config
       - xen-cppcheck.txt
       - '*.log'
diff --git a/automation/scripts/build b/automation/scripts/build
index 2df154398d..bdaab11c37 100755
--- a/automation/scripts/build
+++ b/automation/scripts/build
@@ -37,22 +37,24 @@ else
     make -j$(nproc) -C xen olddefconfig
 fi
 
-# Save the config file before building because build failure causes the script
-# to exit early -- bash is invoked with -e.
+# Save the config file before building, just in case.
 cp xen/.config xen-config
 
-# Directory for the artefacts to be dumped into
-mkdir -p binaries
+# Directories for artefacts to be dumped into
+mkdir -p binaries intermediates
+
+# Script exit status, to be overridden by the main make's status below.
+ret=0
 
 if [[ "${CPPCHECK}" == "y" ]] && [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Cppcheck analysis invokes Xen-only build
-    xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc)
+    xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc) || ret=$?
 
     # Preserve artefacts
     cp xen/cppcheck-report/xen-cppcheck.txt xen-cppcheck.txt
 elif [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Xen-only build
-    make -j$(nproc) xen
+    make -j$(nproc) xen || ret=$?
 else
     # Full build.  Figure out our ./configure options
     cfgargs=("--prefix=/usr")
@@ -90,7 +92,7 @@ else
     fi
 
     ./configure "${cfgargs[@]}"
-    make -j$(nproc) dist
+    make -j$(nproc) dist || ret=$?
 
     # Preserve artefacts
     (cd dist/install; find | cpio -R 0:0 -o -H newc | gzip) > binaries/xen-tools.cpio.gz
@@ -106,3 +108,12 @@ for f in xen/xen xen/xen-syms xen/xen.efi; do
         cp $f binaries/
     fi
 done
+
+# Preserve Xen intermediate files.  Some may be there only upon build failure.
+for f in xen/.xen-syms.* xen/.xen.efi.*; do
+    if [[ -f $f ]]; then
+        cp $f intermediates/
+    fi
+done
+
+exit $ret
--
generated by git-patchbot for /home/xen/git/xen.git#staging


From xen-changelog-bounces@lists.xenproject.org Tue May 12 02:55:09 2026
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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] time: drop dead code from gmtime()
Message-Id: <E1wMdGv-000ys3-1i@xenbits.xenproject.org>
Date: Tue, 12 May 2026 02:55:01 +0000

commit 4909438bc397b8d31d6b48a44498ca1ec242324b
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 13:19:31 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Mon May 11 13:19:31 2026 +0200

    time: drop dead code from gmtime()
    
    "days", as calculated, can't be negative. Drop the respective loop and
    change its type. Similarly "rem" can't be negative and doesn't require
    more than 32 bits. Change its type, too.
    
    As a consequence, the tm_wday calculation also can't yield negative
    values, so the respective conditional can be dropped as well.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/common/time.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/xen/common/time.c b/xen/common/time.c
index c873b5731b..04a65f00b3 100644
--- a/xen/common/time.c
+++ b/xen/common/time.c
@@ -45,7 +45,8 @@ static DEFINE_SPINLOCK(wc_lock);
 struct tm gmtime(unsigned long t)
 {
     struct tm tbuf;
-    long days, rem;
+    unsigned long days;
+    unsigned int rem;
     int y;
     const unsigned short int *ip;
 
@@ -70,18 +71,11 @@ struct tm gmtime(unsigned long t)
     tbuf.tm_sec = rem % 60;
     /* January 1, 1970 was a Thursday.  */
     tbuf.tm_wday = (4 + days) % 7;
-    if ( tbuf.tm_wday < 0 )
-        tbuf.tm_wday += 7;
     while ( days >= (rem = __isleap(y) ? 366 : 365) )
     {
         ++y;
         days -= rem;
     }
-    while ( days < 0 )
-    {
-        --y;
-        days += __isleap(y) ? 366 : 365;
-    }
     tbuf.tm_year = y - 1900;
     tbuf.tm_yday = days;
     /* SAF-14-safe use boolean as an array index */
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: re-work Xen artifacts collection
Message-Id: <E1wMdH5-000ysR-24@xenbits.xenproject.org>
Date: Tue, 12 May 2026 02:55:11 +0000

commit 87dd994a3e98f86c3e29505c4b11b14b8eb7af1a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 15:04:32 2026 +0200
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Mon May 11 18:40:53 2026 -0700

    CI: re-work Xen artifacts collection
    
    There's no need to do this separately from three places. Once moved to the
    bottom of the script, the need for this to be a function also disappears.
    
    While there also make sure xen-syms is collected. This is rather more
    useful for analysis of possible problems than its stripped counterpart.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/scripts/build | 30 +++++++++++-------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/automation/scripts/build b/automation/scripts/build
index 359ee18444..2df154398d 100755
--- a/automation/scripts/build
+++ b/automation/scripts/build
@@ -44,30 +44,15 @@ cp xen/.config xen-config
 # Directory for the artefacts to be dumped into
 mkdir -p binaries
 
-collect_xen_artefacts()
-{
-    local f
-
-    for f in xen/xen xen/xen.efi; do
-        if [[ -f $f ]]; then
-            cp $f binaries/
-        fi
-    done
-}
-
 if [[ "${CPPCHECK}" == "y" ]] && [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Cppcheck analysis invokes Xen-only build
     xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc)
 
     # Preserve artefacts
-    collect_xen_artefacts
     cp xen/cppcheck-report/xen-cppcheck.txt xen-cppcheck.txt
 elif [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Xen-only build
     make -j$(nproc) xen
-
-    # Preserve artefacts
-    collect_xen_artefacts
 else
     # Full build.  Figure out our ./configure options
     cfgargs=("--prefix=/usr")
@@ -108,9 +93,16 @@ else
     make -j$(nproc) dist
 
     # Preserve artefacts
-    # Note: Some smoke tests depending on finding binaries/xen on a full build
-    # even though dist/ contains everything, while some containers don't even
-    # build Xen
     (cd dist/install; find | cpio -R 0:0 -o -H newc | gzip) > binaries/xen-tools.cpio.gz
-    collect_xen_artefacts
 fi
+
+# Preserve Xen artefacts
+#
+# Note: Some smoke tests depend on finding binaries/xen on a full build
+# even though dist/ contains everything, while some containers don't even
+# build Xen.
+for f in xen/xen xen/xen-syms xen/xen.efi; do
+    if [[ -f $f ]]; then
+        cp $f binaries/
+    fi
+done
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] CI: collect certain intermediate files as artifacts
Message-Id: <E1wMdHF-000yut-2N@xenbits.xenproject.org>
Date: Tue, 12 May 2026 02:55:21 +0000

commit 2121f895036809fccaa5181aed25a16b13adf647
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon May 11 15:05:02 2026 +0200
Commit:     Stefano Stabellini <stefano.stabellini@amd.com>
CommitDate: Mon May 11 18:40:58 2026 -0700

    CI: collect certain intermediate files as artifacts
    
    When one of the linking passes fails, additional intermediate files are
    still in place. Having them available for analysis of the underlying
    problem can be pretty helpful. Collect some into a new intermediates/
    directory. (Nothing new will be collected if linking succeeds.)
    
    As the script is run with -e passed to bash, defer exit if the main
    "make" (or substituent script thereof) failed. This way more artifacts
    are collected, potentially making it easier to analyze the failure.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
 automation/gitlab-ci/build.yaml |  1 +
 automation/scripts/build        | 25 ++++++++++++++++++-------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index f058957291..7f5b5938e8 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -6,6 +6,7 @@
   artifacts:
     paths:
       - binaries/
+      - intermediates/
       - xen-config
       - xen-cppcheck.txt
       - '*.log'
diff --git a/automation/scripts/build b/automation/scripts/build
index 2df154398d..bdaab11c37 100755
--- a/automation/scripts/build
+++ b/automation/scripts/build
@@ -37,22 +37,24 @@ else
     make -j$(nproc) -C xen olddefconfig
 fi
 
-# Save the config file before building because build failure causes the script
-# to exit early -- bash is invoked with -e.
+# Save the config file before building, just in case.
 cp xen/.config xen-config
 
-# Directory for the artefacts to be dumped into
-mkdir -p binaries
+# Directories for artefacts to be dumped into
+mkdir -p binaries intermediates
+
+# Script exit status, to be overridden by the main make's status below.
+ret=0
 
 if [[ "${CPPCHECK}" == "y" ]] && [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Cppcheck analysis invokes Xen-only build
-    xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc)
+    xen/scripts/xen-analysis.py --run-cppcheck --cppcheck-misra -- -j$(nproc) || ret=$?
 
     # Preserve artefacts
     cp xen/cppcheck-report/xen-cppcheck.txt xen-cppcheck.txt
 elif [[ "${HYPERVISOR_ONLY}" == "y" ]]; then
     # Xen-only build
-    make -j$(nproc) xen
+    make -j$(nproc) xen || ret=$?
 else
     # Full build.  Figure out our ./configure options
     cfgargs=("--prefix=/usr")
@@ -90,7 +92,7 @@ else
     fi
 
     ./configure "${cfgargs[@]}"
-    make -j$(nproc) dist
+    make -j$(nproc) dist || ret=$?
 
     # Preserve artefacts
     (cd dist/install; find | cpio -R 0:0 -o -H newc | gzip) > binaries/xen-tools.cpio.gz
@@ -106,3 +108,12 @@ for f in xen/xen xen/xen-syms xen/xen.efi; do
         cp $f binaries/
     fi
 done
+
+# Preserve Xen intermediate files.  Some may be there only upon build failure.
+for f in xen/.xen-syms.* xen/.xen.efi.*; do
+    if [[ -f $f ]]; then
+        cp $f intermediates/
+    fi
+done
+
+exit $ret
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/MCE: adjust S3 resume handling
Message-Id: <E1wMjek-001Kke-0v@xenbits.xenproject.org>
Date: Tue, 12 May 2026 09:44:02 +0000

commit d9b3aceae1ebe859c3aa8413bf0d90cfa508be54
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 12 08:31:31 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 12 08:31:31 2026 +0200

    x86/MCE: adjust S3 resume handling
    
    The BSP resume path calls mcheck_init() with the address of
    boot_cpu_data, thus rendering comparisons against that pointer
    ineffective. The additional "bsp" boolean needs to be used (and
    propagated as necessary) instead.
    
    While touching intel_init_thermal(), constify its 1st parameter, which
    in turn requires touching intel_thermal_supported() as well.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mcheck/mce_amd.c   |  4 ++--
 xen/arch/x86/cpu/mcheck/mce_intel.c | 18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
index 25c29eb3d2..bf353c9a69 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -318,7 +318,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
         mcequirk_amd_apply(quirkflag);
 
     if ( cpu_has(c, X86_FEATURE_AMD_PPIN) &&
-         (c == &boot_cpu_data || ppin_msr) )
+         (bsp || ppin_msr) )
     {
         uint64_t val;
 
@@ -333,7 +333,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_AMD_PPIN;
     }
 
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 839a0e5ba9..673e608376 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -87,7 +87,7 @@ static void cf_check intel_thermal_interrupt(void)
 }
 
 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
-static bool intel_thermal_supported(struct cpuinfo_x86 *c)
+static bool intel_thermal_supported(const struct cpuinfo_x86 *c)
 {
     if ( !cpu_has_apic )
         return false;
@@ -110,7 +110,7 @@ static void __init mcheck_intel_therm_init(void)
 }
 
 /* P4/Xeon Thermal regulation detect and init */
-static void intel_init_thermal(struct cpuinfo_x86 *c)
+static void intel_init_thermal(const struct cpuinfo_x86 *c, bool bsp)
 {
     uint64_t msr_content;
     uint32_t val;
@@ -143,7 +143,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
     if ( (msr_content & (1ULL<<3))
          && (val & APIC_DM_MASK) == APIC_DM_SMI )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal monitoring handled by SMI\n");
         return; /* -EBUSY */
     }
@@ -154,7 +154,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
     /* check whether a vector already exists, temporarily masked? */
     if ( val & APIC_VECTOR_MASK )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal LVT vector (%#x) already installed\n",
                    val & APIC_VECTOR_MASK);
         return; /* -EBUSY */
@@ -852,7 +852,7 @@ static void intel_init_mce(bool bsp)
     mce_uhandler_num = ARRAY_SIZE(intel_mce_uhandlers);
 }
 
-static void intel_init_ppin(const struct cpuinfo_x86 *c)
+static void intel_init_ppin(const struct cpuinfo_x86 *c, bool bsp)
 {
     /*
      * Even if testing the presence of the MSR would be enough, we don't
@@ -881,7 +881,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case INTEL_SAPPHIRERAPIDS_X:
     case INTEL_EMERALDRAPIDS_X:
 
-        if ( (c != &boot_cpu_data && !ppin_msr) ||
+        if ( (!bsp && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, &val) )
             return;
 
@@ -894,7 +894,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_PPIN;
 
         break;
@@ -995,9 +995,9 @@ enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool bsp)
 
     intel_init_cmci(c);
 
-    intel_init_thermal(c);
+    intel_init_thermal(c, bsp);
 
-    intel_init_ppin(c);
+    intel_init_ppin(c, bsp);
 
     return mcheck_intel;
 }
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86emul: support LKGS
Message-Id: <E1wMjeu-001KmN-1U@xenbits.xenproject.org>
Date: Tue, 12 May 2026 09:44:12 +0000

commit a6b143e5a3a5733c12b71e7e2f5b6e9300e5920a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 12 08:31:59 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 12 08:31:59 2026 +0200

    x86emul: support LKGS
    
    Provide support for this insn, which is a prereq to FRED. CPUID-wise,
    while its and FRED's enumerators were already introduced, their dependency
    still needs adding.
    
    While adding a testcase, also add a SWAPGS one. In order to not affect
    the behavior of pre-existing tests, install write_{segment,msr} hooks
    only transiently.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 tools/tests/x86_emulator/predicates.c        |  1 +
 tools/tests/x86_emulator/test_x86_emulator.c | 96 ++++++++++++++++++++++++++++
 tools/tests/x86_emulator/x86-emulate.c       |  1 +
 xen/arch/x86/x86_emulate/decode.c            |  6 +-
 xen/arch/x86/x86_emulate/private.h           |  1 +
 xen/arch/x86/x86_emulate/x86_emulate.c       | 33 +++++++++-
 xen/tools/gen-cpuid.py                       |  3 +-
 7 files changed, 137 insertions(+), 4 deletions(-)

diff --git a/tools/tests/x86_emulator/predicates.c b/tools/tests/x86_emulator/predicates.c
index 019c2ced8a..8ff2653895 100644
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -326,6 +326,7 @@ static const struct {
     { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */
     { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */
     { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */
+    { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */
     { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */
     { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */
     { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */
diff --git a/tools/tests/x86_emulator/test_x86_emulator.c b/tools/tests/x86_emulator/test_x86_emulator.c
index 20929b80c6..af29b106f1 100644
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -673,6 +673,10 @@ static int blk(
     return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt);
 }
 
+#ifdef __x86_64__
+static unsigned long gs_base, gs_base_shadow;
+#endif
+
 static int read_segment(
     enum x86_segment seg,
     struct segment_register *reg,
@@ -682,9 +686,26 @@ static int read_segment(
         return X86EMUL_UNHANDLEABLE;
     memset(reg, 0, sizeof(*reg));
     reg->p = 1;
+
     return X86EMUL_OKAY;
 }
 
+#ifdef __x86_64__
+static int write_segment(
+    enum x86_segment seg,
+    const struct segment_register *reg,
+    struct x86_emulate_ctxt *ctxt)
+{
+    if ( !is_x86_user_segment(seg) )
+        return X86EMUL_UNHANDLEABLE;
+
+    if ( seg == x86_seg_gs )
+        gs_base = reg->base;
+
+    return X86EMUL_OKAY;
+}
+#endif
+
 static int read_msr(
     unsigned int reg,
     uint64_t *val,
@@ -696,6 +717,20 @@ static int read_msr(
         *val = ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0;
         return X86EMUL_OKAY;
 
+#ifdef __x86_64__
+    case MSR_GS_BASE:
+        if ( ctxt->addr_size < 64 )
+            break;
+        *val = gs_base;
+        return X86EMUL_OKAY;
+
+    case MSR_SHADOW_GS_BASE:
+        if ( ctxt->addr_size < 64 )
+            break;
+        *val = gs_base_shadow;
+        return X86EMUL_OKAY;
+#endif
+
     case MSR_TSC_AUX:
 #define TSC_AUX_VALUE 0xCACACACA
         *val = TSC_AUX_VALUE;
@@ -705,6 +740,32 @@ static int read_msr(
     return X86EMUL_UNHANDLEABLE;
 }
 
+#ifdef __x86_64__
+static int write_msr(
+    unsigned int reg,
+    uint64_t val,
+    struct x86_emulate_ctxt *ctxt,
+    bool explicit)
+{
+    switch ( reg )
+    {
+    case MSR_GS_BASE:
+        if ( ctxt->addr_size < 64 || !is_canonical_address(val) )
+            break;
+        gs_base = val;
+        return X86EMUL_OKAY;
+
+    case MSR_SHADOW_GS_BASE:
+        if ( ctxt->addr_size < 64 || !is_canonical_address(val) )
+            break;
+        gs_base_shadow = val;
+        return X86EMUL_OKAY;
+    }
+
+    return X86EMUL_UNHANDLEABLE;
+}
+#endif
+
 #define INVPCID_ADDR 0x12345678
 #define INVPCID_PCID 0x123
 
@@ -1339,6 +1400,41 @@ int main(int argc, char **argv)
         printf("%u bytes read - ", bytes_read);
         goto fail;
     }
+    printf("okay\n");
+
+    emulops.write_segment = write_segment;
+    emulops.write_msr     = write_msr;
+
+    printf("%-40s", "Testing swapgs...");
+    instr[0] = 0x0f; instr[1] = 0x01; instr[2] = 0xf8;
+    regs.eip = (unsigned long)&instr[0];
+    gs_base = 0xffffeeeecccc8888UL;
+    gs_base_shadow = 0x0000111122224444UL;
+    rc = x86_emulate(&ctxt, &emulops);
+    if ( (rc != X86EMUL_OKAY) ||
+         (regs.eip != (unsigned long)&instr[3]) ||
+         (gs_base != 0x0000111122224444UL) ||
+         (gs_base_shadow != 0xffffeeeecccc8888UL) )
+        goto fail;
+    printf("okay\n");
+
+    printf("%-40s", "Testing lkgs 2(%rdx)...");
+    instr[0] = 0xf2; instr[1] = 0x0f; instr[2] = 0x00; instr[3] = 0x72; instr[4] = 0x02;
+    regs.eip = (unsigned long)&instr[0];
+    regs.edx = (unsigned long)res;
+    res[0]   = 0x00004444;
+    res[1]   = 0x8888cccc;
+    i = cpu_policy.extd.nscb; cpu_policy.extd.nscb = true; /* for AMD */
+    rc = x86_emulate(&ctxt, &emulops);
+    if ( (rc != X86EMUL_OKAY) ||
+         (regs.eip != (unsigned long)&instr[5]) ||
+         (gs_base != 0x0000111122224444UL) ||
+         gs_base_shadow )
+        goto fail;
+
+    cpu_policy.extd.nscb = i;
+    emulops.write_segment = NULL;
+    emulops.write_msr     = NULL;
 #endif
     printf("okay\n");
 
diff --git a/tools/tests/x86_emulator/x86-emulate.c b/tools/tests/x86_emulator/x86-emulate.c
index 379e206dd3..b22c7d6add 100644
--- a/tools/tests/x86_emulator/x86-emulate.c
+++ b/tools/tests/x86_emulator/x86-emulate.c
@@ -85,6 +85,7 @@ bool emul_test_init(void)
     cpu_policy.feat.invpcid = true;
     cpu_policy.feat.adx = true;
     cpu_policy.feat.rdpid = true;
+    cpu_policy.feat.lkgs = true;
     cpu_policy.feat.wrmsrns = true;
     cpu_policy.extd.clzero = true;
 
diff --git a/xen/arch/x86/x86_emulate/decode.c b/xen/arch/x86/x86_emulate/decode.c
index 346777422b..2c13356c4d 100644
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -745,8 +745,12 @@ decode_twobyte(struct x86_emulate_state *s,
         case 0:
             s->desc |= DstMem | SrcImplicit | Mov;
             break;
+        case 6:
+            if ( !(s->modrm_reg & 1) && mode_64bit() )
+            {
         case 2: case 4:
-            s->desc |= SrcMem16;
+                s->desc |= SrcMem16;
+            }
             break;
         }
         break;
diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/private.h
index dfdc263f9c..6c96f72327 100644
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -609,6 +609,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
 #define vcpu_has_avx_vnni()    (ctxt->cpuid->feat.avx_vnni)
 #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
 #define vcpu_has_cmpccxadd()   (ctxt->cpuid->feat.cmpccxadd)
+#define vcpu_has_lkgs()        (ctxt->cpuid->feat.lkgs)
 #define vcpu_has_wrmsrns()     (ctxt->cpuid->feat.wrmsrns)
 #define vcpu_has_avx_ifma()    (ctxt->cpuid->feat.avx_ifma)
 #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8)
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index e58735ee95..364e6c092d 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2899,8 +2899,37 @@ x86_emulate(
                 break;
             }
             break;
-        default:
-            generate_exception_if(true, X86_EXC_UD);
+
+        case 6: /* lkgs */
+            generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2,
+                                  X86_EXC_UD);
+            generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD);
+            vcpu_must_have(lkgs);
+            fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr);
+            if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val,
+                                     ctxt)) != X86EMUL_OKAY ||
+                 (rc = ops->read_msr(MSR_GS_BASE, &sreg.base,
+                                     ctxt)) != X86EMUL_OKAY )
+                goto done;
+            dst.orig_val = sreg.base; /* Preserve current GS Base. */
+            if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg,
+                                         ctxt, ops)) != X86EMUL_OKAY )
+                goto done;
+            /* Write new base into SHADOW_GS, zero extended from GDT/LDT. */
+            if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base,
+                                      ctxt, false)) != X86EMUL_OKAY ||
+                 (sreg.base = dst.orig_val, /* Reinstate original GS Base. */
+                  (rc = ops->write_segment(x86_seg_gs, &sreg,
+                                           ctxt)) != X86EMUL_OKAY) )
+            {
+                /*
+                 * In real hardware, access to the registers cannot fail.  It
+                 * is an error in Xen if the writes fail.
+                 */
+                ASSERT_UNREACHABLE();
+                x86_emul_reset_event(ctxt);
+                generate_exception(X86_EXC_DF, 0);
+            }
             break;
         }
         break;
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index b751dbab27..a30c68b40a 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -282,7 +282,8 @@ def crunch_numbers(state):
         # superpages, PCID and PKU are only available in 4 level paging.
         # NO_LMSL indicates the absense of Long Mode Segment Limits, which
         # have been dropped in hardware.
-        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD],
+        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
+             LKGS],
 
         # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
         # standard 3DNow in the earlier K6 processors.
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/MCE: adjust S3 resume handling
Message-Id: <E1wMkan-001NlP-1k@xenbits.xenproject.org>
Date: Tue, 12 May 2026 10:44:01 +0000

commit d9b3aceae1ebe859c3aa8413bf0d90cfa508be54
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 12 08:31:31 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 12 08:31:31 2026 +0200

    x86/MCE: adjust S3 resume handling
    
    The BSP resume path calls mcheck_init() with the address of
    boot_cpu_data, thus rendering comparisons against that pointer
    ineffective. The additional "bsp" boolean needs to be used (and
    propagated as necessary) instead.
    
    While touching intel_init_thermal(), constify its 1st parameter, which
    in turn requires touching intel_thermal_supported() as well.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 xen/arch/x86/cpu/mcheck/mce_amd.c   |  4 ++--
 xen/arch/x86/cpu/mcheck/mce_intel.c | 18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
index 25c29eb3d2..bf353c9a69 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -318,7 +318,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
         mcequirk_amd_apply(quirkflag);
 
     if ( cpu_has(c, X86_FEATURE_AMD_PPIN) &&
-         (c == &boot_cpu_data || ppin_msr) )
+         (bsp || ppin_msr) )
     {
         uint64_t val;
 
@@ -333,7 +333,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_AMD_PPIN;
     }
 
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 839a0e5ba9..673e608376 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -87,7 +87,7 @@ static void cf_check intel_thermal_interrupt(void)
 }
 
 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
-static bool intel_thermal_supported(struct cpuinfo_x86 *c)
+static bool intel_thermal_supported(const struct cpuinfo_x86 *c)
 {
     if ( !cpu_has_apic )
         return false;
@@ -110,7 +110,7 @@ static void __init mcheck_intel_therm_init(void)
 }
 
 /* P4/Xeon Thermal regulation detect and init */
-static void intel_init_thermal(struct cpuinfo_x86 *c)
+static void intel_init_thermal(const struct cpuinfo_x86 *c, bool bsp)
 {
     uint64_t msr_content;
     uint32_t val;
@@ -143,7 +143,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
     if ( (msr_content & (1ULL<<3))
          && (val & APIC_DM_MASK) == APIC_DM_SMI )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal monitoring handled by SMI\n");
         return; /* -EBUSY */
     }
@@ -154,7 +154,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
     /* check whether a vector already exists, temporarily masked? */
     if ( val & APIC_VECTOR_MASK )
     {
-        if ( c == &boot_cpu_data )
+        if ( bsp )
             printk(KERN_DEBUG "Thermal LVT vector (%#x) already installed\n",
                    val & APIC_VECTOR_MASK);
         return; /* -EBUSY */
@@ -852,7 +852,7 @@ static void intel_init_mce(bool bsp)
     mce_uhandler_num = ARRAY_SIZE(intel_mce_uhandlers);
 }
 
-static void intel_init_ppin(const struct cpuinfo_x86 *c)
+static void intel_init_ppin(const struct cpuinfo_x86 *c, bool bsp)
 {
     /*
      * Even if testing the presence of the MSR would be enough, we don't
@@ -881,7 +881,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case INTEL_SAPPHIRERAPIDS_X:
     case INTEL_EMERALDRAPIDS_X:
 
-        if ( (c != &boot_cpu_data && !ppin_msr) ||
+        if ( (!bsp && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, &val) )
             return;
 
@@ -894,7 +894,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
 
         if ( !(val & PPIN_ENABLE) )
             ppin_msr = 0;
-        else if ( c == &boot_cpu_data )
+        else if ( bsp )
             ppin_msr = MSR_PPIN;
 
         break;
@@ -995,9 +995,9 @@ enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool bsp)
 
     intel_init_cmci(c);
 
-    intel_init_thermal(c);
+    intel_init_thermal(c, bsp);
 
-    intel_init_ppin(c);
+    intel_init_ppin(c, bsp);
 
     return mcheck_intel;
 }
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86emul: support LKGS
Message-Id: <E1wMkax-001Nmx-2I@xenbits.xenproject.org>
Date: Tue, 12 May 2026 10:44:11 +0000

commit a6b143e5a3a5733c12b71e7e2f5b6e9300e5920a
Author:     Jan Beulich <jbeulich@suse.com>
AuthorDate: Tue May 12 08:31:59 2026 +0200
Commit:     Jan Beulich <jbeulich@suse.com>
CommitDate: Tue May 12 08:31:59 2026 +0200

    x86emul: support LKGS
    
    Provide support for this insn, which is a prereq to FRED. CPUID-wise,
    while its and FRED's enumerators were already introduced, their dependency
    still needs adding.
    
    While adding a testcase, also add a SWAPGS one. In order to not affect
    the behavior of pre-existing tests, install write_{segment,msr} hooks
    only transiently.
    
    Signed-off-by: Jan Beulich <jbeulich@suse.com>
    Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
 tools/tests/x86_emulator/predicates.c        |  1 +
 tools/tests/x86_emulator/test_x86_emulator.c | 96 ++++++++++++++++++++++++++++
 tools/tests/x86_emulator/x86-emulate.c       |  1 +
 xen/arch/x86/x86_emulate/decode.c            |  6 +-
 xen/arch/x86/x86_emulate/private.h           |  1 +
 xen/arch/x86/x86_emulate/x86_emulate.c       | 33 +++++++++-
 xen/tools/gen-cpuid.py                       |  3 +-
 7 files changed, 137 insertions(+), 4 deletions(-)

diff --git a/tools/tests/x86_emulator/predicates.c b/tools/tests/x86_emulator/predicates.c
index 019c2ced8a..8ff2653895 100644
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -326,6 +326,7 @@ static const struct {
     { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */
     { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */
     { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */
+    { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */
     { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */
     { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */
     { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */
diff --git a/tools/tests/x86_emulator/test_x86_emulator.c b/tools/tests/x86_emulator/test_x86_emulator.c
index 20929b80c6..af29b106f1 100644
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -673,6 +673,10 @@ static int blk(
     return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt);
 }
 
+#ifdef __x86_64__
+static unsigned long gs_base, gs_base_shadow;
+#endif
+
 static int read_segment(
     enum x86_segment seg,
     struct segment_register *reg,
@@ -682,9 +686,26 @@ static int read_segment(
         return X86EMUL_UNHANDLEABLE;
     memset(reg, 0, sizeof(*reg));
     reg->p = 1;
+
     return X86EMUL_OKAY;
 }
 
+#ifdef __x86_64__
+static int write_segment(
+    enum x86_segment seg,
+    const struct segment_register *reg,
+    struct x86_emulate_ctxt *ctxt)
+{
+    if ( !is_x86_user_segment(seg) )
+        return X86EMUL_UNHANDLEABLE;
+
+    if ( seg == x86_seg_gs )
+        gs_base = reg->base;
+
+    return X86EMUL_OKAY;
+}
+#endif
+
 static int read_msr(
     unsigned int reg,
     uint64_t *val,
@@ -696,6 +717,20 @@ static int read_msr(
         *val = ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0;
         return X86EMUL_OKAY;
 
+#ifdef __x86_64__
+    case MSR_GS_BASE:
+        if ( ctxt->addr_size < 64 )
+            break;
+        *val = gs_base;
+        return X86EMUL_OKAY;
+
+    case MSR_SHADOW_GS_BASE:
+        if ( ctxt->addr_size < 64 )
+            break;
+        *val = gs_base_shadow;
+        return X86EMUL_OKAY;
+#endif
+
     case MSR_TSC_AUX:
 #define TSC_AUX_VALUE 0xCACACACA
         *val = TSC_AUX_VALUE;
@@ -705,6 +740,32 @@ static int read_msr(
     return X86EMUL_UNHANDLEABLE;
 }
 
+#ifdef __x86_64__
+static int write_msr(
+    unsigned int reg,
+    uint64_t val,
+    struct x86_emulate_ctxt *ctxt,
+    bool explicit)
+{
+    switch ( reg )
+    {
+    case MSR_GS_BASE:
+        if ( ctxt->addr_size < 64 || !is_canonical_address(val) )
+            break;
+        gs_base = val;
+        return X86EMUL_OKAY;
+
+    case MSR_SHADOW_GS_BASE:
+        if ( ctxt->addr_size < 64 || !is_canonical_address(val) )
+            break;
+        gs_base_shadow = val;
+        return X86EMUL_OKAY;
+    }
+
+    return X86EMUL_UNHANDLEABLE;
+}
+#endif
+
 #define INVPCID_ADDR 0x12345678
 #define INVPCID_PCID 0x123
 
@@ -1339,6 +1400,41 @@ int main(int argc, char **argv)
         printf("%u bytes read - ", bytes_read);
         goto fail;
     }
+    printf("okay\n");
+
+    emulops.write_segment = write_segment;
+    emulops.write_msr     = write_msr;
+
+    printf("%-40s", "Testing swapgs...");
+    instr[0] = 0x0f; instr[1] = 0x01; instr[2] = 0xf8;
+    regs.eip = (unsigned long)&instr[0];
+    gs_base = 0xffffeeeecccc8888UL;
+    gs_base_shadow = 0x0000111122224444UL;
+    rc = x86_emulate(&ctxt, &emulops);
+    if ( (rc != X86EMUL_OKAY) ||
+         (regs.eip != (unsigned long)&instr[3]) ||
+         (gs_base != 0x0000111122224444UL) ||
+         (gs_base_shadow != 0xffffeeeecccc8888UL) )
+        goto fail;
+    printf("okay\n");
+
+    printf("%-40s", "Testing lkgs 2(%rdx)...");
+    instr[0] = 0xf2; instr[1] = 0x0f; instr[2] = 0x00; instr[3] = 0x72; instr[4] = 0x02;
+    regs.eip = (unsigned long)&instr[0];
+    regs.edx = (unsigned long)res;
+    res[0]   = 0x00004444;
+    res[1]   = 0x8888cccc;
+    i = cpu_policy.extd.nscb; cpu_policy.extd.nscb = true; /* for AMD */
+    rc = x86_emulate(&ctxt, &emulops);
+    if ( (rc != X86EMUL_OKAY) ||
+         (regs.eip != (unsigned long)&instr[5]) ||
+         (gs_base != 0x0000111122224444UL) ||
+         gs_base_shadow )
+        goto fail;
+
+    cpu_policy.extd.nscb = i;
+    emulops.write_segment = NULL;
+    emulops.write_msr     = NULL;
 #endif
     printf("okay\n");
 
diff --git a/tools/tests/x86_emulator/x86-emulate.c b/tools/tests/x86_emulator/x86-emulate.c
index 379e206dd3..b22c7d6add 100644
--- a/tools/tests/x86_emulator/x86-emulate.c
+++ b/tools/tests/x86_emulator/x86-emulate.c
@@ -85,6 +85,7 @@ bool emul_test_init(void)
     cpu_policy.feat.invpcid = true;
     cpu_policy.feat.adx = true;
     cpu_policy.feat.rdpid = true;
+    cpu_policy.feat.lkgs = true;
     cpu_policy.feat.wrmsrns = true;
     cpu_policy.extd.clzero = true;
 
diff --git a/xen/arch/x86/x86_emulate/decode.c b/xen/arch/x86/x86_emulate/decode.c
index 346777422b..2c13356c4d 100644
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -745,8 +745,12 @@ decode_twobyte(struct x86_emulate_state *s,
         case 0:
             s->desc |= DstMem | SrcImplicit | Mov;
             break;
+        case 6:
+            if ( !(s->modrm_reg & 1) && mode_64bit() )
+            {
         case 2: case 4:
-            s->desc |= SrcMem16;
+                s->desc |= SrcMem16;
+            }
             break;
         }
         break;
diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/private.h
index dfdc263f9c..6c96f72327 100644
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -609,6 +609,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
 #define vcpu_has_avx_vnni()    (ctxt->cpuid->feat.avx_vnni)
 #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
 #define vcpu_has_cmpccxadd()   (ctxt->cpuid->feat.cmpccxadd)
+#define vcpu_has_lkgs()        (ctxt->cpuid->feat.lkgs)
 #define vcpu_has_wrmsrns()     (ctxt->cpuid->feat.wrmsrns)
 #define vcpu_has_avx_ifma()    (ctxt->cpuid->feat.avx_ifma)
 #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8)
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index e58735ee95..364e6c092d 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2899,8 +2899,37 @@ x86_emulate(
                 break;
             }
             break;
-        default:
-            generate_exception_if(true, X86_EXC_UD);
+
+        case 6: /* lkgs */
+            generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2,
+                                  X86_EXC_UD);
+            generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD);
+            vcpu_must_have(lkgs);
+            fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr);
+            if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val,
+                                     ctxt)) != X86EMUL_OKAY ||
+                 (rc = ops->read_msr(MSR_GS_BASE, &sreg.base,
+                                     ctxt)) != X86EMUL_OKAY )
+                goto done;
+            dst.orig_val = sreg.base; /* Preserve current GS Base. */
+            if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg,
+                                         ctxt, ops)) != X86EMUL_OKAY )
+                goto done;
+            /* Write new base into SHADOW_GS, zero extended from GDT/LDT. */
+            if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base,
+                                      ctxt, false)) != X86EMUL_OKAY ||
+                 (sreg.base = dst.orig_val, /* Reinstate original GS Base. */
+                  (rc = ops->write_segment(x86_seg_gs, &sreg,
+                                           ctxt)) != X86EMUL_OKAY) )
+            {
+                /*
+                 * In real hardware, access to the registers cannot fail.  It
+                 * is an error in Xen if the writes fail.
+                 */
+                ASSERT_UNREACHABLE();
+                x86_emul_reset_event(ctxt);
+                generate_exception(X86_EXC_DF, 0);
+            }
             break;
         }
         break;
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index b751dbab27..a30c68b40a 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -282,7 +282,8 @@ def crunch_numbers(state):
         # superpages, PCID and PKU are only available in 4 level paging.
         # NO_LMSL indicates the absense of Long Mode Segment Limits, which
         # have been dropped in hardware.
-        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD],
+        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
+             LKGS],
 
         # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
         # standard 3DNow in the earlier K6 processors.
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] xen/arm: sci: Don't create a domain with unsatisfied user requests
Message-Id: <E1wMoL4-001bKx-0o@xenbits.xenproject.org>
Date: Tue, 12 May 2026 14:44:02 +0000

commit f7b9752dc88c626192d3115ace7585b20a025433
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue May 12 09:52:55 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Tue May 12 13:31:01 2026 +0200

    xen/arm: sci: Don't create a domain with unsatisfied user requests
    
    On Arm we stay on the safe side and refuse to create a domain on user
    requests (e.g. via xl.cfg, DT options) that cannot be satisfied due to
    the feature not being compiled in. SCI fall through the crack and does not
    adhere to that i.e. a user request for SCI type other than NONE when
    CONFIG_SCMI_SMC (and thus CONFIG_ARM_SCI) is not set would be silently
    ignored. Fix it by not allowing anything else other than NONE if the
    feature is not enabled.
    
    Fixes: 10e7473d6024 ("xen/arm: scmi-smc: passthrough SCMI SMC to domain, single agent")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/dom0less-build.c           | 11 +++++++++--
 xen/arch/arm/include/asm/firmware/sci.h |  5 +++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 6f73c65e51..52cf788a45 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -273,8 +273,7 @@ static int __init domu_dt_sci_parse(struct dt_device_node *node,
 
     d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
 
-    if ( !IS_ENABLED(CONFIG_ARM_SCI) ||
-         !dt_property_read_bool(node, "xen,sci_type") )
+    if ( !dt_property_read_bool(node, "xen,sci_type") )
         return 0;
 
     ret = dt_property_read_string(node, "xen,sci_type", &sci_type);
@@ -284,7 +283,15 @@ static int __init domu_dt_sci_parse(struct dt_device_node *node,
     if ( !strcmp(sci_type, "none") )
         d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
     else if ( !strcmp(sci_type, "scmi_smc") )
+    {
+        if ( !IS_ENABLED(CONFIG_SCMI_SMC) )
+        {
+            printk(XENLOG_ERR "xen,sci_type=scmi_smc requested, but CONFIG_SCMI_SMC not set\n");
+            return -EINVAL;
+        }
+
         d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
+    }
     else
     {
         printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n",
diff --git a/xen/arch/arm/include/asm/firmware/sci.h b/xen/arch/arm/include/asm/firmware/sci.h
index 3500216bc2..485ce211c9 100644
--- a/xen/arch/arm/include/asm/firmware/sci.h
+++ b/xen/arch/arm/include/asm/firmware/sci.h
@@ -148,6 +148,8 @@ int sci_dt_finalize(struct domain *d, void *fdt);
 int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev);
 #else
 
+#include <public/arch-arm.h>
+
 static inline bool sci_domain_is_enabled(struct domain *d)
 {
     return false;
@@ -162,6 +164,9 @@ static inline int sci_domain_init(struct domain *d,
 static inline int
 sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
 {
+    if ( config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_NONE )
+        return -EINVAL;
+
     return 0;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/dom0: enable pf-fixup by default for PVH dom0
Message-Id: <E1wMphF-001gcq-2q@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:11:01 +0000

commit fa8687810af66ec37940ecc93e2ef4e9a47889a2
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Fri May 8 10:55:09 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Tue May 12 18:02:44 2026 +0200

    x86/dom0: enable pf-fixup by default for PVH dom0
    
    A non-trivial amount of issues related to PVH dom0 are fixed by enabling
    the `pf-fixup` command line option, and no issues have been reported as a
    result of its usage.  Enable the option by default to make PVH dom0 more
    robust in its default configuration.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 CHANGELOG.md                      | 2 ++
 docs/misc/xen-command-line.pandoc | 8 ++++++--
 xen/arch/x86/hvm/emulate.c        | 2 +-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index ce46020dbd..25f5a192ed 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,6 +7,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 ## [4.22.0 UNRELEASED](https://xenbits.xenproject.org/gitweb/?p=xen.git;a=shortlog;h=staging) - TBD
 
 ### Changed
+ - On x86:
+   - Enable pf-fixup option by default for PVH dom0.
 
 ### Added
  - Support for per-domain Xenstore quota in C xenstored (includes
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 6c77129732..2da90548d8 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -849,7 +849,7 @@ Controls for how dom0 is constructed on x86 systems.
     If using this option is necessary to fix an issue, please report a bug.
 
 *   The `pf-fixup` boolean is only applicable when using a PVH dom0 and
-    defaults to false.
+    defaults to true.
 
     When running dom0 in PVH mode the dom0 kernel has no way to map MMIO
     regions into its physical memory map, such mode relies on Xen dom0 builder
@@ -857,10 +857,14 @@ Controls for how dom0 is constructed on x86 systems.
     access.  However Xen doesn't have a complete picture of the host memory
     map, due to not being able to process ACPI dynamic tables.
 
-    The `pf-fixup` option allows Xen to attempt to add missing MMIO regions
+    The `pf-fixup` option causes Xen to attempt to add missing MMIO regions
     to the dom0 physical memory map in response to page-faults generated by
     dom0 trying to access unpopulated entries in the memory map.
 
+    Users having to disable the feature to boot in PVH dom0 mode should report
+    it to the xen-devel mailing list, together with Xen and dom0 output with the
+    option enabled.
+
 Enables features on dom0 on Arm systems.
 
 *   The `sve` integer parameter enables Arm SVE usage for Dom0 and sets the
diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index f3aae158e9..bb1bb03ac4 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -165,7 +165,7 @@ void hvmemul_cancel(struct vcpu *v)
     hvmemul_cache_disable(v);
 }
 
-bool __ro_after_init opt_dom0_pf_fixup;
+bool __ro_after_init opt_dom0_pf_fixup = true;
 static int hwdom_fixup_p2m(paddr_t addr)
 {
     unsigned long gfn = paddr_to_pfn(addr);
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMphP-001ge4-38@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:11:11 +0000

commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 12 17:05:30 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 712734a6e7..70783c9a0a 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1015,11 +1015,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.family == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.family == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.family == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.21] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMpru-001hPx-0h@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:02 +0000

commit 8af05b49176dc22db12d6743a927899561314ec8
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 15:30:12 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 1bb0766ebf..b5bf2b732e 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1116,11 +1116,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.21


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.20] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMps4-001hRB-1Y@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:12 +0000

commit 3ed365e3f9ee281a8b34d65b6f5a4bf04bc871e4
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 15:31:11 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 43883e04db..3914032269 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1050,11 +1050,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.20


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.19] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMpsE-001hS4-2P@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:22 +0000

commit 8056c4032f2956041b0c0a3d31a12b474caa61de
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 15:32:52 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 12876de1df..3416fb1a93 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1050,11 +1050,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.18] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMpsP-001hSt-00@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:33 +0000

commit 581a10f8846768920e7f809e1c51cf2a9f13cbce
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 15:32:57 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 43cd3ae9ba..89284b740b 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1049,11 +1049,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.18


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.17] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1wMpsZ-001hUL-1M@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:43 +0000

commit 550d632f9b7e2599b8485246aa33d7d01cb95d47
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Mon Mar 25 15:14:46 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 16:07:05 2026 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit a1746cd4434dd27ca2da8430dfb10edc76264bb3)
---
 docs/misc/xen-command-line.pandoc           |  9 +++++-
 xen/arch/x86/cpu-policy.c                   | 21 +++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 47 +++++++++++++++++++++++------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 94 insertions(+), 18 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 4f2907eb67..ad80277326 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2330,7 +2330,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2479,6 +2479,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index f259c77435..9224c36d81 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __ro_after_init     raw_cpu_policy;
@@ -650,6 +651,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 3312d896dd..8c4e50de45 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1018,16 +1018,33 @@ static void amd_init_fp_cfg(const struct cpuinfo_x86 *c)
     wrmsrl(MSR_AMD64_FP_CFG, val | new);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1036,7 +1053,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1314,7 +1331,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index bed0ab7b21..db3db08a54 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -391,6 +391,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102c
 #define MSR_AMD64_BP_CFG		0xc001102e
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 60844b755d..b7349ac898 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -102,6 +102,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 5005f0acdd..b71fe0a4ec 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -95,6 +95,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -155,6 +156,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -375,6 +377,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -517,7 +521,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -542,11 +546,12 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
            (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "",
            (e21c & cpufeat_mask(X86_FEATURE_TSA_SQ_NO))      ? " TSA_SQ_NO"      : "",
            (e21c & cpufeat_mask(X86_FEATURE_TSA_L1_NO))      ? " TSA_L1_NO"      : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -566,6 +571,7 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
            (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "",
            (e21a & cpufeat_mask(X86_FEATURE_VERW_CLEAR))     ? " VERW_CLEAR"     : "");
 
     /* Compiled-in support which pertains to mitigations. */
@@ -1138,7 +1144,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1163,22 +1169,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 42db132b4c..12ca3efc5c 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -289,7 +289,9 @@ XEN_CPUFEATURE(NSCB,               11*32+ 6) /*A  Null Selector Clears Base (and
 XEN_CPUFEATURE(AUTO_IBRS,          11*32+ 8) /*   Automatic IBRS */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.17


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen staging-4.17] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMpsj-001hVe-1e@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:22:53 +0000

commit caf651fdbcad3b3ae798172b46953ea1aa08a646
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 16:07:50 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 8c4e50de45..86268e8619 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1022,11 +1022,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.17


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.17] x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
Message-Id: <E1wMqDC-001jEo-1K@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:44:02 +0000

commit 550d632f9b7e2599b8485246aa33d7d01cb95d47
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Mon Mar 25 15:14:46 2024 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 16:07:05 2026 +0100

    x86/spec-ctrl: Support for SRSO_U/S_NO and SRSO_MSR_FIX
    
    AMD have updated the SRSO whitepaper[1] with further information.  These
    features exist on AMD Zen5 CPUs and are necessary for Xen to use.
    
    The two features are in principle unrelated:
    
     * SRSO_U/S_NO is an enumeration saying that SRSO attacks can't cross the
       User(CPL3) / Supervisor(CPL<3) boundary.  i.e. Xen don't need to use
       IBPB-on-entry for PV64.  PV32 guests are explicitly unsupported for
       speculative issues, and excluded from consideration for simplicity.
    
     * SRSO_MSR_FIX is an enumeration identifying that the BP_SPEC_REDUCE bit is
       available in MSR_BP_CFG.  When set, SRSO attacks can't cross the host/guest
       boundary.  i.e. Xen don't need to use IBPB-on-entry for HVM.
    
    Extend ibpb_calculations() to account for these when calculating
    opt_ibpb_entry_{pv,hvm} defaults.  Add a `bp-spec-reduce=<bool>` option to
    control the use of BP_SPEC_REDUCE, with it active by default.
    
    Because MSR_BP_CFG is core-scoped with a race condition updating it, repurpose
    amd_check_erratum_1485() into amd_check_bp_cfg() and calculate all updates at
    once.
    
    Xen also needs to to advertise SRSO_U/S_NO to guests to allow the guest kernel
    to skip SRSO mitigations too:
    
     * This is trivial for HVM guests.  It is also is accurate for PV32 guests
       too, but we have already excluded them from consideration, and do so again
       here to simplify the policy logic.
    
     * As written, SRSO_U/S_NO does not help for the PV64 user->kernel boundary.
       However, after discussing with AMD, an implementation detail of having
       BP_SPEC_REDUCE active causes the PV64 user->kernel boundary to have the
       property described by SRSO_U/S_NO, so we can advertise SRSO_U/S_NO to
       guests when the BP_SPEC_REDUCE precondition is met.
    
    Finally, fix a typo in the SRSO_NO's comment.
    
    [1] https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit a1746cd4434dd27ca2da8430dfb10edc76264bb3)
---
 docs/misc/xen-command-line.pandoc           |  9 +++++-
 xen/arch/x86/cpu-policy.c                   | 21 +++++++++++++
 xen/arch/x86/cpu/amd.c                      | 29 ++++++++++++++----
 xen/arch/x86/include/asm/msr-index.h        |  1 +
 xen/arch/x86/include/asm/spec_ctrl.h        |  1 +
 xen/arch/x86/spec_ctrl.c                    | 47 +++++++++++++++++++++++------
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++-
 7 files changed, 94 insertions(+), 18 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 4f2907eb67..ad80277326 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2330,7 +2330,7 @@ By default SSBD will be mitigated at runtime (i.e `ssbd=runtime`).
 >              {ibrs,ibpb,ssbd,psfd,
 >              eager-fpu,l1d-flush,branch-harden,srb-lock,
 >              unpriv-mmio,gds-mit,div-scrub,lock-harden,
->              bhi-dis-s}=<bool> ]`
+>              bhi-dis-s,bp-spec-reduce}=<bool> ]`
 
 Controls for speculative execution sidechannel mitigations.  By default, Xen
 will pick the most appropriate mitigations based on compiled in support,
@@ -2479,6 +2479,13 @@ boolean can be used to force or prevent Xen from using speculation barriers to
 protect lock critical regions.  This mitigation won't be engaged by default,
 and needs to be explicitly enabled on the command line.
 
+On hardware supporting SRSO_MSR_FIX, the `bp-spec-reduce=` option can be used
+to force or prevent Xen from using MSR_BP_CFG.BP_SPEC_REDUCE to mitigate the
+SRSO (Speculative Return Stack Overflow) vulnerability.  Xen will use
+bp-spec-reduce when available, as it is preferable to using `ibpb-entry=hvm`
+to mitigate SRSO for HVM guests, and because it is a prerequisite to advertise
+SRSO_U/S_NO to PV guests.
+
 ### sync_console
 > `= <boolean>`
 
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index f259c77435..9224c36d81 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -14,6 +14,7 @@
 #include <asm/msr-index.h>
 #include <asm/paging.h>
 #include <asm/setup.h>
+#include <asm/spec_ctrl.h>
 #include <asm/xstate.h>
 
 struct cpu_policy __ro_after_init     raw_cpu_policy;
@@ -650,6 +651,26 @@ static void __init calculate_pv_max_policy(void)
         __clear_bit(X86_FEATURE_IBRS, fs);
     }
 
+    /*
+     * SRSO_U/S_NO means that the CPU is not vulnerable to SRSO attacks across
+     * the User (CPL3) / Supervisor (CPL<3) boundary.
+     *
+     * PV32 guests are unsupported for speculative issues, and excluded from
+     * consideration for simplicity.
+     *
+     * The PV64 user/kernel boundary is CPL3 on both sides, so SRSO_U/S_NO
+     * won't convey the meaning that a PV kernel expects.
+     *
+     * After discussions with AMD, an implementation detail of having
+     * BP_SPEC_REDUCE active causes the PV64 user/kernel boundary to have a
+     * property compatible with the meaning of SRSO_U/S_NO.
+     *
+     * If BP_SPEC_REDUCE isn't active, remove SRSO_U/S_NO from the PV max
+     * policy, which will cause it to filter out of PV default too.
+     */
+    if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+        __clear_bit(X86_FEATURE_SRSO_US_NO, fs);
+
     guest_common_max_feature_adjustments(fs);
     guest_common_feature_adjustments(fs);
 
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 3312d896dd..8c4e50de45 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1018,16 +1018,33 @@ static void amd_init_fp_cfg(const struct cpuinfo_x86 *c)
     wrmsrl(MSR_AMD64_FP_CFG, val | new);
 }
 
-static void amd_check_erratum_1485(void)
+static void amd_check_bp_cfg(void)
 {
-	uint64_t val, chickenbit = (1 << 5);
+	uint64_t val, new = 0;
 
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x19 || !is_zen4_uarch())
+	/*
+	 * AMD Erratum #1485.  Set bit 5, as instructed.
+	 */
+	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+		new |= (1 << 5);
+
+	/*
+	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
+	 * default.  This lets us do two things:
+	 *
+	 * 1) Avoid IBPB-on-entry to mitigate SRSO attacks from HVM guests.
+	 * 2) Advertise SRSO_US_NO to PV guests.
+	 */
+	if (boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) && opt_bp_spec_reduce)
+		new |= BP_CFG_SPEC_REDUCE;
+
+	/* Avoid reading BP_CFG if we don't intend to change anything. */
+	if (!new)
 		return;
 
 	rdmsrl(MSR_AMD64_BP_CFG, val);
 
-	if (val & chickenbit)
+	if ((val & new) == new)
 		return;
 
 	/*
@@ -1036,7 +1053,7 @@ static void amd_check_erratum_1485(void)
 	 * same time before the chickenbit is set. It's benign because the
 	 * value being written is the same on both.
 	 */
-	wrmsrl(MSR_AMD64_BP_CFG, val | chickenbit);
+	wrmsrl(MSR_AMD64_BP_CFG, val | new);
 }
 
 static void cf_check init_amd(struct cpuinfo_x86 *c)
@@ -1314,7 +1331,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		disable_c1_ramping();
 
 	amd_check_zenbleed();
-	amd_check_erratum_1485();
+	amd_check_bp_cfg();
 
 	if (fam17_c6_disabled)
 		fam17_disable_c6(NULL);
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index bed0ab7b21..db3db08a54 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -391,6 +391,7 @@
 #define AMD64_DE_CFG_LFENCE_SERIALISE	(_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG		0xc001102c
 #define MSR_AMD64_BP_CFG		0xc001102e
+#define  BP_CFG_SPEC_REDUCE		(_AC(1, ULL) <<  4)
 #define MSR_AMD64_DE_CFG2		0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 60844b755d..b7349ac898 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -102,6 +102,7 @@ extern int8_t opt_xpti_hwdom, opt_xpti_domu;
 
 extern bool cpu_has_bug_l1tf;
 extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu;
+extern bool opt_bp_spec_reduce;
 
 /*
  * The L1D address mask, which might be wider than reported in CPUID, and the
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 5005f0acdd..b71fe0a4ec 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -95,6 +95,7 @@ static bool __initdata opt_unpriv_mmio;
 static bool __ro_after_init opt_verw_mmio;
 static int8_t __initdata opt_gds_mit = -1;
 static int8_t __initdata opt_div_scrub = -1;
+bool __ro_after_init opt_bp_spec_reduce = true;
 
 static int __init cf_check parse_spec_ctrl(const char *s)
 {
@@ -155,6 +156,7 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_unpriv_mmio = false;
             opt_gds_mit = 0;
             opt_div_scrub = 0;
+            opt_bp_spec_reduce = false;
         }
         else if ( val > 0 )
             rc = -EINVAL;
@@ -375,6 +377,8 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             opt_gds_mit = val;
         else if ( (val = parse_boolean("div-scrub", s, ss)) >= 0 )
             opt_div_scrub = val;
+        else if ( (val = parse_boolean("bp-spec-reduce", s, ss)) >= 0 )
+            opt_bp_spec_reduce = val;
         else
             rc = -EINVAL;
 
@@ -517,7 +521,7 @@ static void __init print_details(enum ind_thunk thunk)
      * Hardware read-only information, stating immunity to certain issues, or
      * suggestions of which mitigation to use.
      */
-    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (caps & ARCH_CAPS_RDCL_NO)                        ? " RDCL_NO"        : "",
            (caps & ARCH_CAPS_EIBRS)                          ? " EIBRS"          : "",
            (caps & ARCH_CAPS_RSBA)                           ? " RSBA"           : "",
@@ -542,11 +546,12 @@ static void __init print_details(enum ind_thunk thunk)
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB_RET))       ? " IBPB_RET"       : "",
            (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE))    ? " IBPB_BRTYPE"    : "",
            (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO))        ? " SRSO_NO"        : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_US_NO))     ? " SRSO_US_NO"     : "",
            (e21c & cpufeat_mask(X86_FEATURE_TSA_SQ_NO))      ? " TSA_SQ_NO"      : "",
            (e21c & cpufeat_mask(X86_FEATURE_TSA_L1_NO))      ? " TSA_L1_NO"      : "");
 
     /* Hardware features which need driving to mitigate issues. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB)) ||
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB))          ? " IBPB"           : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBRS)) ||
@@ -566,6 +571,7 @@ static void __init print_details(enum ind_thunk thunk)
            (caps & ARCH_CAPS_GDS_CTRL)                       ? " GDS_CTRL"       : "",
            (caps & ARCH_CAPS_RFDS_CLEAR)                     ? " RFDS_CLEAR"     : "",
            (e21a & cpufeat_mask(X86_FEATURE_SBPB))           ? " SBPB"           : "",
+           (e21a & cpufeat_mask(X86_FEATURE_SRSO_MSR_FIX))   ? " SRSO_MSR_FIX"   : "",
            (e21a & cpufeat_mask(X86_FEATURE_VERW_CLEAR))     ? " VERW_CLEAR"     : "");
 
     /* Compiled-in support which pertains to mitigations. */
@@ -1138,7 +1144,7 @@ static void __init div_calculations(bool hw_smt_enabled)
 
 static void __init ibpb_calculations(void)
 {
-    bool def_ibpb_entry = false;
+    bool def_ibpb_entry_pv = false, def_ibpb_entry_hvm = false;
 
     /* Check we have hardware IBPB support before using it... */
     if ( !boot_cpu_has(X86_FEATURE_IBRSB) && !boot_cpu_has(X86_FEATURE_IBPB) )
@@ -1163,22 +1169,43 @@ static void __init ibpb_calculations(void)
          * Confusion.  Mitigate with IBPB-on-entry.
          */
         if ( !boot_cpu_has(X86_FEATURE_BTC_NO) )
-            def_ibpb_entry = true;
+            def_ibpb_entry_pv = def_ibpb_entry_hvm = true;
 
         /*
-         * Further to BTC, Zen3/4 CPUs suffer from Speculative Return Stack
-         * Overflow in most configurations.  Mitigate with IBPB-on-entry if we
-         * have the microcode that makes this an effective option.
+         * In addition to BTC, Zen3 and later CPUs suffer from Speculative
+         * Return Stack Overflow in most configurations.  If we have microcode
+         * that makes IBPB-on-entry an effective mitigation, see about using
+         * it.
          */
         if ( !boot_cpu_has(X86_FEATURE_SRSO_NO) &&
              boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) )
-            def_ibpb_entry = true;
+        {
+            /*
+             * SRSO_U/S_NO is a subset of SRSO_NO, identifying that SRSO isn't
+             * possible across the User (CPL3) / Supervisor (CPL<3) boundary.
+             *
+             * Ignoring PV32 (not security supported for speculative issues),
+             * this means we only need to use IBPB-on-entry for PV guests on
+             * hardware which doesn't enumerate SRSO_US_NO.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_US_NO) )
+                def_ibpb_entry_pv = true;
+
+            /*
+             * SRSO_MSR_FIX enumerates that we can use MSR_BP_CFG.SPEC_REDUCE
+             * to mitigate SRSO across the host/guest boundary.  We only need
+             * to use IBPB-on-entry for HVM guests if we haven't enabled this
+             * control.
+             */
+            if ( !boot_cpu_has(X86_FEATURE_SRSO_MSR_FIX) || !opt_bp_spec_reduce )
+                def_ibpb_entry_hvm = true;
+        }
     }
 
     if ( opt_ibpb_entry_pv == -1 )
-        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry;
+        opt_ibpb_entry_pv = IS_ENABLED(CONFIG_PV) && def_ibpb_entry_pv;
     if ( opt_ibpb_entry_hvm == -1 )
-        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry;
+        opt_ibpb_entry_hvm = IS_ENABLED(CONFIG_HVM) && def_ibpb_entry_hvm;
 
     if ( opt_ibpb_entry_pv )
     {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 42db132b4c..12ca3efc5c 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -289,7 +289,9 @@ XEN_CPUFEATURE(NSCB,               11*32+ 6) /*A  Null Selector Clears Base (and
 XEN_CPUFEATURE(AUTO_IBRS,          11*32+ 8) /*   Automatic IBRS */
 XEN_CPUFEATURE(SBPB,               11*32+27) /*A  Selective Branch Predictor Barrier */
 XEN_CPUFEATURE(IBPB_BRTYPE,        11*32+28) /*A  IBPB flushes Branch Type predictions too */
-XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulnerable to Speculative Return Stack Overflow */
+XEN_CPUFEATURE(SRSO_US_NO,         11*32+30) /*A! Hardware not vulnerable to SRSO across the User/Supervisor boundary */
+XEN_CPUFEATURE(SRSO_MSR_FIX,       11*32+31) /*   MSR_BP_CFG.BP_SPEC_REDUCE available */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
 XEN_CPUFEATURE(INTEL_PPIN,         12*32+ 0) /*   Protected Processor Inventory Number */
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.17


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen stable-4.17] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMqDM-001jGW-1n@xenbits.xenproject.org>
Date: Tue, 12 May 2026 16:44:12 +0000

commit caf651fdbcad3b3ae798172b46953ea1aa08a646
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Wed May 6 16:07:50 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
    (cherry picked from commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb)
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 8c4e50de45..86268e8619 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1022,11 +1022,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.x86 == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.17


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] xen/arm: sci: Don't create a domain with unsatisfied user requests
Message-Id: <E1wMsFy-001x00-0n@xenbits.xenproject.org>
Date: Tue, 12 May 2026 18:55:02 +0000

commit f7b9752dc88c626192d3115ace7585b20a025433
Author:     Michal Orzel <michal.orzel@amd.com>
AuthorDate: Tue May 12 09:52:55 2026 +0200
Commit:     Michal Orzel <michal.orzel@amd.com>
CommitDate: Tue May 12 13:31:01 2026 +0200

    xen/arm: sci: Don't create a domain with unsatisfied user requests
    
    On Arm we stay on the safe side and refuse to create a domain on user
    requests (e.g. via xl.cfg, DT options) that cannot be satisfied due to
    the feature not being compiled in. SCI fall through the crack and does not
    adhere to that i.e. a user request for SCI type other than NONE when
    CONFIG_SCMI_SMC (and thus CONFIG_ARM_SCI) is not set would be silently
    ignored. Fix it by not allowing anything else other than NONE if the
    feature is not enabled.
    
    Fixes: 10e7473d6024 ("xen/arm: scmi-smc: passthrough SCMI SMC to domain, single agent")
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
    Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
 xen/arch/arm/dom0less-build.c           | 11 +++++++++--
 xen/arch/arm/include/asm/firmware/sci.h |  5 +++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 6f73c65e51..52cf788a45 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -273,8 +273,7 @@ static int __init domu_dt_sci_parse(struct dt_device_node *node,
 
     d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
 
-    if ( !IS_ENABLED(CONFIG_ARM_SCI) ||
-         !dt_property_read_bool(node, "xen,sci_type") )
+    if ( !dt_property_read_bool(node, "xen,sci_type") )
         return 0;
 
     ret = dt_property_read_string(node, "xen,sci_type", &sci_type);
@@ -284,7 +283,15 @@ static int __init domu_dt_sci_parse(struct dt_device_node *node,
     if ( !strcmp(sci_type, "none") )
         d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
     else if ( !strcmp(sci_type, "scmi_smc") )
+    {
+        if ( !IS_ENABLED(CONFIG_SCMI_SMC) )
+        {
+            printk(XENLOG_ERR "xen,sci_type=scmi_smc requested, but CONFIG_SCMI_SMC not set\n");
+            return -EINVAL;
+        }
+
         d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
+    }
     else
     {
         printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n",
diff --git a/xen/arch/arm/include/asm/firmware/sci.h b/xen/arch/arm/include/asm/firmware/sci.h
index 3500216bc2..485ce211c9 100644
--- a/xen/arch/arm/include/asm/firmware/sci.h
+++ b/xen/arch/arm/include/asm/firmware/sci.h
@@ -148,6 +148,8 @@ int sci_dt_finalize(struct domain *d, void *fdt);
 int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev);
 #else
 
+#include <public/arch-arm.h>
+
 static inline bool sci_domain_is_enabled(struct domain *d)
 {
     return false;
@@ -162,6 +164,9 @@ static inline int sci_domain_init(struct domain *d,
 static inline int
 sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
 {
+    if ( config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_NONE )
+        return -EINVAL;
+
     return 0;
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/dom0: enable pf-fixup by default for PVH dom0
Message-Id: <E1wMsG8-001x0S-1F@xenbits.xenproject.org>
Date: Tue, 12 May 2026 18:55:12 +0000

commit fa8687810af66ec37940ecc93e2ef4e9a47889a2
Author:     Roger Pau Monne <roger.pau@citrix.com>
AuthorDate: Fri May 8 10:55:09 2026 +0200
Commit:     Roger Pau Monne <roger.pau@citrix.com>
CommitDate: Tue May 12 18:02:44 2026 +0200

    x86/dom0: enable pf-fixup by default for PVH dom0
    
    A non-trivial amount of issues related to PVH dom0 are fixed by enabling
    the `pf-fixup` command line option, and no issues have been reported as a
    result of its usage.  Enable the option by default to make PVH dom0 more
    robust in its default configuration.
    
    Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
    Reviewed-by: Jan Beulich <jbeulich@suse.com>
    Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
    Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 CHANGELOG.md                      | 2 ++
 docs/misc/xen-command-line.pandoc | 8 ++++++--
 xen/arch/x86/hvm/emulate.c        | 2 +-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index ce46020dbd..25f5a192ed 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,6 +7,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 ## [4.22.0 UNRELEASED](https://xenbits.xenproject.org/gitweb/?p=xen.git;a=shortlog;h=staging) - TBD
 
 ### Changed
+ - On x86:
+   - Enable pf-fixup option by default for PVH dom0.
 
 ### Added
  - Support for per-domain Xenstore quota in C xenstored (includes
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 6c77129732..2da90548d8 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -849,7 +849,7 @@ Controls for how dom0 is constructed on x86 systems.
     If using this option is necessary to fix an issue, please report a bug.
 
 *   The `pf-fixup` boolean is only applicable when using a PVH dom0 and
-    defaults to false.
+    defaults to true.
 
     When running dom0 in PVH mode the dom0 kernel has no way to map MMIO
     regions into its physical memory map, such mode relies on Xen dom0 builder
@@ -857,10 +857,14 @@ Controls for how dom0 is constructed on x86 systems.
     access.  However Xen doesn't have a complete picture of the host memory
     map, due to not being able to process ACPI dynamic tables.
 
-    The `pf-fixup` option allows Xen to attempt to add missing MMIO regions
+    The `pf-fixup` option causes Xen to attempt to add missing MMIO regions
     to the dom0 physical memory map in response to page-faults generated by
     dom0 trying to access unpopulated entries in the memory map.
 
+    Users having to disable the feature to boot in PVH dom0 mode should report
+    it to the xen-devel mailing list, together with Xen and dom0 output with the
+    option enabled.
+
 Enables features on dom0 on Arm systems.
 
 *   The `sve` integer parameter enables Arm SVE usage for Dom0 and sets the
diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index f3aae158e9..bb1bb03ac4 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -165,7 +165,7 @@ void hvmemul_cancel(struct vcpu *v)
     hvmemul_cache_disable(v);
 }
 
-bool __ro_after_init opt_dom0_pf_fixup;
+bool __ro_after_init opt_dom0_pf_fixup = true;
 static int hwdom_fixup_p2m(paddr_t addr)
 {
     unsigned long gfn = paddr_to_pfn(addr);
--
generated by git-patchbot for /home/xen/git/xen.git#master


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From: patchbot@xen.org
To: xen-changelog@lists.xenproject.org
Reply-To: xen-devel@lists.xenproject.org
Subject: [xen master] x86/amd: Mitigate AMD-SN-7052
Message-Id: <E1wMsGI-001x2n-1X@xenbits.xenproject.org>
Date: Tue, 12 May 2026 18:55:22 +0000

commit 8070bdfa7220e772fae248abd3cbf5e87fc0fefb
Author:     Andrew Cooper <andrew.cooper3@citrix.com>
AuthorDate: Tue Nov 4 18:08:07 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@citrix.com>
CommitDate: Tue May 12 17:05:30 2026 +0100

    x86/amd: Mitigate AMD-SN-7052
    
    This is XSA-490 / CVE-2025-54518.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
    Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 712734a6e7..70783c9a0a 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1015,11 +1015,25 @@ static void amd_check_bp_cfg(void)
 {
 	uint64_t val, new = 0;
 
-	/*
-	 * AMD Erratum #1485.  Set bit 5, as instructed.
-	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.family == 0x19 && is_zen4_uarch())
-		new |= (1 << 5);
+	if (!cpu_has_hypervisor) {
+		/*
+		 * AMD Erratum #1485.  If SMT is enabled and STIBP disabled,
+		 * the CPU may fetch incorrect instruction bytes.
+		 *
+		 * Set bit 5, as instructed.
+		 */
+		if (boot_cpu_data.family == 0x19 && is_zen4_uarch())
+			new |= (1 << 5);
+
+		/*
+		 * AMD SB-7052.  CPU OP Cache corruption, causing instructions
+		 * to be executed at a higher privilege.
+		 *
+		 * Set bit 33, as instructed.
+		 */
+		if (boot_cpu_data.family == 0x17 && is_zen2_uarch())
+			new |= (1UL << 33);
+	}
 
 	/*
 	 * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by
--
generated by git-patchbot for /home/xen/git/xen.git#master


